- EMC clock have standard peripheral clock block. Use it. - Implement full frequency set method for PLLD2. This PLL is used as HDMI pixel clock so we must be able to set it to wide range of frequencies, within 5% tolerance allowed by HDMI specification. Due to this, full state space search (over m, n, p fields) is necessary. MFC after: 3 weeks
610 lines
17 KiB
C
610 lines
17 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/kobj.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <gnu/dts/include/dt-bindings/clock/tegra124-car.h>
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#include "clkdev_if.h"
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#include "hwreset_if.h"
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#include "tegra124_car.h"
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-car", 1},
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{NULL, 0},
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};
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#define PLIST(x) static const char *x[]
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/* Pure multiplexer. */
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#define MUX(_id, cname, plists, o, s, w) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = plists, \
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.clkdef.parent_cnt = nitems(plists), \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.shift = s, \
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.width = w, \
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}
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/* Fractional divider (7.1). */
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#define DIV7_1(_id, cname, plist, o, s) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){plist}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.i_shift = (s) + 1, \
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.i_width = 7, \
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.f_shift = s, \
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.f_width = 1, \
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}
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/* Integer divider. */
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#define DIV(_id, cname, plist, o, s, w, f) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){plist}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.i_shift = s, \
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.i_width = w, \
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.div_flags = f, \
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}
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/* Gate in PLL block. */
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#define GATE_PLL(_id, cname, plist, o, s) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){plist}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.shift = s, \
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.mask = 3, \
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.on_value = 3, \
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.off_value = 0, \
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}
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/* Standard gate. */
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#define GATE(_id, cname, plist, o, s) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){plist}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.shift = s, \
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.mask = 1, \
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.on_value = 1, \
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.off_value = 0, \
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}
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/* Inverted gate. */
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#define GATE_INV(_id, cname, plist, o, s) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){plist}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.offset = o, \
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.shift = s, \
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.mask = 1, \
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.on_value = 0, \
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.off_value = 1, \
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}
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/* Fixed rate clock. */
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#define FRATE(_id, cname, _freq) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = NULL, \
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.clkdef.parent_cnt = 0, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.freq = _freq, \
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}
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/* Fixed rate multipier/divider. */
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#define FACT(_id, cname, pname, _mult, _div) \
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{ \
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.clkdef.id = _id, \
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.clkdef.name = cname, \
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.clkdef.parent_names = (const char *[]){pname}, \
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.clkdef.parent_cnt = 1, \
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.clkdef.flags = CLK_NODE_STATIC_STRINGS, \
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.mult = _mult, \
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.div = _div, \
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}
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static uint32_t osc_freqs[16] = {
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[0] = 13000000,
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[1] = 16800000,
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[4] = 19200000,
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[5] = 38400000,
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[8] = 12000000,
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[9] = 48000000,
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[12] = 260000000,
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};
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/* Parent lists. */
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PLIST(mux_pll_srcs) = {"osc_div_clk", NULL, "pllP_out0", NULL}; /* FIXME */
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PLIST(mux_plle_src1) = {"osc_div_clk", "pllP_out0"};
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PLIST(mux_plle_src) = {"pllE_src1", "pllREFE_out"};
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PLIST(mux_plld_out0_plld2_out0) = {"pllD_out0", "pllD2_out0"};
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PLIST(mux_xusb_hs) = {"xusb_ss_div2", "pllU_60"};
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PLIST(mux_xusb_ss) = {"pc_xusb_ss", "osc_div_clk"};
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/* Clocks ajusted online. */
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static struct clk_fixed_def fixed_clk_m =
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FRATE(TEGRA124_CLK_CLK_M, "clk_m", 12000000);
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static struct clk_fixed_def fixed_osc_div_clk =
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FACT(0, "osc_div_clk", "clk_m", 1, 1);
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static struct clk_fixed_def tegra124_fixed_clks[] = {
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/* Core clocks. */
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FRATE(0, "clk_s", 32768),
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FACT(0, "clk_m_div2", "clk_m", 1, 2),
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FACT(0, "clk_m_div4", "clk_m", 1, 3),
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FACT(0, "pllU_60", "pllU_out", 1, 8),
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FACT(0, "pllU_48", "pllU_out", 1, 10),
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FACT(0, "pllU_12", "pllU_out", 1, 40),
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FACT(TEGRA124_CLK_PLL_D_OUT0, "pllD_out0", "pllD_out", 1, 2),
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FACT(TEGRA124_CLK_PLL_D2_OUT0, "pllD2_out0", "pllD2_out", 1, 1),
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FACT(0, "pllX_out0", "pllX_out", 1, 2),
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FACT(0, "pllC_UD", "pllC_out0", 1, 1),
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FACT(0, "pllM_UD", "pllM_out0", 1, 1),
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/* Audio clocks. */
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FRATE(0, "audio0", 10000000),
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FRATE(0, "audio1", 10000000),
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FRATE(0, "audio2", 10000000),
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FRATE(0, "audio3", 10000000),
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FRATE(0, "audio4", 10000000),
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FRATE(0, "ext_vimclk", 10000000),
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/* XUSB */
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FACT(TEGRA124_CLK_XUSB_SS_DIV2, "xusb_ss_div2", "xusb_ss", 1, 2),
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};
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static struct clk_mux_def tegra124_mux_clks[] = {
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/* Core clocks. */
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MUX(0, "pllD2_src", mux_pll_srcs, PLLD2_BASE, 25, 2),
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MUX(0, "pllDP_src", mux_pll_srcs, PLLDP_BASE, 25, 2),
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MUX(0, "pllC4_src", mux_pll_srcs, PLLC4_BASE, 25, 2),
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MUX(0, "pllE_src1", mux_plle_src1, PLLE_AUX, 2, 1),
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MUX(0, "pllE_src", mux_plle_src, PLLE_AUX, 28, 1),
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/* Base peripheral clocks. */
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MUX(0, "dsia_mux", mux_plld_out0_plld2_out0, PLLD_BASE, 25, 1),
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MUX(0, "dsib_mux", mux_plld_out0_plld2_out0, PLLD2_BASE, 25, 1),
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/* USB. */
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MUX(TEGRA124_CLK_XUSB_HS_SRC, "xusb_hs", mux_xusb_hs, CLK_SOURCE_XUSB_SS, 25, 1),
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MUX(0, "xusb_ss_mux", mux_xusb_ss, CLK_SOURCE_XUSB_SS, 24, 1),
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};
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static struct clk_gate_def tegra124_gate_clks[] = {
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/* Core clocks. */
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GATE_PLL(0, "pllC_out1", "pllC_out1_div", PLLC_OUT, 0),
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GATE_PLL(0, "pllM_out1", "pllM_out1_div", PLLM_OUT, 0),
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GATE_PLL(TEGRA124_CLK_PLL_U_480M, "pllU_480", "pllU_out", PLLU_BASE, 22),
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GATE_PLL(0, "pllP_outX0", "pllP_outX0_div", PLLP_RESHIFT, 0),
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GATE_PLL(0, "pllP_out1", "pllP_out1_div", PLLP_OUTA, 0),
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GATE_PLL(0, "pllP_out2", "pllP_out2_div", PLLP_OUTA, 16),
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GATE_PLL(0, "pllP_out3", "pllP_out3_div", PLLP_OUTB, 0),
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GATE_PLL(0, "pllP_out4", "pllP_out4_div", PLLP_OUTB, 16),
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GATE_PLL(0, "pllP_out5", "pllP_out5_div", PLLP_OUTC, 16),
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GATE_PLL(0, "pllA_out0", "pllA_out1_div", PLLA_OUT, 0),
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/* Base peripheral clocks. */
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GATE(TEGRA124_CLK_CML0, "cml0", "pllE_out0", PLLE_AUX, 0),
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GATE(TEGRA124_CLK_CML1, "cml1", "pllE_out0", PLLE_AUX, 1),
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GATE_INV(TEGRA124_CLK_HCLK, "hclk", "hclk_div", CLK_SYSTEM_RATE, 7),
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GATE_INV(TEGRA124_CLK_PCLK, "pclk", "pclk_div", CLK_SYSTEM_RATE, 3),
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};
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static struct clk_div_def tegra124_div_clks[] = {
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/* Core clocks. */
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DIV7_1(0, "pllC_out1_div", "pllC_out0", PLLC_OUT, 2),
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DIV7_1(0, "pllM_out1_div", "pllM_out0", PLLM_OUT, 8),
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DIV7_1(0, "pllP_outX0_div", "pllP_out0", PLLP_RESHIFT, 2),
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DIV7_1(0, "pllP_out1_div", "pllP_out0", PLLP_OUTA, 8),
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DIV7_1(0, "pllP_out2_div", "pllP_out0", PLLP_OUTA, 24),
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DIV7_1(0, "pllP_out3_div", "pllP_out0", PLLP_OUTB, 8),
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DIV7_1(0, "pllP_out4_div", "pllP_out0", PLLP_OUTB, 24),
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DIV7_1(0, "pllP_out5_div", "pllP_out0", PLLP_OUTC, 24),
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DIV7_1(0, "pllA_out1_div", "pllA_out", PLLA_OUT, 8),
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/* Base peripheral clocks. */
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DIV(0, "hclk_div", "sclk", CLK_SYSTEM_RATE, 4, 2, 0),
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DIV(0, "pclk_div", "hclk", CLK_SYSTEM_RATE, 0, 2, 0),
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};
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/* Initial setup table. */
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static struct tegra124_init_item clk_init_table[] = {
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/* clock, partent, frequency, enable */
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{"uarta", "pllP_out0", 408000000, 0},
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{"uartb", "pllP_out0", 408000000, 0},
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{"uartc", "pllP_out0", 408000000, 0},
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{"uartd", "pllP_out0", 408000000, 0},
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{"pllA_out", NULL, 282240000, 1},
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{"pllA_out0", NULL, 11289600, 1},
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{"extperiph1", "pllA_out0", 0, 1},
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{"i2s0", "pllA_out0", 11289600, 0},
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{"i2s1", "pllA_out0", 11289600, 0},
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{"i2s2", "pllA_out0", 11289600, 0},
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{"i2s3", "pllA_out0", 11289600, 0},
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{"i2s4", "pllA_out0", 11289600, 0},
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{"vde", "pllP_out0", 0, 0},
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{"host1x", "pllP_out0", 136000000, 1},
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{"sclk", "pllP_out2", 102000000, 1},
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{"dvfs_soc", "pllP_out0", 51000000, 1},
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{"dvfs_ref", "pllP_out0", 51000000, 1},
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{"pllC_out0", NULL, 600000000, 0},
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{"pllC_out1", NULL, 100000000, 0},
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{"spi4", "pllP_out0", 12000000, 1},
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{"tsec", "pllC3_out0", 0, 0},
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{"msenc", "pllC3_out0", 0, 0},
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{"pllREFE_out", NULL, 672000000, 0},
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{"pc_xusb_ss", "pllU_480", 120000000, 0},
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{"xusb_ss", "pc_xusb_ss", 120000000, 0},
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{"pc_xusb_fs", "pllU_48", 48000000, 0},
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{"xusb_hs", "pllU_60", 60000000, 0},
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{"pc_xusb_falcon", "pllREFE_out", 224000000, 0},
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{"xusb_core_host", "pllREFE_out", 112000000, 0},
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{"sata", "pllP_out0", 102000000, 0},
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{"sata_oob", "pllP_out0", 204000000, 0},
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{"sata_cold", NULL, 0, 1},
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{"emc", NULL, 0, 1},
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{"mselect", NULL, 0, 1},
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{"csite", NULL, 0, 1},
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{"tsensor", "clk_m", 400000, 0},
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/* tegra124 only*/
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{"soc_therm", "pllP_out0", 51000000, 0},
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{"cclk_g", NULL, 0, 1},
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{"hda", "pllP_out0", 102000000, 0},
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{"hda2codec_2x", "pllP_out0", 48000000, 0},
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};
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static void
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init_divs(struct tegra124_car_softc *sc, struct clk_div_def *clks, int nclks)
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{
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int i, rv;
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for (i = 0; i < nclks; i++) {
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rv = clknode_div_register(sc->clkdom, clks + i);
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if (rv != 0)
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panic("clk_div_register failed");
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}
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}
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static void
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init_gates(struct tegra124_car_softc *sc, struct clk_gate_def *clks, int nclks)
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{
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int i, rv;
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for (i = 0; i < nclks; i++) {
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rv = clknode_gate_register(sc->clkdom, clks + i);
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if (rv != 0)
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panic("clk_gate_register failed");
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}
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}
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static void
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init_muxes(struct tegra124_car_softc *sc, struct clk_mux_def *clks, int nclks)
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{
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int i, rv;
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for (i = 0; i < nclks; i++) {
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rv = clknode_mux_register(sc->clkdom, clks + i);
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if (rv != 0)
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panic("clk_mux_register failed");
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}
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}
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static void
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init_fixeds(struct tegra124_car_softc *sc, struct clk_fixed_def *clks,
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int nclks)
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{
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int i, rv;
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uint32_t val;
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int osc_idx;
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CLKDEV_READ_4(sc->dev, OSC_CTRL, &val);
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osc_idx = val >> OSC_CTRL_OSC_FREQ_SHIFT;
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fixed_clk_m.freq = osc_freqs[osc_idx];
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if (fixed_clk_m.freq == 0)
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panic("Undefined input frequency");
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rv = clknode_fixed_register(sc->clkdom, &fixed_clk_m);
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if (rv != 0) panic("clk_fixed_register failed");
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val = (val >> OSC_CTRL_PLL_REF_DIV_SHIFT) & 3;
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fixed_osc_div_clk.div = 1 << val;
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rv = clknode_fixed_register(sc->clkdom, &fixed_osc_div_clk);
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if (rv != 0) panic("clk_fixed_register failed");
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for (i = 0; i < nclks; i++) {
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rv = clknode_fixed_register(sc->clkdom, clks + i);
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if (rv != 0)
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panic("clk_fixed_register failed");
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}
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}
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static void
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postinit_clock(struct tegra124_car_softc *sc)
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{
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int i;
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struct tegra124_init_item *tbl;
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struct clknode *clknode;
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int rv;
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for (i = 0; i < nitems(clk_init_table); i++) {
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tbl = &clk_init_table[i];
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clknode = clknode_find_by_name(tbl->name);
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if (clknode == NULL) {
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device_printf(sc->dev, "Cannot find clock %s\n",
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tbl->name);
|
|
continue;
|
|
}
|
|
if (tbl->parent != NULL) {
|
|
rv = clknode_set_parent_by_name(clknode, tbl->parent);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"Cannot set parent for %s (to %s): %d\n",
|
|
tbl->name, tbl->parent, rv);
|
|
continue;
|
|
}
|
|
}
|
|
if (tbl->frequency != 0) {
|
|
rv = clknode_set_freq(clknode, tbl->frequency, 0 , 9999);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"Cannot set frequency for %s: %d\n",
|
|
tbl->name, rv);
|
|
continue;
|
|
}
|
|
}
|
|
if (tbl->enable!= 0) {
|
|
rv = clknode_enable(clknode);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"Cannot enable %s: %d\n", tbl->name, rv);
|
|
continue;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void
|
|
register_clocks(device_t dev)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->clkdom = clkdom_create(dev);
|
|
if (sc->clkdom == NULL)
|
|
panic("clkdom == NULL");
|
|
|
|
tegra124_init_plls(sc);
|
|
init_fixeds(sc, tegra124_fixed_clks, nitems(tegra124_fixed_clks));
|
|
init_muxes(sc, tegra124_mux_clks, nitems(tegra124_mux_clks));
|
|
init_divs(sc, tegra124_div_clks, nitems(tegra124_div_clks));
|
|
init_gates(sc, tegra124_gate_clks, nitems(tegra124_gate_clks));
|
|
tegra124_periph_clock(sc);
|
|
tegra124_super_mux_clock(sc);
|
|
clkdom_finit(sc->clkdom);
|
|
clkdom_xlock(sc->clkdom);
|
|
postinit_clock(sc);
|
|
clkdom_unlock(sc->clkdom);
|
|
if (bootverbose)
|
|
clkdom_dump(sc->clkdom);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_clkdev_read_4(device_t dev, bus_addr_t addr, uint32_t *val)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
*val = bus_read_4(sc->mem_res, addr);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_clkdev_write_4(device_t dev, bus_addr_t addr, uint32_t val)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
bus_write_4(sc->mem_res, addr, val);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_clkdev_modify_4(device_t dev, bus_addr_t addr, uint32_t clear_mask,
|
|
uint32_t set_mask)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
uint32_t reg;
|
|
|
|
sc = device_get_softc(dev);
|
|
reg = bus_read_4(sc->mem_res, addr);
|
|
reg &= ~clear_mask;
|
|
reg |= set_mask;
|
|
bus_write_4(sc->mem_res, addr, reg);
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
tegra124_car_clkdev_device_lock(device_t dev)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
mtx_lock(&sc->mtx);
|
|
}
|
|
|
|
static void
|
|
tegra124_car_clkdev_device_unlock(device_t dev)
|
|
{
|
|
struct tegra124_car_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
mtx_unlock(&sc->mtx);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_detach(device_t dev)
|
|
{
|
|
|
|
device_printf(dev, "Error: Clock driver cannot be detached\n");
|
|
return (EBUSY);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) {
|
|
device_set_desc(dev, "Tegra Clock Driver");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_attach(device_t dev)
|
|
{
|
|
struct tegra124_car_softc *sc = device_get_softc(dev);
|
|
int rid, rv;
|
|
|
|
sc->dev = dev;
|
|
|
|
mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
|
|
sc->type = ofw_bus_search_compatible(dev, compat_data)->ocd_data;
|
|
|
|
/* Resource setup. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (!sc->mem_res) {
|
|
device_printf(dev, "cannot allocate memory resource\n");
|
|
rv = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
register_clocks(dev);
|
|
hwreset_register_ofw_provider(dev);
|
|
return (0);
|
|
|
|
fail:
|
|
if (sc->mem_res)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->mem_res);
|
|
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
tegra124_car_hwreset_assert(device_t dev, intptr_t id, bool value)
|
|
{
|
|
struct tegra124_car_softc *sc = device_get_softc(dev);
|
|
|
|
return (tegra124_hwreset_by_idx(sc, id, value));
|
|
}
|
|
|
|
static device_method_t tegra124_car_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, tegra124_car_probe),
|
|
DEVMETHOD(device_attach, tegra124_car_attach),
|
|
DEVMETHOD(device_detach, tegra124_car_detach),
|
|
|
|
/* Clkdev interface*/
|
|
DEVMETHOD(clkdev_read_4, tegra124_car_clkdev_read_4),
|
|
DEVMETHOD(clkdev_write_4, tegra124_car_clkdev_write_4),
|
|
DEVMETHOD(clkdev_modify_4, tegra124_car_clkdev_modify_4),
|
|
DEVMETHOD(clkdev_device_lock, tegra124_car_clkdev_device_lock),
|
|
DEVMETHOD(clkdev_device_unlock, tegra124_car_clkdev_device_unlock),
|
|
|
|
/* Reset interface */
|
|
DEVMETHOD(hwreset_assert, tegra124_car_hwreset_assert),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static devclass_t tegra124_car_devclass;
|
|
static DEFINE_CLASS_0(car, tegra124_car_driver, tegra124_car_methods,
|
|
sizeof(struct tegra124_car_softc));
|
|
EARLY_DRIVER_MODULE(tegra124_car, simplebus, tegra124_car_driver,
|
|
tegra124_car_devclass, NULL, NULL, BUS_PASS_TIMER);
|