Alan Cox 072a067fb8 Because of AArch64's weak memory consistency model, we need to include a ... memory barrier between the stores for initializing a page table page and the store for adding that page to the page table. Otherwise, a page table walk by another processor's MMU could see the page table page before it sees the initialized entries. Simplify pmap_growkernel(). In particular, eliminate an unnecessary TLB invalidation. Reviewed by: andrew, markj MFC after: 1 week Differential Revision: https://reviews.freebsd.org/D21126		2019-08-02 22:36:42 +00:00
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acpica	arm64 acpi_iort: add some error handling	2019-06-24 21:24:55 +00:00
arm64	Because of AArch64's weak memory consistency model, we need to include a	2019-08-02 22:36:42 +00:00
cavium	Rename the ThunderX CPU identification macros to include the X. This is the	2018-06-13 12:17:11 +00:00
cloudabi32	Remove sv_pagesize, originally introduced with r100384.	2019-03-01 16:16:38 +00:00
cloudabi64	Remove sv_pagesize, originally introduced with r100384.	2019-03-01 16:16:38 +00:00
conf	Add support for the SD/MMC controller found in Terasic DE10-Pro	2019-07-30 12:51:14 +00:00
coresight	Extract eventfilter declarations to sys/_eventfilter.h	2019-05-20 00:38:23 +00:00
include	Use ATTR_DBM even when hardware dirty bit management is not enabled.	2019-08-01 22:48:06 +00:00
linux	linuxulator: rename linux_locore.s to .asm	2019-07-30 17:18:31 +00:00
qualcomm	Enable Qualcomm Debug Subsystem (QDSS) block on MSM8916 SoC.	2018-04-10 12:53:48 +00:00
rockchip	Add driver for Rockchip RK3399 eMMC PHY.	2019-07-20 02:03:31 +00:00