1311 lines
44 KiB
C
1311 lines
44 KiB
C
/*-
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* Copyright (c) 2017 Chelsio Communications, Inc.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/types.h>
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#include <sys/param.h>
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#include "common/common.h"
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#include "common/t4_regs.h"
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#include "cudbg.h"
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#include "cudbg_lib_common.h"
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#include "cudbg_entity.h"
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int collect_wtp_data(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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/*SGE_DEBUG Registers.*/
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#define TP_MIB_SIZE 0x5e
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struct sge_debug_reg_data {
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/*indx0*/
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u32 reserved1:4;
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u32 reserved2:4;
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u32 debug_uP_SOP_cnt:4;
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u32 debug_uP_EOP_cnt:4;
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u32 debug_CIM_SOP1_cnt:4;
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u32 debug_CIM_EOP1_cnt:4;
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u32 debug_CIM_SOP0_cnt:4;
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u32 debug_CIM_EOP0_cnt:4;
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/*indx1*/
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u32 reserved3:32;
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/*indx2*/
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u32 debug_T_Rx_SOP1_cnt:4;
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u32 debug_T_Rx_EOP1_cnt:4;
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u32 debug_T_Rx_SOP0_cnt:4;
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u32 debug_T_Rx_EOP0_cnt:4;
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u32 debug_U_Rx_SOP1_cnt:4;
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u32 debug_U_Rx_EOP1_cnt:4;
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u32 debug_U_Rx_SOP0_cnt:4;
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u32 debug_U_Rx_EOP0_cnt:4;
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/*indx3*/
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u32 reserved4:32;
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/*indx4*/
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u32 debug_UD_Rx_SOP3_cnt:4;
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u32 debug_UD_Rx_EOP3_cnt:4;
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u32 debug_UD_Rx_SOP2_cnt:4;
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u32 debug_UD_Rx_EOP2_cnt:4;
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u32 debug_UD_Rx_SOP1_cnt:4;
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u32 debug_UD_Rx_EOP1_cnt:4;
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u32 debug_UD_Rx_SOP0_cnt:4;
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u32 debug_UD_Rx_EOP0_cnt:4;
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/*indx5*/
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u32 reserved5:32;
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/*indx6*/
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u32 debug_U_Tx_SOP3_cnt:4;
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u32 debug_U_Tx_EOP3_cnt:4;
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u32 debug_U_Tx_SOP2_cnt:4;
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u32 debug_U_Tx_EOP2_cnt:4;
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u32 debug_U_Tx_SOP1_cnt:4;
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u32 debug_U_Tx_EOP1_cnt:4;
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u32 debug_U_Tx_SOP0_cnt:4;
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u32 debug_U_Tx_EOP0_cnt:4;
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/*indx7*/
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u32 reserved6:32;
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/*indx8*/
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u32 debug_PC_Rsp_SOP1_cnt:4;
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u32 debug_PC_Rsp_EOP1_cnt:4;
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u32 debug_PC_Rsp_SOP0_cnt:4;
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u32 debug_PC_Rsp_EOP0_cnt:4;
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u32 debug_PC_Req_SOP1_cnt:4;
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u32 debug_PC_Req_EOP1_cnt:4;
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u32 debug_PC_Req_SOP0_cnt:4;
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u32 debug_PC_Req_EOP0_cnt:4;
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/*indx9*/
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u32 reserved7:32;
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/*indx10*/
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u32 debug_PD_Req_SOP3_cnt:4;
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u32 debug_PD_Req_EOP3_cnt:4;
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u32 debug_PD_Req_SOP2_cnt:4;
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u32 debug_PD_Req_EOP2_cnt:4;
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u32 debug_PD_Req_SOP1_cnt:4;
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u32 debug_PD_Req_EOP1_cnt:4;
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u32 debug_PD_Req_SOP0_cnt:4;
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u32 debug_PD_Req_EOP0_cnt:4;
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/*indx11*/
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u32 reserved8:32;
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/*indx12*/
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u32 debug_PD_Rsp_SOP3_cnt:4;
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u32 debug_PD_Rsp_EOP3_cnt:4;
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u32 debug_PD_Rsp_SOP2_cnt:4;
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u32 debug_PD_Rsp_EOP2_cnt:4;
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u32 debug_PD_Rsp_SOP1_cnt:4;
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u32 debug_PD_Rsp_EOP1_cnt:4;
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u32 debug_PD_Rsp_SOP0_cnt:4;
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u32 debug_PD_Rsp_EOP0_cnt:4;
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/*indx13*/
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u32 reserved9:32;
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/*indx14*/
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u32 debug_CPLSW_TP_Rx_SOP1_cnt:4;
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u32 debug_CPLSW_TP_Rx_EOP1_cnt:4;
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u32 debug_CPLSW_TP_Rx_SOP0_cnt:4;
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u32 debug_CPLSW_TP_Rx_EOP0_cnt:4;
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u32 debug_CPLSW_CIM_SOP1_cnt:4;
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u32 debug_CPLSW_CIM_EOP1_cnt:4;
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u32 debug_CPLSW_CIM_SOP0_cnt:4;
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u32 debug_CPLSW_CIM_EOP0_cnt:4;
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/*indx15*/
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u32 reserved10:32;
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/*indx16*/
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u32 debug_PD_Req_Rd3_cnt:4;
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u32 debug_PD_Req_Rd2_cnt:4;
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u32 debug_PD_Req_Rd1_cnt:4;
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u32 debug_PD_Req_Rd0_cnt:4;
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u32 debug_PD_Req_Int3_cnt:4;
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u32 debug_PD_Req_Int2_cnt:4;
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u32 debug_PD_Req_Int1_cnt:4;
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u32 debug_PD_Req_Int0_cnt:4;
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};
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struct tp_mib_type tp_mib[] = {
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{"tp_mib_mac_in_err_0", 0x0},
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{"tp_mib_mac_in_err_1", 0x1},
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{"tp_mib_mac_in_err_2", 0x2},
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{"tp_mib_mac_in_err_3", 0x3},
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{"tp_mib_hdr_in_err_0", 0x4},
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{"tp_mib_hdr_in_err_1", 0x5},
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{"tp_mib_hdr_in_err_2", 0x6},
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{"tp_mib_hdr_in_err_3", 0x7},
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{"tp_mib_tcp_in_err_0", 0x8},
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{"tp_mib_tcp_in_err_1", 0x9},
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{"tp_mib_tcp_in_err_2", 0xa},
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{"tp_mib_tcp_in_err_3", 0xb},
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{"tp_mib_tcp_out_rst", 0xc},
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{"tp_mib_tcp_in_seg_hi", 0x10},
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{"tp_mib_tcp_in_seg_lo", 0x11},
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{"tp_mib_tcp_out_seg_hi", 0x12},
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{"tp_mib_tcp_out_seg_lo", 0x13},
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{"tp_mib_tcp_rxt_seg_hi", 0x14},
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{"tp_mib_tcp_rxt_seg_lo", 0x15},
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{"tp_mib_tnl_cng_drop_0", 0x18},
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{"tp_mib_tnl_cng_drop_1", 0x19},
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{"tp_mib_tnl_cng_drop_2", 0x1a},
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{"tp_mib_tnl_cng_drop_3", 0x1b},
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{"tp_mib_ofd_chn_drop_0", 0x1c},
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{"tp_mib_ofd_chn_drop_1", 0x1d},
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{"tp_mib_ofd_chn_drop_2", 0x1e},
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{"tp_mib_ofd_chn_drop_3", 0x1f},
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{"tp_mib_tnl_out_pkt_0", 0x20},
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{"tp_mib_tnl_out_pkt_1", 0x21},
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{"tp_mib_tnl_out_pkt_2", 0x22},
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{"tp_mib_tnl_out_pkt_3", 0x23},
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{"tp_mib_tnl_in_pkt_0", 0x24},
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{"tp_mib_tnl_in_pkt_1", 0x25},
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{"tp_mib_tnl_in_pkt_2", 0x26},
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{"tp_mib_tnl_in_pkt_3", 0x27},
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{"tp_mib_tcp_v6in_err_0", 0x28},
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{"tp_mib_tcp_v6in_err_1", 0x29},
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{"tp_mib_tcp_v6in_err_2", 0x2a},
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{"tp_mib_tcp_v6in_err_3", 0x2b},
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{"tp_mib_tcp_v6out_rst", 0x2c},
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{"tp_mib_tcp_v6in_seg_hi", 0x30},
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{"tp_mib_tcp_v6in_seg_lo", 0x31},
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{"tp_mib_tcp_v6out_seg_hi", 0x32},
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{"tp_mib_tcp_v6out_seg_lo", 0x33},
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{"tp_mib_tcp_v6rxt_seg_hi", 0x34},
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{"tp_mib_tcp_v6rxt_seg_lo", 0x35},
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{"tp_mib_ofd_arp_drop", 0x36},
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{"tp_mib_ofd_dfr_drop", 0x37},
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{"tp_mib_cpl_in_req_0", 0x38},
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{"tp_mib_cpl_in_req_1", 0x39},
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{"tp_mib_cpl_in_req_2", 0x3a},
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{"tp_mib_cpl_in_req_3", 0x3b},
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{"tp_mib_cpl_out_rsp_0", 0x3c},
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{"tp_mib_cpl_out_rsp_1", 0x3d},
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{"tp_mib_cpl_out_rsp_2", 0x3e},
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{"tp_mib_cpl_out_rsp_3", 0x3f},
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{"tp_mib_tnl_lpbk_0", 0x40},
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{"tp_mib_tnl_lpbk_1", 0x41},
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{"tp_mib_tnl_lpbk_2", 0x42},
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{"tp_mib_tnl_lpbk_3", 0x43},
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{"tp_mib_tnl_drop_0", 0x44},
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{"tp_mib_tnl_drop_1", 0x45},
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{"tp_mib_tnl_drop_2", 0x46},
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{"tp_mib_tnl_drop_3", 0x47},
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{"tp_mib_fcoe_ddp_0", 0x48},
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{"tp_mib_fcoe_ddp_1", 0x49},
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{"tp_mib_fcoe_ddp_2", 0x4a},
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{"tp_mib_fcoe_ddp_3", 0x4b},
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{"tp_mib_fcoe_drop_0", 0x4c},
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{"tp_mib_fcoe_drop_1", 0x4d},
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{"tp_mib_fcoe_drop_2", 0x4e},
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{"tp_mib_fcoe_drop_3", 0x4f},
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{"tp_mib_fcoe_byte_0_hi", 0x50},
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{"tp_mib_fcoe_byte_0_lo", 0x51},
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{"tp_mib_fcoe_byte_1_hi", 0x52},
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{"tp_mib_fcoe_byte_1_lo", 0x53},
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{"tp_mib_fcoe_byte_2_hi", 0x54},
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{"tp_mib_fcoe_byte_2_lo", 0x55},
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{"tp_mib_fcoe_byte_3_hi", 0x56},
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{"tp_mib_fcoe_byte_3_lo", 0x57},
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{"tp_mib_ofd_vln_drop_0", 0x58},
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{"tp_mib_ofd_vln_drop_1", 0x59},
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{"tp_mib_ofd_vln_drop_2", 0x5a},
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{"tp_mib_ofd_vln_drop_3", 0x5b},
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{"tp_mib_usm_pkts", 0x5c},
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{"tp_mib_usm_drop", 0x5d},
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{"tp_mib_usm_bytes_hi", 0x5e},
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{"tp_mib_usm_bytes_lo", 0x5f},
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{"tp_mib_tid_del", 0x60},
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{"tp_mib_tid_inv", 0x61},
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{"tp_mib_tid_act", 0x62},
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{"tp_mib_tid_pas", 0x63},
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{"tp_mib_rqe_dfr_mod", 0x64},
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{"tp_mib_rqe_dfr_pkt", 0x65}
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};
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static u32 read_sge_debug_data(struct cudbg_init *pdbg_init, u32 *sge_dbg_reg)
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{
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struct adapter *padap = pdbg_init->adap;
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u32 value;
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int i = 0;
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for (i = 0; i <= 15; i++) {
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t4_write_reg(padap, A_SGE_DEBUG_INDEX, (u32)i);
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value = t4_read_reg(padap, A_SGE_DEBUG_DATA_LOW);
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/*printf("LOW 0x%08x\n", value);*/
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sge_dbg_reg[(i << 1) | 1] = HTONL_NIBBLE(value);
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value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH);
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/*printf("HIGH 0x%08x\n", value);*/
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sge_dbg_reg[(i << 1)] = HTONL_NIBBLE(value);
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}
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return 0;
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}
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static u32 read_tp_mib_data(struct cudbg_init *pdbg_init,
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struct tp_mib_data **ppTp_Mib)
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{
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struct adapter *padap = pdbg_init->adap;
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u32 i = 0;
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for (i = 0; i < TP_MIB_SIZE; i++) {
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t4_tp_mib_read(padap, &tp_mib[i].value, 1,
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(u32)tp_mib[i].addr, true);
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}
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*ppTp_Mib = (struct tp_mib_data *)&tp_mib[0];
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return 0;
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}
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static int t5_wtp_data(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct sge_debug_reg_data *sge_dbg_reg = NULL;
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struct cudbg_buffer scratch_buff;
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struct tp_mib_data *ptp_mib = NULL;
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struct wtp_data *wtp;
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u32 Sge_Dbg[32] = {0};
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u32 value = 0;
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u32 i = 0;
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u32 drop = 0;
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u32 err = 0;
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u32 offset;
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int rc = 0;
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rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff);
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if (rc)
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goto err;
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offset = scratch_buff.offset;
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wtp = (struct wtp_data *)((char *)scratch_buff.data + offset);
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read_sge_debug_data(pdbg_init, Sge_Dbg);
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read_tp_mib_data(pdbg_init, &ptp_mib);
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sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0];
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/*#######################################################################*/
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/*# TX PATH, starting from pcie*/
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/*#######################################################################*/
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/* Get Requests of commands from SGE to PCIE*/
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wtp->sge_pcie_cmd_req.sop[0] = sge_dbg_reg->debug_PC_Req_SOP0_cnt;
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wtp->sge_pcie_cmd_req.sop[1] = sge_dbg_reg->debug_PC_Req_SOP1_cnt;
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wtp->sge_pcie_cmd_req.eop[0] = sge_dbg_reg->debug_PC_Req_EOP0_cnt;
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wtp->sge_pcie_cmd_req.eop[1] = sge_dbg_reg->debug_PC_Req_EOP1_cnt;
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/* Get Requests of commands from PCIE to core*/
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value = t4_read_reg(padap, A_PCIE_CMDR_REQ_CNT);
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wtp->pcie_core_cmd_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
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wtp->pcie_core_cmd_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
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/* there is no EOP for this, so we fake it.*/
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wtp->pcie_core_cmd_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
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wtp->pcie_core_cmd_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
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/* Get DMA stats*/
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for (i = 0; i < 4; i++) {
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value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
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wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF;
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wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF);
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}
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/* Get SGE debug data high index 6*/
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value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_6);
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wtp->sge_debug_data_high_index_6.sop[0] = ((value >> 4) & 0x0F);
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wtp->sge_debug_data_high_index_6.eop[0] = ((value >> 0) & 0x0F);
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wtp->sge_debug_data_high_index_6.sop[1] = ((value >> 12) & 0x0F);
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wtp->sge_debug_data_high_index_6.eop[1] = ((value >> 8) & 0x0F);
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wtp->sge_debug_data_high_index_6.sop[2] = ((value >> 20) & 0x0F);
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wtp->sge_debug_data_high_index_6.eop[2] = ((value >> 16) & 0x0F);
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wtp->sge_debug_data_high_index_6.sop[3] = ((value >> 28) & 0x0F);
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wtp->sge_debug_data_high_index_6.eop[3] = ((value >> 24) & 0x0F);
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/* Get SGE debug data high index 3*/
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value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_3);
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wtp->sge_debug_data_high_index_3.sop[0] = ((value >> 4) & 0x0F);
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wtp->sge_debug_data_high_index_3.eop[0] = ((value >> 0) & 0x0F);
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wtp->sge_debug_data_high_index_3.sop[1] = ((value >> 12) & 0x0F);
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wtp->sge_debug_data_high_index_3.eop[1] = ((value >> 8) & 0x0F);
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wtp->sge_debug_data_high_index_3.sop[2] = ((value >> 20) & 0x0F);
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wtp->sge_debug_data_high_index_3.eop[2] = ((value >> 16) & 0x0F);
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wtp->sge_debug_data_high_index_3.sop[3] = ((value >> 28) & 0x0F);
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wtp->sge_debug_data_high_index_3.eop[3] = ((value >> 24) & 0x0F);
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|
|
/* Get ULP SE CNT CHx*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
|
|
wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F);
|
|
wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F);
|
|
}
|
|
|
|
/* Get MAC PORTx PKT COUNT*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
|
|
wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF);
|
|
wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF);
|
|
wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF);
|
|
wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF);
|
|
}
|
|
|
|
/* Get mac portx aFramesTransmittedok*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, 0x30a80 + ((i * 4) << 12));
|
|
wtp->mac_portx_aframestra_ok.sop[i] = (value & 0xFF);
|
|
wtp->mac_portx_aframestra_ok.eop[i] = (value & 0xFF);
|
|
}
|
|
|
|
/* Get command respones from core to PCIE*/
|
|
value = t4_read_reg(padap, A_PCIE_CMDR_RSP_CNT);
|
|
|
|
wtp->core_pcie_cmd_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->core_pcie_cmd_rsp.sop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
|
|
wtp->core_pcie_cmd_rsp.eop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->core_pcie_cmd_rsp.eop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
/*Get command Resposes from PCIE to SGE*/
|
|
wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt;
|
|
wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt;
|
|
|
|
wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
|
|
wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP1_cnt;
|
|
|
|
/* Get commands sent from SGE to CIM/uP*/
|
|
wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt;
|
|
wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt;
|
|
|
|
wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt;
|
|
wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt;
|
|
|
|
/* Get Requests of data from PCIE by SGE*/
|
|
wtp->utx_sge_dma_req.sop[0] = sge_dbg_reg->debug_UD_Rx_SOP0_cnt;
|
|
wtp->utx_sge_dma_req.sop[1] = sge_dbg_reg->debug_UD_Rx_SOP1_cnt;
|
|
wtp->utx_sge_dma_req.sop[2] = sge_dbg_reg->debug_UD_Rx_SOP2_cnt;
|
|
wtp->utx_sge_dma_req.sop[3] = sge_dbg_reg->debug_UD_Rx_SOP3_cnt;
|
|
|
|
wtp->utx_sge_dma_req.eop[0] = sge_dbg_reg->debug_UD_Rx_EOP0_cnt;
|
|
wtp->utx_sge_dma_req.eop[1] = sge_dbg_reg->debug_UD_Rx_EOP1_cnt;
|
|
wtp->utx_sge_dma_req.eop[2] = sge_dbg_reg->debug_UD_Rx_EOP2_cnt;
|
|
wtp->utx_sge_dma_req.eop[3] = sge_dbg_reg->debug_UD_Rx_EOP3_cnt;
|
|
|
|
/* Get Requests of data from PCIE by SGE*/
|
|
wtp->sge_pcie_dma_req.sop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt;
|
|
wtp->sge_pcie_dma_req.sop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt;
|
|
wtp->sge_pcie_dma_req.sop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt;
|
|
wtp->sge_pcie_dma_req.sop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt;
|
|
/*no EOP's, so fake it.*/
|
|
wtp->sge_pcie_dma_req.eop[0] = sge_dbg_reg->debug_PD_Req_Rd0_cnt;
|
|
wtp->sge_pcie_dma_req.eop[1] = sge_dbg_reg->debug_PD_Req_Rd1_cnt;
|
|
wtp->sge_pcie_dma_req.eop[2] = sge_dbg_reg->debug_PD_Req_Rd2_cnt;
|
|
wtp->sge_pcie_dma_req.eop[3] = sge_dbg_reg->debug_PD_Req_Rd3_cnt;
|
|
|
|
/* Get Requests of data from PCIE to core*/
|
|
value = t4_read_reg(padap, A_PCIE_DMAR_REQ_CNT);
|
|
|
|
wtp->pcie_core_dma_req.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dma_req.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dma_req.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dma_req.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
/* There is no eop so fake it.*/
|
|
wtp->pcie_core_dma_req.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dma_req.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dma_req.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dma_req.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
/* Get data responses from core to PCIE*/
|
|
value = t4_read_reg(padap, A_PCIE_DMAR_RSP_SOP_CNT);
|
|
|
|
wtp->core_pcie_dma_rsp.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->core_pcie_dma_rsp.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->core_pcie_dma_rsp.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->core_pcie_dma_rsp.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
value = t4_read_reg(padap, A_PCIE_DMAR_RSP_EOP_CNT);
|
|
|
|
wtp->core_pcie_dma_rsp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->core_pcie_dma_rsp.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->core_pcie_dma_rsp.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->core_pcie_dma_rsp.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
/* Get PCIE_DATA to SGE*/
|
|
wtp->pcie_sge_dma_rsp.sop[0] = sge_dbg_reg->debug_PD_Rsp_SOP0_cnt;
|
|
wtp->pcie_sge_dma_rsp.sop[1] = sge_dbg_reg->debug_PD_Rsp_SOP1_cnt;
|
|
wtp->pcie_sge_dma_rsp.sop[2] = sge_dbg_reg->debug_PD_Rsp_SOP2_cnt;
|
|
wtp->pcie_sge_dma_rsp.sop[3] = sge_dbg_reg->debug_PD_Rsp_SOP3_cnt;
|
|
|
|
wtp->pcie_sge_dma_rsp.eop[0] = sge_dbg_reg->debug_PD_Rsp_EOP0_cnt;
|
|
wtp->pcie_sge_dma_rsp.eop[1] = sge_dbg_reg->debug_PD_Rsp_EOP1_cnt;
|
|
wtp->pcie_sge_dma_rsp.eop[2] = sge_dbg_reg->debug_PD_Rsp_EOP2_cnt;
|
|
wtp->pcie_sge_dma_rsp.eop[3] = sge_dbg_reg->debug_PD_Rsp_EOP3_cnt;
|
|
|
|
/*Get SGE to ULP_TX*/
|
|
wtp->sge_utx.sop[0] = sge_dbg_reg->debug_U_Tx_SOP0_cnt;
|
|
wtp->sge_utx.sop[1] = sge_dbg_reg->debug_U_Tx_SOP1_cnt;
|
|
wtp->sge_utx.sop[2] = sge_dbg_reg->debug_U_Tx_SOP2_cnt;
|
|
wtp->sge_utx.sop[3] = sge_dbg_reg->debug_U_Tx_SOP3_cnt;
|
|
|
|
wtp->sge_utx.eop[0] = sge_dbg_reg->debug_U_Tx_EOP0_cnt;
|
|
wtp->sge_utx.eop[1] = sge_dbg_reg->debug_U_Tx_EOP1_cnt;
|
|
wtp->sge_utx.eop[2] = sge_dbg_reg->debug_U_Tx_EOP2_cnt;
|
|
wtp->sge_utx.eop[3] = sge_dbg_reg->debug_U_Tx_EOP3_cnt;
|
|
|
|
/* Get ULP_TX to TP*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, (A_ULP_TX_SE_CNT_CH0 + (i*4)));
|
|
|
|
wtp->utx_tp.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
|
|
wtp->utx_tp.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
|
|
}
|
|
|
|
/* Get TP_DBG_CSIDE registers*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
|
|
true);
|
|
|
|
wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
|
|
wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
|
|
wtp->tpcside_rxpld.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/
|
|
wtp->tpcside_rxpld.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/
|
|
wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
|
|
wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
|
|
wtp->tpcside_rxcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
|
|
wtp->tpcside_rxcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
|
|
}
|
|
|
|
/* TP_DBG_ESIDE*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
|
|
true);
|
|
|
|
wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
|
|
wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
|
|
wtp->tpeside_pm.sop[i] = ((value >> 20) & 0xF); /*bits 20:23*/
|
|
wtp->tpeside_pm.eop[i] = ((value >> 16) & 0xF); /*bits 16:19*/
|
|
wtp->mps_tpeside.sop[i] = ((value >> 12) & 0xF); /*bits 12:15*/
|
|
wtp->mps_tpeside.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
|
|
wtp->tpeside_pld.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
|
|
wtp->tpeside_pld.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
|
|
|
|
}
|
|
|
|
/*PCIE CMD STAT2*/
|
|
for (i = 0; i < 3; i++) {
|
|
value = t4_read_reg(padap, 0x5988 + (i * 0x10));
|
|
wtp->pcie_cmd_stat2.sop[i] = value & 0xFF;
|
|
wtp->pcie_cmd_stat2.eop[i] = value & 0xFF;
|
|
}
|
|
|
|
/*PCIE cmd stat3*/
|
|
for (i = 0; i < 3; i++) {
|
|
value = t4_read_reg(padap, 0x598c + (i * 0x10));
|
|
wtp->pcie_cmd_stat3.sop[i] = value & 0xFF;
|
|
wtp->pcie_cmd_stat3.eop[i] = value & 0xFF;
|
|
}
|
|
|
|
/* ULP_RX input/output*/
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
|
|
|
|
wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
|
|
wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
|
|
wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
|
|
wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
|
|
}
|
|
|
|
/* Get the MPS input from TP*/
|
|
drop = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
|
|
wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
|
|
*/
|
|
wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
|
|
*/
|
|
}
|
|
drop = ptp_mib->TP_MIB_OFD_ARP_DROP.value;
|
|
drop += ptp_mib->TP_MIB_OFD_DFR_DROP.value;
|
|
|
|
drop += ptp_mib->TP_MIB_TNL_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_TNL_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_TNL_DROP_2.value;
|
|
drop += ptp_mib->TP_MIB_TNL_DROP_3.value;
|
|
|
|
wtp->tp_mps.drops = drop;
|
|
|
|
/* Get the MPS output to the MAC's*/
|
|
drop = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
|
|
wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/
|
|
wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF);/*bit 0:7*/
|
|
wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
|
|
*/
|
|
wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
|
|
*/
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_TX_PORT_DROP_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
drop += value;
|
|
}
|
|
wtp->mps_xgm.drops = (drop & 0xFF);
|
|
|
|
/* Get the SOP/EOP counters into and out of MAC. [JHANEL] I think this
|
|
* is*/
|
|
/* clear on read, so you have to read both TX and RX path at same
|
|
* time.*/
|
|
drop = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MAC_PORT_PKT_COUNT) +
|
|
(i * T5_PORT_STRIDE)));
|
|
|
|
wtp->tx_xgm_xgm.sop[i] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
wtp->tx_xgm_xgm.eop[i] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->rx_xgm_xgm.sop[i] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->rx_xgm_xgm.eop[i] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
}
|
|
|
|
/* Get the MAC's output to the wire*/
|
|
drop = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MAC_PORT_AFRAMESTRANSMITTEDOK) +
|
|
(i * T5_PORT_STRIDE)));
|
|
wtp->xgm_wire.sop[i] = (value);
|
|
wtp->xgm_wire.eop[i] = (value); /* No EOP for XGMAC, so fake
|
|
it.*/
|
|
}
|
|
|
|
/*########################################################################*/
|
|
/*# RX PATH, starting from wire*/
|
|
/*########################################################################*/
|
|
|
|
/* Add up the wire input to the MAC*/
|
|
drop = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MAC_PORT_AFRAMESRECEIVEDOK) +
|
|
(i * T5_PORT_STRIDE)));
|
|
|
|
wtp->wire_xgm.sop[i] = (value);
|
|
wtp->wire_xgm.eop[i] = (value); /* No EOP for XGMAC, so fake
|
|
it.*/
|
|
}
|
|
|
|
/* Already read the rx_xgm_xgm when reading TX path.*/
|
|
|
|
/* Add up SOP/EOP's on all 8 MPS buffer channels*/
|
|
drop = 0;
|
|
for (i = 0; i < 8; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
|
|
|
|
wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/
|
|
wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/
|
|
}
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
|
|
/* typo in JHANEL's code.*/
|
|
drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF);
|
|
}
|
|
wtp->xgm_mps.cls_drop = drop & 0xFF;
|
|
|
|
/* Add up the overflow drops on all 4 ports.*/
|
|
drop = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 2)));
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 2)));
|
|
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
|
|
value = t4_read_reg(padap,
|
|
T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) +
|
|
(i * T5_PORT_STRIDE));
|
|
drop += value;
|
|
}
|
|
wtp->xgm_mps.drop = (drop & 0xFF);
|
|
|
|
/* Add up the MPS errors that should result in dropped packets*/
|
|
err = 0;
|
|
for (i = 0; i < 4; i++) {
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG((A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
|
|
(i * T5_PORT_STRIDE) + 4)));
|
|
}
|
|
wtp->xgm_mps.err = (err & 0xFF);
|
|
|
|
drop = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
|
|
|
|
wtp->mps_tp.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->mps_tp.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->mps_tp.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
|
|
*/
|
|
wtp->mps_tp.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
|
|
*/
|
|
}
|
|
drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_TNL_CNG_DROP_2.value;
|
|
drop += ptp_mib->TP_MIB_TNL_CNG_DROP_3.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_2.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_3.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_2.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_3.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_2.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_3.value;
|
|
drop += ptp_mib->TP_MIB_USM_DROP.value;
|
|
|
|
wtp->mps_tp.drops = drop;
|
|
|
|
/* Get TP_DBG_CSIDE_TX registers*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
|
|
true);
|
|
|
|
wtp->tpcside_csw.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
|
|
wtp->tpcside_csw.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
|
|
wtp->tpcside_pm.sop[i] = ((value >> 20) & 0xF);/*bits 20:23*/
|
|
wtp->tpcside_pm.eop[i] = ((value >> 16) & 0xF);/*bits 16:19*/
|
|
wtp->tpcside_uturn.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
|
|
wtp->tpcside_uturn.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
|
|
wtp->tpcside_txcpl.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
|
|
wtp->tpcside_txcpl.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
|
|
}
|
|
|
|
/* TP to CPL_SWITCH*/
|
|
wtp->tp_csw.sop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP0_cnt;
|
|
wtp->tp_csw.sop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_SOP1_cnt;
|
|
|
|
wtp->tp_csw.eop[0] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP0_cnt;
|
|
wtp->tp_csw.eop[1] = sge_dbg_reg->debug_CPLSW_TP_Rx_EOP1_cnt;
|
|
|
|
/* TP/CPL_SWITCH to SGE*/
|
|
wtp->csw_sge.sop[0] = sge_dbg_reg->debug_T_Rx_SOP0_cnt;
|
|
wtp->csw_sge.sop[1] = sge_dbg_reg->debug_T_Rx_SOP1_cnt;
|
|
|
|
wtp->csw_sge.eop[0] = sge_dbg_reg->debug_T_Rx_EOP0_cnt;
|
|
wtp->csw_sge.eop[1] = sge_dbg_reg->debug_T_Rx_EOP1_cnt;
|
|
|
|
wtp->sge_pcie.sop[0] = sge_dbg_reg->debug_PD_Req_SOP0_cnt;
|
|
wtp->sge_pcie.sop[1] = sge_dbg_reg->debug_PD_Req_SOP1_cnt;
|
|
wtp->sge_pcie.sop[2] = sge_dbg_reg->debug_PD_Req_SOP2_cnt;
|
|
wtp->sge_pcie.sop[3] = sge_dbg_reg->debug_PD_Req_SOP3_cnt;
|
|
|
|
wtp->sge_pcie.eop[0] = sge_dbg_reg->debug_PD_Req_EOP0_cnt;
|
|
wtp->sge_pcie.eop[1] = sge_dbg_reg->debug_PD_Req_EOP1_cnt;
|
|
wtp->sge_pcie.eop[2] = sge_dbg_reg->debug_PD_Req_EOP2_cnt;
|
|
wtp->sge_pcie.eop[3] = sge_dbg_reg->debug_PD_Req_EOP3_cnt;
|
|
|
|
wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
|
|
wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
|
|
wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
|
|
wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
|
|
/* NO EOP, so fake it.*/
|
|
wtp->sge_pcie_ints.eop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
|
|
wtp->sge_pcie_ints.eop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
|
|
wtp->sge_pcie_ints.eop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
|
|
wtp->sge_pcie_ints.eop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
|
|
|
|
/*Get PCIE DMA1 STAT2*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
|
|
wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F);
|
|
wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F);
|
|
wtp->pcie_dma1_stat2_core.sop[i] += value & 0x0F;
|
|
wtp->pcie_dma1_stat2_core.eop[i] += value & 0x0F;
|
|
}
|
|
|
|
/* Get mac porrx aFramesTransmittedok*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, 0x30a88 + ((i * 4) << 12));
|
|
wtp->mac_porrx_aframestra_ok.sop[i] = (value & 0xFF);
|
|
wtp->mac_porrx_aframestra_ok.eop[i] = (value & 0xFF);
|
|
}
|
|
|
|
/*Get SGE debug data high index 7*/
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
|
|
wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.sop[2] = ((value >> 20) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[2] = ((value >> 16) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.sop[3] = ((value >> 28) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[3] = ((value >> 24) & 0x0F);
|
|
|
|
/*Get SGE debug data high index 1*/
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
|
|
wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F);
|
|
|
|
/*Get TP debug CSIDE Tx registers*/
|
|
for (i = 0; i < 2; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
|
|
true);
|
|
|
|
wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31
|
|
*/
|
|
wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF);
|
|
}
|
|
|
|
/*Get SGE debug data high index 9*/
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
|
|
wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F);
|
|
wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F);
|
|
wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F);
|
|
wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F);
|
|
wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F);
|
|
wtp->sge_work_req_pkt.sop[1] = ((value >> 12) & 0x0F);
|
|
|
|
/*Get LE DB response count*/
|
|
value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
|
|
wtp->le_db_rsp_cnt.sop = value & 0xF;
|
|
wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF;
|
|
|
|
/*Get TP debug Eside PKTx*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
|
|
true);
|
|
|
|
wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF);
|
|
wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF);
|
|
}
|
|
|
|
/* Get data responses from core to PCIE*/
|
|
value = t4_read_reg(padap, A_PCIE_DMAW_SOP_CNT);
|
|
|
|
wtp->pcie_core_dmaw.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dmaw.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dmaw.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dmaw.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
value = t4_read_reg(padap, A_PCIE_DMAW_EOP_CNT);
|
|
|
|
wtp->pcie_core_dmaw.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dmaw.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dmaw.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dmaw.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
value = t4_read_reg(padap, A_PCIE_DMAI_CNT);
|
|
|
|
wtp->pcie_core_dmai.sop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dmai.sop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dmai.sop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dmai.sop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
/* no eop for interrups, just fake it.*/
|
|
wtp->pcie_core_dmai.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->pcie_core_dmai.eop[1] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->pcie_core_dmai.eop[2] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
wtp->pcie_core_dmai.eop[3] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
|
|
rc = write_compression_hdr(&scratch_buff, dbg_buff);
|
|
|
|
if (rc)
|
|
goto err1;
|
|
|
|
rc = compress_buff(&scratch_buff, dbg_buff);
|
|
|
|
err1:
|
|
release_scratch_buff(&scratch_buff, dbg_buff);
|
|
err:
|
|
return rc;
|
|
}
|
|
|
|
static int t6_wtp_data(struct cudbg_init *pdbg_init,
|
|
struct cudbg_buffer *dbg_buff,
|
|
struct cudbg_error *cudbg_err)
|
|
{
|
|
struct adapter *padap = pdbg_init->adap;
|
|
struct sge_debug_reg_data *sge_dbg_reg = NULL;
|
|
struct cudbg_buffer scratch_buff;
|
|
struct tp_mib_data *ptp_mib = NULL;
|
|
struct wtp_data *wtp;
|
|
u32 Sge_Dbg[32] = {0};
|
|
u32 value = 0;
|
|
u32 i = 0;
|
|
u32 drop = 0;
|
|
u32 err = 0;
|
|
u32 offset;
|
|
int rc = 0;
|
|
|
|
rc = get_scratch_buff(dbg_buff, sizeof(struct wtp_data), &scratch_buff);
|
|
|
|
if (rc)
|
|
goto err;
|
|
|
|
offset = scratch_buff.offset;
|
|
wtp = (struct wtp_data *)((char *)scratch_buff.data + offset);
|
|
|
|
read_sge_debug_data(pdbg_init, Sge_Dbg);
|
|
read_tp_mib_data(pdbg_init, &ptp_mib);
|
|
|
|
sge_dbg_reg = (struct sge_debug_reg_data *) &Sge_Dbg[0];
|
|
|
|
/*# TX PATH*/
|
|
|
|
/*PCIE CMD STAT2*/
|
|
value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT2);
|
|
wtp->pcie_cmd_stat2.sop[0] = value & 0xFF;
|
|
wtp->pcie_cmd_stat2.eop[0] = value & 0xFF;
|
|
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
|
|
wtp->sge_pcie_cmd_req.sop[0] = ((value >> 20) & 0x0F);
|
|
wtp->sge_pcie_cmd_req.eop[0] = ((value >> 16) & 0x0F);
|
|
wtp->sge_pcie_cmd_req.sop[1] = ((value >> 28) & 0x0F);
|
|
wtp->sge_pcie_cmd_req.eop[1] = ((value >> 24) & 0x0F);
|
|
|
|
value = t4_read_reg(padap, A_PCIE_T5_CMD_STAT3);
|
|
wtp->pcie_cmd_stat3.sop[0] = value & 0xFF;
|
|
wtp->pcie_cmd_stat3.eop[0] = value & 0xFF;
|
|
|
|
/*Get command Resposes from PCIE to SGE*/
|
|
wtp->pcie_sge_cmd_rsp.sop[0] = sge_dbg_reg->debug_PC_Rsp_SOP0_cnt;
|
|
wtp->pcie_sge_cmd_rsp.eop[0] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
|
|
wtp->pcie_sge_cmd_rsp.sop[1] = sge_dbg_reg->debug_PC_Rsp_SOP1_cnt;
|
|
wtp->pcie_sge_cmd_rsp.eop[1] = sge_dbg_reg->debug_PC_Rsp_EOP0_cnt;
|
|
|
|
/* Get commands sent from SGE to CIM/uP*/
|
|
wtp->sge_cim.sop[0] = sge_dbg_reg->debug_CIM_SOP0_cnt;
|
|
wtp->sge_cim.sop[1] = sge_dbg_reg->debug_CIM_SOP1_cnt;
|
|
|
|
wtp->sge_cim.eop[0] = sge_dbg_reg->debug_CIM_EOP0_cnt;
|
|
wtp->sge_cim.eop[1] = sge_dbg_reg->debug_CIM_EOP1_cnt;
|
|
|
|
/*Get SGE debug data high index 9*/
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
|
|
wtp->sge_work_req_pkt.sop[0] = ((value >> 4) & 0x0F);
|
|
wtp->sge_work_req_pkt.eop[0] = ((value >> 0) & 0x0F);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT2 + (i * 0x10));
|
|
wtp->pcie_dma1_stat2.sop[i] = ((value >> 8) & 0x0F);
|
|
wtp->pcie_dma1_stat2.eop[i] = ((value >> 8) & 0x0F);
|
|
wtp->pcie_dma1_stat2_core.sop[i] = value & 0x0F;
|
|
wtp->pcie_dma1_stat2_core.eop[i] = value & 0x0F;
|
|
}
|
|
|
|
/* Get DMA0 stats3*/
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, A_PCIE_T5_DMA_STAT3 + (i * 0x10));
|
|
wtp->pcie_t5_dma_stat3.sop[i] = value & 0xFF;
|
|
wtp->pcie_t5_dma_stat3.eop[i] = ((value >> 16) & 0xFF);
|
|
}
|
|
|
|
/* Get ULP SE CNT CHx*/
|
|
for (i = 0; i < 4; i++) {
|
|
value = t4_read_reg(padap, A_ULP_TX_SE_CNT_CH0 + (i * 4));
|
|
wtp->ulp_se_cnt_chx.sop[i] = ((value >> 28) & 0x0F);
|
|
wtp->ulp_se_cnt_chx.eop[i] = ((value >> 24) & 0x0F);
|
|
}
|
|
|
|
/* Get TP_DBG_CSIDE registers*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_RX0 + i),
|
|
true);
|
|
|
|
wtp->utx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
|
|
wtp->utx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
|
|
wtp->tpcside_rxarb.sop[i] = ((value >> 12) & 0xF);/*bits 12:15*/
|
|
wtp->tpcside_rxarb.eop[i] = ((value >> 8) & 0xF); /*bits 8:11*/
|
|
}
|
|
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
|
|
true);
|
|
|
|
|
|
wtp->tpeside_mps.sop[i] = ((value >> 28) & 0xF); /*bits 28:31*/
|
|
wtp->tpeside_mps.eop[i] = ((value >> 24) & 0xF); /*bits 24:27*/
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_TP01 + (i << 2)));
|
|
wtp->tp_mps.sop[(i*2)] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->tp_mps.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->tp_mps.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
|
|
*/
|
|
wtp->tp_mps.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
|
|
*/
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_TX_SE_CNT_MAC01 + (i << 2)));
|
|
wtp->mps_xgm.sop[(i*2)] = ((value >> 8) & 0xFF);/*bit 8:15*/
|
|
wtp->mps_xgm.eop[(i*2)] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->mps_xgm.sop[(i*2) + 1] = ((value >> 24) & 0xFF);/*bit 24:31
|
|
*/
|
|
wtp->mps_xgm.eop[(i*2) + 1] = ((value >> 16) & 0xFF);/*bit 16:23
|
|
*/
|
|
}
|
|
|
|
/* Get MAC PORTx PKT COUNT*/
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, 0x3081c + ((i * 4) << 12));
|
|
wtp->mac_portx_pkt_count.sop[i] = ((value >> 24) & 0xFF);
|
|
wtp->mac_portx_pkt_count.eop[i] = ((value >> 16) & 0xFF);
|
|
wtp->mac_porrx_pkt_count.sop[i] = ((value >> 8) & 0xFF);
|
|
wtp->mac_porrx_pkt_count.eop[i] = ((value >> 0) & 0xFF);
|
|
}
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, 0x30f20 + ((i * 4) << 12));
|
|
wtp->mac_portx_aframestra_ok.sop[i] = value & 0xff;
|
|
wtp->mac_portx_aframestra_ok.eop[i] = value & 0xff;
|
|
}
|
|
|
|
/*MAC_PORT_MTIP_1G10G_TX_etherStatsPkts*/
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, 0x30f60 + ((i * 4) << 12));
|
|
wtp->mac_portx_etherstatspkts.sop[i] = value & 0xff;
|
|
wtp->mac_portx_etherstatspkts.eop[i] = value & 0xff;
|
|
}
|
|
|
|
/*RX path*/
|
|
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_7);
|
|
wtp->sge_debug_data_high_indx7.sop[0] = ((value >> 4) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[0] = ((value >> 0) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.sop[1] = ((value >> 12) & 0x0F);
|
|
wtp->sge_debug_data_high_indx7.eop[1] = ((value >> 8) & 0x0F);
|
|
|
|
/*Get SGE debug data high index 1*/
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_1);
|
|
wtp->sge_debug_data_high_indx1.sop[0] = ((value >> 20) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.eop[0] = ((value >> 16) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.sop[1] = ((value >> 28) & 0x0F);
|
|
wtp->sge_debug_data_high_indx1.eop[1] = ((value >> 24) & 0x0F);
|
|
|
|
value = t4_read_reg(padap, A_SGE_DEBUG_DATA_HIGH_INDEX_9);
|
|
wtp->sge_debug_data_high_indx9.sop[0] = ((value >> 20) & 0x0F);
|
|
wtp->sge_debug_data_high_indx9.sop[1] = ((value >> 28) & 0x0F);
|
|
|
|
wtp->sge_debug_data_high_indx9.eop[0] = ((value >> 16) & 0x0F);
|
|
wtp->sge_debug_data_high_indx9.eop[1] = ((value >> 24) & 0x0F);
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_CSIDE_TX0 + i),
|
|
true);
|
|
|
|
wtp->utx_tpcside_tx.sop[i] = ((value >> 28) & 0xF);/*bits 28:31
|
|
*/
|
|
wtp->utx_tpcside_tx.eop[i] = ((value >> 24) & 0xF);
|
|
}
|
|
|
|
/*ULP_RX input/output*/
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_ULP_RX_SE_CNT_CH0 + (i*4)));
|
|
|
|
wtp->pmrx_ulprx.sop[i] = ((value >> 4) & 0xF); /*bits 4:7*/
|
|
wtp->pmrx_ulprx.eop[i] = ((value >> 0) & 0xF); /*bits 0:3*/
|
|
wtp->ulprx_tpcside.sop[i] = ((value >> 28) & 0xF);/*bits 28:31*/
|
|
wtp->ulprx_tpcside.eop[i] = ((value >> 24) & 0xF);/*bits 24:27*/
|
|
}
|
|
|
|
/*Get LE DB response count*/
|
|
value = t4_read_reg(padap, A_LE_DB_REQ_RSP_CNT);
|
|
wtp->le_db_rsp_cnt.sop = value & 0xF;
|
|
wtp->le_db_rsp_cnt.eop = (value >> 16) & 0xF;
|
|
|
|
/*Get TP debug Eside PKTx*/
|
|
for (i = 0; i < 4; i++) {
|
|
t4_tp_pio_read(padap, &value, 1, (u32)(A_TP_DBG_ESIDE_PKT0 + i),
|
|
true);
|
|
|
|
wtp->tp_dbg_eside_pktx.sop[i] = ((value >> 12) & 0xF);
|
|
wtp->tp_dbg_eside_pktx.eop[i] = ((value >> 8) & 0xF);
|
|
}
|
|
|
|
drop = 0;
|
|
/*MPS_RX_SE_CNT_OUT01*/
|
|
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_OUT01 + (i << 2)));
|
|
wtp->mps_tp.sop[0] = ((value >> 8) & 0xFF); /*bit 8:15*/
|
|
wtp->mps_tp.eop[0] = ((value >> 0) & 0xFF); /*bit 0:7*/
|
|
wtp->mps_tp.sop[1] = ((value >> 24) & 0xFF); /*bit 24:31*/
|
|
wtp->mps_tp.eop[1] = ((value >> 16) & 0xFF); /*bit 16:23*/
|
|
|
|
drop = ptp_mib->TP_MIB_TNL_CNG_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_TNL_CNG_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_OFD_CHN_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_FCOE_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_0.value;
|
|
drop += ptp_mib->TP_MIB_OFD_VLN_DROP_1.value;
|
|
drop += ptp_mib->TP_MIB_USM_DROP.value;
|
|
|
|
wtp->mps_tp.drops = drop;
|
|
|
|
drop = 0;
|
|
for (i = 0; i < 8; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_RX_SE_CNT_IN0 + (i << 2)));
|
|
|
|
wtp->xgm_mps.sop[i] = ((value >> 8) & 0xFF); /*bits 8:15*/
|
|
wtp->xgm_mps.eop[i] = ((value >> 0) & 0xFF); /*bits 0:7*/
|
|
}
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, (A_MPS_RX_CLS_DROP_CNT0 + (i << 2)));
|
|
drop += (value & 0xFFFF) + ((value >> 16) & 0xFFFF);
|
|
}
|
|
wtp->xgm_mps.cls_drop = drop & 0xFF;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, 0x30e20 + ((i * 4) << 12));
|
|
wtp->mac_porrx_aframestra_ok.sop[i] = value & 0xff;
|
|
wtp->mac_porrx_aframestra_ok.eop[i] = value & 0xff;
|
|
}
|
|
|
|
/*MAC_PORT_MTIP_1G10G_RX_etherStatsPkts*/
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap, 0x30e60 + ((i * 4) << 12));
|
|
wtp->mac_porrx_etherstatspkts.sop[i] = value & 0xff;
|
|
wtp->mac_porrx_etherstatspkts.eop[i] = value & 0xff;
|
|
}
|
|
|
|
wtp->sge_pcie_ints.sop[0] = sge_dbg_reg->debug_PD_Req_Int0_cnt;
|
|
wtp->sge_pcie_ints.sop[1] = sge_dbg_reg->debug_PD_Req_Int1_cnt;
|
|
wtp->sge_pcie_ints.sop[2] = sge_dbg_reg->debug_PD_Req_Int2_cnt;
|
|
wtp->sge_pcie_ints.sop[3] = sge_dbg_reg->debug_PD_Req_Int3_cnt;
|
|
|
|
/* Add up the overflow drops on all 4 ports.*/
|
|
drop = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 2)));
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_LB_DROP_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_DROP_FRAME_L +
|
|
(i << 2)));
|
|
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_LB_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
drop += value;
|
|
value = t4_read_reg(padap,
|
|
(A_MPS_STAT_RX_BG_0_MAC_TRUNC_FRAME_L +
|
|
(i << 3)));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_LB_PORT_DROP_FRAMES) +
|
|
(i * T5_PORT_STRIDE)));
|
|
drop += value;
|
|
}
|
|
wtp->xgm_mps.drop = (drop & 0xFF);
|
|
|
|
/* Add up the MPS errors that should result in dropped packets*/
|
|
err = 0;
|
|
for (i = 0; i < 2; i++) {
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_MTU_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_CRC_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LEN_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_SYM_ERROR_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
|
|
(i * T5_PORT_STRIDE)));
|
|
err += value;
|
|
value = t4_read_reg(padap,
|
|
(T5_PORT0_REG(A_MPS_PORT_STAT_RX_PORT_LESS_64B_L) +
|
|
(i * T5_PORT_STRIDE) + 4));
|
|
}
|
|
wtp->xgm_mps.err = (err & 0xFF);
|
|
|
|
rc = write_compression_hdr(&scratch_buff, dbg_buff);
|
|
|
|
if (rc)
|
|
goto err1;
|
|
|
|
rc = compress_buff(&scratch_buff, dbg_buff);
|
|
|
|
err1:
|
|
release_scratch_buff(&scratch_buff, dbg_buff);
|
|
err:
|
|
return rc;
|
|
}
|
|
|
|
int collect_wtp_data(struct cudbg_init *pdbg_init,
|
|
struct cudbg_buffer *dbg_buff,
|
|
struct cudbg_error *cudbg_err)
|
|
{
|
|
struct adapter *padap = pdbg_init->adap;
|
|
int rc = -1;
|
|
|
|
if (is_t5(padap))
|
|
rc = t5_wtp_data(pdbg_init, dbg_buff, cudbg_err);
|
|
else if (is_t6(padap))
|
|
rc = t6_wtp_data(pdbg_init, dbg_buff, cudbg_err);
|
|
|
|
return rc;
|
|
}
|