a0e512b219
the chipset. This is already how the multi-hose systems handle resource allocation and it fixes a bug where dense and bwx memory allocations were not handled properly. Reviewed by: gallatin
221 lines
5.6 KiB
C
221 lines
5.6 KiB
C
/*-
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* Copyright (c) 2000 Andrew Gallatin
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <machine/md_var.h>
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#include <machine/bwx.h>
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#include <sys/rman.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <alpha/pci/irongatereg.h>
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#include <alpha/pci/irongatevar.h>
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#include <alpha/pci/pcibus.h>
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#include "alphapci_if.h"
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#include "pcib_if.h"
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t pcib_devclass;
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static int
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irongate_pcib_probe(device_t dev)
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{
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device_set_desc(dev, "AMD 751 PCI host bus adapter");
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pci_init_resources();
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device_add_child(dev, "pci", 0);
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/*
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* XXX -- The SRM console doesn't properly initialize
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* the AcerLabs M1533C southbridge. We must turn off 32-bit
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* DMA support.
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*/
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if ((0x153310b9 == PCIB_READ_CONFIG(dev, 0, 7, 0,
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PCIR_DEVVENDOR, 4))) {
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u_int8_t value = PCIB_READ_CONFIG(dev, 0, 7, 0, 0x42, 1);
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value &= ~0x40;
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PCIB_WRITE_CONFIG(dev, 0, 7, 0, 0x42, 0, 1);
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}
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return 0;
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}
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static int
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irongate_pcib_read_ivar(device_t dev, device_t child, int which, u_long *result)
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{
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switch (which) {
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case PCIB_IVAR_BUS:
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*result = 0;
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return 0;
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}
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return ENOENT;
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}
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static void *
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irongate_pcib_cvt_dense(device_t dev, vm_offset_t addr)
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{
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addr &= 0xffffffffUL;
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return (void *) KV(addr | IRONGATE_MEM);
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}
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static void *
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irongate_pcib_cvt_bwx(device_t dev, vm_offset_t addr)
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{
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addr &= 0xffffffffUL;
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return (void *) KV(addr | IRONGATE_MEM);
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}
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static int
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irongate_pcib_maxslots(device_t dev)
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{
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return 31;
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}
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static void
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irongate_clear_abort(void)
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{
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alpha_mb();
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alpha_pal_draina();
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}
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static int
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irongate_check_abort(void)
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{
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alpha_pal_draina();
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alpha_mb();
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return 0;
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}
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#define IRONGATE_CFGADDR(b, s, f, r) \
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KV(IRONGATE_CONF | ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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#define CFGREAD(b, s, f, r, width, type, op) do { \
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vm_offset_t va; \
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type data; \
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va = IRONGATE_CFGADDR(b, s, f, r); \
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irongate_clear_abort(); \
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if (badaddr((caddr_t)va, width)) { \
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irongate_check_abort(); \
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return ~0; \
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} \
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data = ##op##(va); \
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if (irongate_check_abort()) \
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return ~0; \
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return data; \
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} while (0)
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#define CFGWRITE(b, s, f, r, data, width, op) do { \
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vm_offset_t va; \
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va = IRONGATE_CFGADDR(b, s, f, r); \
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irongate_clear_abort(); \
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if (badaddr((caddr_t)va, width)) \
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return; \
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##op##(va, data); \
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irongate_check_abort(); \
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} while (0)
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static u_int32_t
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irongate_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, int width)
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{
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switch (width) {
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case 1:
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CFGREAD(b, s, f, reg, 1, u_int8_t, ldbu);
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break;
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case 2:
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CFGREAD(b, s, f, reg, 2, u_int16_t, ldwu);
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break;
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case 4:
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CFGREAD(b, s, f, reg, 4, u_int32_t, ldl);
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}
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return ~0;
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}
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static void
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irongate_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
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u_int reg, u_int32_t val, int width)
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{
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switch (width) {
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case 1:
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CFGWRITE(b, s, f, reg, val, 1, stb);
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break;
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case 2:
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CFGWRITE(b, s, f, reg, val, 2, stw);
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break;
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case 4:
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CFGWRITE(b, s, f, reg, val, 4, stl);
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}
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}
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static device_method_t irongate_pcib_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, irongate_pcib_probe),
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DEVMETHOD(device_attach, bus_generic_attach),
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/* Bus interface */
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DEVMETHOD(bus_print_child, bus_generic_print_child),
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DEVMETHOD(bus_read_ivar, irongate_pcib_read_ivar),
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DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
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DEVMETHOD(bus_release_resource, pci_release_resource),
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DEVMETHOD(bus_activate_resource, pci_activate_resource),
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DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
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DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
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DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
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/* alphapci interface */
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DEVMETHOD(alphapci_cvt_dense, irongate_pcib_cvt_dense),
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DEVMETHOD(alphapci_cvt_bwx, irongate_pcib_cvt_bwx),
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/* pcib interface */
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DEVMETHOD(pcib_maxslots, irongate_pcib_maxslots),
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DEVMETHOD(pcib_read_config, irongate_pcib_read_config),
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DEVMETHOD(pcib_write_config, irongate_pcib_write_config),
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DEVMETHOD(pcib_route_interrupt, alpha_pci_route_interrupt),
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{ 0, 0 }
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};
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static driver_t irongate_pcib_driver = {
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"pcib",
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irongate_pcib_methods,
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1,
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};
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DRIVER_MODULE(pcib, irongate, irongate_pcib_driver, pcib_devclass, 0, 0);
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