143cfad710
encryption types. The AR5210 only has four WEP key slots, in contrast to what the later MACs have (ie, the keycache.) So there's no way to store a "clear" key. Even if the driver is taught to not allocate CLR key entries for the AR5210, the hardware will actually attempt to decode the encrypted frames with the (likely all 0!) WEP keys. So for now, disable the hardware encryption entirely and just so it all in software. That allows both WEP -and- WPA to actually work. If someone wishes to try and make hardware WEP _but_ software WPA work, they'll have to create a HAL capability to enable/disable hardware encryption based on the current STA/Hostap mode. However, making multi-vap work with one WEP and one WPA VAP will require hardware encryption to be disabled anyway.
271 lines
6.7 KiB
C
271 lines
6.7 KiB
C
/*
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* Copyright (c) 2002-2008 Sam Leffler, Errno Consulting
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* Copyright (c) 2002-2004 Atheros Communications, Inc.
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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* $FreeBSD$
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*/
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#include "opt_ah.h"
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#include "ah.h"
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#include "ah_internal.h"
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#include "ah_desc.h"
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#include "ar5210/ar5210.h"
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#include "ar5210/ar5210reg.h"
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#include "ar5210/ar5210desc.h"
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/*
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* Get the RXDP.
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*/
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uint32_t
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ar5210GetRxDP(struct ath_hal *ah, HAL_RX_QUEUE qtype)
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{
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HALASSERT(qtype == HAL_RX_QUEUE_HP);
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return OS_REG_READ(ah, AR_RXDP);
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}
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/*
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* Set the RxDP.
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*/
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void
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ar5210SetRxDP(struct ath_hal *ah, uint32_t rxdp, HAL_RX_QUEUE qtype)
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{
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HALASSERT(qtype == HAL_RX_QUEUE_HP);
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OS_REG_WRITE(ah, AR_RXDP, rxdp);
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}
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/*
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* Set Receive Enable bits.
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*/
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void
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ar5210EnableReceive(struct ath_hal *ah)
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{
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXE);
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}
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/*
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* Stop Receive at the DMA engine
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*/
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HAL_BOOL
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ar5210StopDmaReceive(struct ath_hal *ah)
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{
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int i;
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OS_REG_WRITE(ah, AR_CR, AR_CR_RXD); /* Set receive disable bit */
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for (i = 0; i < 1000; i++) {
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if ((OS_REG_READ(ah, AR_CR) & AR_CR_RXE) == 0)
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return AH_TRUE;
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OS_DELAY(10);
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}
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#ifdef AH_DEBUG
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ath_hal_printf(ah, "ar5210: dma receive failed to stop in 10ms\n");
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ath_hal_printf(ah, "AR_CR=0x%x\n", OS_REG_READ(ah, AR_CR));
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ath_hal_printf(ah, "AR_DIAG_SW=0x%x\n", OS_REG_READ(ah, AR_DIAG_SW));
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#endif
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return AH_FALSE;
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}
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/*
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* Start Transmit at the PCU engine (unpause receive)
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*/
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void
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ar5210StartPcuReceive(struct ath_hal *ah)
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{
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ar5210UpdateDiagReg(ah,
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OS_REG_READ(ah, AR_DIAG_SW) & ~(AR_DIAG_SW_DIS_RX));
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}
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/*
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* Stop Transmit at the PCU engine (pause receive)
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*/
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void
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ar5210StopPcuReceive(struct ath_hal *ah)
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{
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ar5210UpdateDiagReg(ah,
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OS_REG_READ(ah, AR_DIAG_SW) | AR_DIAG_SW_DIS_RX);
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}
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/*
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* Set multicast filter 0 (lower 32-bits)
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* filter 1 (upper 32-bits)
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*/
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void
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ar5210SetMulticastFilter(struct ath_hal *ah, uint32_t filter0, uint32_t filter1)
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{
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OS_REG_WRITE(ah, AR_MCAST_FIL0, filter0);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, filter1);
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}
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/*
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* Clear multicast filter by index
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*/
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HAL_BOOL
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ar5210ClrMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
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{
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uint32_t val;
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if (ix >= 64)
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return AH_FALSE;
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if (ix >= 32) {
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val = OS_REG_READ(ah, AR_MCAST_FIL1);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, (val &~ (1<<(ix-32))));
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} else {
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val = OS_REG_READ(ah, AR_MCAST_FIL0);
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OS_REG_WRITE(ah, AR_MCAST_FIL0, (val &~ (1<<ix)));
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}
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return AH_TRUE;
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}
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/*
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* Set multicast filter by index
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*/
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HAL_BOOL
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ar5210SetMulticastFilterIndex(struct ath_hal *ah, uint32_t ix)
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{
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uint32_t val;
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if (ix >= 64)
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return AH_FALSE;
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if (ix >= 32) {
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val = OS_REG_READ(ah, AR_MCAST_FIL1);
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OS_REG_WRITE(ah, AR_MCAST_FIL1, (val | (1<<(ix-32))));
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} else {
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val = OS_REG_READ(ah, AR_MCAST_FIL0);
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OS_REG_WRITE(ah, AR_MCAST_FIL0, (val | (1<<ix)));
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}
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return AH_TRUE;
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}
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/*
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* Return the receive packet filter.
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*/
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uint32_t
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ar5210GetRxFilter(struct ath_hal *ah)
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{
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/* XXX can't be sure if promiscuous mode is set because of PHYRADAR */
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return OS_REG_READ(ah, AR_RX_FILTER);
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}
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/*
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* Turn off/on bits in the receive packet filter.
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*/
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void
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ar5210SetRxFilter(struct ath_hal *ah, uint32_t bits)
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{
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if (bits & HAL_RX_FILTER_PHYRADAR) {
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/* must enable promiscuous mode to get radar */
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bits = (bits &~ HAL_RX_FILTER_PHYRADAR) | AR_RX_FILTER_PROMISCUOUS;
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}
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OS_REG_WRITE(ah, AR_RX_FILTER, bits);
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}
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/*
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* Initialize RX descriptor, by clearing the status and clearing
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* the size. This is not strictly HW dependent, but we want the
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* control and status words to be opaque above the hal.
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*/
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HAL_BOOL
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ar5210SetupRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t size, u_int flags)
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{
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struct ar5210_desc *ads = AR5210DESC(ds);
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(void) flags;
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ads->ds_ctl0 = 0;
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ads->ds_ctl1 = size & AR_BufLen;
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if (ads->ds_ctl1 != size) {
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HALDEBUG(ah, HAL_DEBUG_ANY, "%s: buffer size %u too large\n",
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__func__, size);
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return AH_FALSE;
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}
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if (flags & HAL_RXDESC_INTREQ)
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ads->ds_ctl1 |= AR_RxInterReq;
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ads->ds_status0 = ads->ds_status1 = 0;
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return AH_TRUE;
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}
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/*
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* Process an RX descriptor, and return the status to the caller.
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* Copy some hardware specific items into the software portion
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* of the descriptor.
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*
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* NB: the caller is responsible for validating the memory contents
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* of the descriptor (e.g. flushing any cached copy).
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*/
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HAL_STATUS
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ar5210ProcRxDesc(struct ath_hal *ah, struct ath_desc *ds,
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uint32_t pa, struct ath_desc *nds, uint64_t tsf,
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struct ath_rx_status *rs)
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{
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struct ar5210_desc *ads = AR5210DESC(ds);
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struct ar5210_desc *ands = AR5210DESC(nds);
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uint32_t now, rstamp;
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if ((ads->ds_status1 & AR_Done) == 0)
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return HAL_EINPROGRESS;
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/*
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* Given the use of a self-linked tail be very sure that the hw is
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* done with this descriptor; the hw may have done this descriptor
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* once and picked it up again...make sure the hw has moved on.
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*/
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if ((ands->ds_status1 & AR_Done) == 0 && OS_REG_READ(ah, AR_RXDP) == pa)
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return HAL_EINPROGRESS;
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rs->rs_datalen = ads->ds_status0 & AR_DataLen;
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rstamp = MS(ads->ds_status1, AR_RcvTimestamp);
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/*
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* Convert timestamp. The value in the
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* descriptor is bits [10..22] of the TSF.
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*/
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now = (OS_REG_READ(ah, AR_TSF_L32) >> 10) & 0xffff;
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if ((now & 0x1fff) < rstamp)
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rstamp |= (now - 0x2000) & 0xffff;
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else
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rstamp |= now;
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/* NB: keep only 15 bits for consistency w/ other chips */
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rs->rs_tstamp = rstamp & 0x7fff;
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rs->rs_status = 0;
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if ((ads->ds_status1 & AR_FrmRcvOK) == 0) {
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if (ads->ds_status1 & AR_CRCErr)
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rs->rs_status |= HAL_RXERR_CRC;
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else if (ads->ds_status1 & AR_DecryptCRCErr)
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rs->rs_status |= HAL_RXERR_DECRYPT;
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else if (ads->ds_status1 & AR_FIFOOverrun)
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rs->rs_status |= HAL_RXERR_FIFO;
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else {
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rs->rs_status |= HAL_RXERR_PHY;
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rs->rs_phyerr =
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(ads->ds_status1 & AR_PHYErr) >> AR_PHYErr_S;
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}
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}
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/* XXX what about KeyCacheMiss? */
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rs->rs_rssi = MS(ads->ds_status0, AR_RcvSigStrength);
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if (ads->ds_status1 & AR_KeyIdxValid)
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rs->rs_keyix = MS(ads->ds_status1, AR_KeyIdx);
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else
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rs->rs_keyix = HAL_RXKEYIX_INVALID;
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/* NB: caller expected to do rate table mapping */
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rs->rs_rate = MS(ads->ds_status0, AR_RcvRate);
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rs->rs_antenna = (ads->ds_status0 & AR_RcvAntenna) ? 1 : 0;
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rs->rs_more = (ads->ds_status0 & AR_More) ? 1 : 0;
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return HAL_OK;
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}
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