296bffc9c0
Peter Wemm <peter@spinner.DIALix.COM>, Steve Passe <smp@csn.net> removed all the IPI_INTS code. made the XFAST_IPI32 code default, renaming Xfastipi32 to Xinvltlb. cleanup of i386/isa/isa_device.h to eliminate SMP dependancies: made the id_irq member of struct isa_device an u_int. made the id_drq member of struct isa_device an int. removed all other '#ifdefs' concerning SMP & APIC_IO. removed SMP/APIC_IO dependancies from if_ze.c.
540 lines
15 KiB
ArmAsm
540 lines
15 KiB
ArmAsm
/*
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* from: vector.s, 386BSD 0.1 unknown origin
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* $Id: vector.s,v 1.26 1997/04/26 11:46:07 peter Exp $
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*/
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/*
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* modified for PC98 by Kakefuda
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*/
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#include "opt_auto_eoi.h"
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#include "opt_smp.h"
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#if defined(SMP)
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#include <machine/smpasm.h> /* this includes <machine/apic.h> */
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#include <machine/smptests.h> /** TEST_CPUHITS */
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#endif /* SMP */
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#include <i386/isa/icu.h>
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#ifdef PC98
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#include <pc98/pc98/pc98.h>
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#else
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#include <i386/isa/isa.h>
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#endif
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#ifdef PC98
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#define ICU_IMR_OFFSET 2 /* IO_ICU{1,2} + 2 */
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#else
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#define ICU_IMR_OFFSET 1 /* IO_ICU{1,2} + 1 */
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#endif
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#if defined(SMP)
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#define GET_MPLOCK call _get_mplock
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#define REL_MPLOCK call _rel_mplock
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#else
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#define GET_MPLOCK /* NOP get Kernel Mutex */
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#define REL_MPLOCK /* NOP release mutex */
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#endif /* SMP */
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#if defined(APIC_IO)
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#if defined(SMP) && defined(TEST_CPUHITS)
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#undef GET_MPLOCK
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#define GET_MPLOCK \
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call _get_mplock ; \
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GETCPUID(%eax) ; \
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incl _cpuhits(,%eax,4)
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#endif /* SMP && TEST_CPUHITS */
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#define REDTBL_IDX(irq_num) (0x10 + ((irq_num) * 2))
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#define IRQ_BIT(irq_num) (1 << (irq_num))
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#define ENABLE_APIC \
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movl _apic_base, %eax ; \
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movl $0, APIC_EOI(%eax)
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#define ENABLE_ICU1 ENABLE_APIC
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#define ENABLE_ICU1_AND_2 ENABLE_APIC
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#define MASK_IRQ(irq_num,icu) \
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orl $IRQ_BIT(irq_num),_imen ; /* set the mask bit */ \
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movl _io_apic_base,%ecx ; /* io apic addr */ \
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \
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orl $IOART_INTMASK,%eax ; /* set the mask */ \
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movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */
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#define UNMASK_IRQ(irq_num,icu) \
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andl $~IRQ_BIT(irq_num),_imen ; /* clear mask bit */ \
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movl _io_apic_base,%ecx ; /* io apic addr */ \
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movl $REDTBL_IDX(irq_num),(%ecx) ; /* write the index */ \
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movl IOAPIC_WINDOW(%ecx),%eax ; /* current value */ \
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andl $~IOART_INTMASK,%eax ; /* clear the mask */ \
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movl %eax,IOAPIC_WINDOW(%ecx) ; /* new value */
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#define TEST_IRQ(irq_num,reg) \
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testl $IRQ_BIT(irq_num),%eax
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#define SET_IPENDING(irq_num) \
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orl $IRQ_BIT(irq_num),_ipending
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/*
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* 'lazy masking' code submitted by: Bruce Evans <bde@zeta.org.au>
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*/
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#define MAYBE_MASK_IRQ(irq_num,icu) \
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testl $IRQ_BIT(irq_num),iactive ; /* lazy masking */ \
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je 1f ; /* NOT currently active */ \
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MASK_IRQ(irq_num,icu) ; \
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ENABLE_APIC ; \
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SET_IPENDING(irq_num) ; \
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REL_MPLOCK ; /* SMP release global lock */ \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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1: ; \
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orl $IRQ_BIT(irq_num),iactive
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#define MAYBE_UNMASK_IRQ(irq_num,icu) \
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andl $~IRQ_BIT(irq_num),iactive ; \
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testl $IRQ_BIT(irq_num),_imen ; \
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je 3f ; \
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UNMASK_IRQ(irq_num,icu) ; \
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3:
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#else /* APIC_IO */
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#define MASK_IRQ(irq_num,icu) \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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orb $IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET
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#define UNMASK_IRQ(irq_num,icu) \
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movb _imen + IRQ_BYTE(irq_num),%al ; \
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andb $~IRQ_BIT(irq_num),%al ; \
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movb %al,_imen + IRQ_BYTE(irq_num) ; \
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outb %al,$icu+ICU_IMR_OFFSET
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#define TEST_IRQ(irq_num,reg) \
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testb $IRQ_BIT(irq_num),%reg
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#define SET_IPENDING(irq_num) \
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orb $IRQ_BIT(irq_num),_ipending + IRQ_BYTE(irq_num)
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#define ICU_EOI 0x20 /* XXX - define elsewhere */
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#define IRQ_BIT(irq_num) (1 << ((irq_num) % 8))
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#define IRQ_BYTE(irq_num) ((irq_num) / 8)
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#ifdef AUTO_EOI_1
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#define ENABLE_ICU1 /* use auto-EOI to reduce i/o */
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#define OUTB_ICU1
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#else
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#define ENABLE_ICU1 \
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movb $ICU_EOI,%al ; /* as soon as possible send EOI ... */ \
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OUTB_ICU1 /* ... to clear in service bit */
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#define OUTB_ICU1 \
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outb %al,$IO_ICU1
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#endif
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#ifdef AUTO_EOI_2
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/*
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* The data sheet says no auto-EOI on slave, but it sometimes works.
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*/
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#define ENABLE_ICU1_AND_2 ENABLE_ICU1
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#else
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#define ENABLE_ICU1_AND_2 \
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movb $ICU_EOI,%al ; /* as above */ \
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outb %al,$IO_ICU2 ; /* but do second icu first ... */ \
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OUTB_ICU1 /* ... then first icu (if !AUTO_EOI_1) */
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#endif
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#define MAYBE_MASK_IRQ(irq_num,icu) \
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MASK_IRQ(irq_num,icu)
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#define MAYBE_UNMASK_IRQ(irq_num,icu) \
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UNMASK_IRQ(irq_num,icu)
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#endif /* APIC_IO */
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#ifdef FAST_INTR_HANDLER_USES_ES
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#define ACTUALLY_PUSHED 1
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#define MAYBE_MOVW_AX_ES movl %ax,%es
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#define MAYBE_POPL_ES popl %es
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#define MAYBE_PUSHL_ES pushl %es
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#else
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/*
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* We can usually skip loading %es for fastintr handlers. %es should
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* only be used for string instructions, and fastintr handlers shouldn't
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* do anything slow enough to justify using a string instruction.
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*/
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#define ACTUALLY_PUSHED 0
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#define MAYBE_MOVW_AX_ES
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#define MAYBE_POPL_ES
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#define MAYBE_PUSHL_ES
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#endif
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/*
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* Macros for interrupt interrupt entry, call to handler, and exit.
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*
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* XXX - the interrupt frame is set up to look like a trap frame. This is
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* usually a waste of time. The only interrupt handlers that want a frame
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* are the clock handler (it wants a clock frame), the npx handler (it's
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* easier to do right all in assembler). The interrupt return routine
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* needs a trap frame for rare AST's (it could easily convert the frame).
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* The direct costs of setting up a trap frame are two pushl's (error
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* code and trap number), an addl to get rid of these, and pushing and
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* popping the call-saved regs %esi, %edi and %ebp twice, The indirect
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* costs are making the driver interface nonuniform so unpending of
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* interrupts is more complicated and slower (call_driver(unit) would
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* be easier than ensuring an interrupt frame for all handlers. Finally,
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* there are some struct copies in the npx handler and maybe in the clock
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* handler that could be avoided by working more with pointers to frames
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* instead of frames.
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*
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* XXX - should we do a cld on every system entry to avoid the requirement
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* for scattered cld's?
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*
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* Coding notes for *.s:
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*
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* If possible, avoid operations that involve an operand size override.
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* Word-sized operations might be smaller, but the operand size override
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* makes them slower on on 486's and no faster on 386's unless perhaps
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* the instruction pipeline is depleted. E.g.,
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*
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* Use movl to seg regs instead of the equivalent but more descriptive
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* movw - gas generates an irelevant (slower) operand size override.
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*
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* Use movl to ordinary regs in preference to movw and especially
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* in preference to movz[bw]l. Use unsigned (long) variables with the
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* top bits clear instead of unsigned short variables to provide more
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* opportunities for movl.
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*
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* If possible, use byte-sized operations. They are smaller and no slower.
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*
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* Use (%reg) instead of 0(%reg) - gas generates larger code for the latter.
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*
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* If the interrupt frame is made more flexible, INTR can push %eax first
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* and decide the ipending case with less overhead, e.g., by avoiding
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* loading segregs.
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*/
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#define FAST_INTR(irq_num, vec_name, enable_icus) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl %eax ; /* save only call-used registers */ \
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pushl %ecx ; \
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pushl %edx ; \
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pushl %ds ; \
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MAYBE_PUSHL_ES ; \
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movl $KDSEL,%eax ; \
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movl %ax,%ds ; \
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MAYBE_MOVW_AX_ES ; \
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FAKE_MCOUNT((4+ACTUALLY_PUSHED)*4(%esp)) ; \
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GET_MPLOCK ; /* SMP Spin lock */ \
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pushl _intr_unit + (irq_num) * 4 ; \
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call *_intr_handler + (irq_num) * 4 ; /* do the work ASAP */ \
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enable_icus ; /* (re)enable ASAP (helps edge trigger?) */ \
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addl $4,%esp ; \
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incl _cnt+V_INTR ; /* book-keeping can wait */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; /* are we unmasking pending HWIs or SWIs? */ \
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notl %eax ; \
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andl _ipending,%eax ; \
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jne 2f ; /* yes, maybe handle them */ \
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1: ; \
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MEXITCOUNT ; \
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REL_MPLOCK ; /* SMP release global lock */ \
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MAYBE_POPL_ES ; \
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popl %ds ; \
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popl %edx ; \
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popl %ecx ; \
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popl %eax ; \
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iret ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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cmpb $3,_intr_nesting_level ; /* is there enough stack? */ \
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jae 1b ; /* no, return */ \
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movl _cpl,%eax ; \
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/* XXX next line is probably unnecessary now. */ \
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movl $HWI_MASK|SWI_MASK,_cpl ; /* limit nesting ... */ \
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incb _intr_nesting_level ; /* ... really limit it ... */ \
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sti ; /* ... to do this as early as possible */ \
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MAYBE_POPL_ES ; /* discard most of thin frame ... */ \
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popl %ecx ; /* ... original %ds ... */ \
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popl %edx ; \
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xchgl %eax,4(%esp) ; /* orig %eax; save cpl */ \
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pushal ; /* build fat frame (grrr) ... */ \
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pushl %ecx ; /* ... actually %ds ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; \
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movl %ax,%es ; \
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movl (2+8+0)*4(%esp),%ecx ; /* ... %ecx from thin frame ... */ \
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movl %ecx,(2+6)*4(%esp) ; /* ... to fat frame ... */ \
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movl (2+8+1)*4(%esp),%eax ; /* ... cpl from thin frame */ \
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pushl %eax ; \
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subl $4,%esp ; /* junk for unit number */ \
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MEXITCOUNT ; \
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jmp _doreti
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#define INTR(irq_num, vec_name, icu, enable_icus, reg) \
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.text ; \
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SUPERALIGN_TEXT ; \
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IDTVEC(vec_name) ; \
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pushl $0 ; /* dummy error code */ \
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pushl $0 ; /* dummy trap type */ \
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pushal ; \
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pushl %ds ; /* save our data and extra segments ... */ \
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pushl %es ; \
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movl $KDSEL,%eax ; /* ... and reload with kernel's own ... */ \
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movl %ax,%ds ; /* ... early for obsolete reasons */ \
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movl %ax,%es ; \
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GET_MPLOCK ; /* SMP Spin lock */ \
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MAYBE_MASK_IRQ(irq_num,icu) ; \
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enable_icus ; \
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movl _cpl,%eax ; \
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TEST_IRQ(irq_num,reg) ; \
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jne 2f ; \
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incb _intr_nesting_level ; \
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__CONCAT(Xresume,irq_num): ; \
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FAKE_MCOUNT(12*4(%esp)) ; /* XXX late to avoid double count */ \
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incl _cnt+V_INTR ; /* tally interrupts */ \
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movl _intr_countp + (irq_num) * 4,%eax ; \
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incl (%eax) ; \
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movl _cpl,%eax ; \
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pushl %eax ; \
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pushl _intr_unit + (irq_num) * 4 ; \
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orl _intr_mask + (irq_num) * 4,%eax ; \
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movl %eax,_cpl ; \
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sti ; \
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call *_intr_handler + (irq_num) * 4 ; \
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cli ; /* must unmask _imen and icu atomically */ \
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MAYBE_UNMASK_IRQ(irq_num,icu) ; \
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sti ; /* XXX _doreti repeats the cli/sti */ \
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MEXITCOUNT ; \
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/* We could usually avoid the following jmp by inlining some of */ \
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/* _doreti, but it's probably better to use less cache. */ \
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jmp _doreti ; \
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; \
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ALIGN_TEXT ; \
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2: ; \
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/* XXX skip mcounting here to avoid double count */ \
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SET_IPENDING(irq_num) ; \
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REL_MPLOCK ; /* SMP release global lock */ \
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popl %es ; \
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popl %ds ; \
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popal ; \
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addl $4+4,%esp ; \
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iret
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#if defined(APIC_IO)
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.text
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SUPERALIGN_TEXT
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.globl _Xinvltlb
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_Xinvltlb:
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pushl %eax
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movl %cr3, %eax
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movl %eax, %cr3
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#if 0
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/** XXX FIXME: convert to Bruces suggested 'ss' style, eliminating %ds */
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ss
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incl _ipihits
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ss
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movl _apic_base, %eax
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ss
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movl $0, APIC_EOI(%eax)
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#else
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pushl %ds
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movl $KDSEL,%eax
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movl %ax,%ds
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incl _ipihits
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movl _apic_base, %eax
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movl $0, APIC_EOI(%eax)
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popl %ds
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#endif
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popl %eax
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iret
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#endif /* APIC_IO */
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MCOUNT_LABEL(bintr)
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FAST_INTR(0,fastintr0, ENABLE_ICU1)
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FAST_INTR(1,fastintr1, ENABLE_ICU1)
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FAST_INTR(2,fastintr2, ENABLE_ICU1)
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FAST_INTR(3,fastintr3, ENABLE_ICU1)
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FAST_INTR(4,fastintr4, ENABLE_ICU1)
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FAST_INTR(5,fastintr5, ENABLE_ICU1)
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FAST_INTR(6,fastintr6, ENABLE_ICU1)
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FAST_INTR(7,fastintr7, ENABLE_ICU1)
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FAST_INTR(8,fastintr8, ENABLE_ICU1_AND_2)
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FAST_INTR(9,fastintr9, ENABLE_ICU1_AND_2)
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FAST_INTR(10,fastintr10, ENABLE_ICU1_AND_2)
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FAST_INTR(11,fastintr11, ENABLE_ICU1_AND_2)
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FAST_INTR(12,fastintr12, ENABLE_ICU1_AND_2)
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FAST_INTR(13,fastintr13, ENABLE_ICU1_AND_2)
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FAST_INTR(14,fastintr14, ENABLE_ICU1_AND_2)
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FAST_INTR(15,fastintr15, ENABLE_ICU1_AND_2)
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#if defined(APIC_IO)
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FAST_INTR(16,fastintr16, ENABLE_ICU1_AND_2)
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FAST_INTR(17,fastintr17, ENABLE_ICU1_AND_2)
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FAST_INTR(18,fastintr18, ENABLE_ICU1_AND_2)
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FAST_INTR(19,fastintr19, ENABLE_ICU1_AND_2)
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FAST_INTR(20,fastintr20, ENABLE_ICU1_AND_2)
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FAST_INTR(21,fastintr21, ENABLE_ICU1_AND_2)
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FAST_INTR(22,fastintr22, ENABLE_ICU1_AND_2)
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FAST_INTR(23,fastintr23, ENABLE_ICU1_AND_2)
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#endif /* APIC_IO */
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INTR(0,intr0, IO_ICU1, ENABLE_ICU1, al)
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INTR(1,intr1, IO_ICU1, ENABLE_ICU1, al)
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INTR(2,intr2, IO_ICU1, ENABLE_ICU1, al)
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INTR(3,intr3, IO_ICU1, ENABLE_ICU1, al)
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INTR(4,intr4, IO_ICU1, ENABLE_ICU1, al)
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INTR(5,intr5, IO_ICU1, ENABLE_ICU1, al)
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INTR(6,intr6, IO_ICU1, ENABLE_ICU1, al)
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INTR(7,intr7, IO_ICU1, ENABLE_ICU1, al)
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INTR(8,intr8, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(9,intr9, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(10,intr10, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(11,intr11, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(12,intr12, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(13,intr13, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(14,intr14, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(15,intr15, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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#if defined(APIC_IO)
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INTR(16,intr16, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(17,intr17, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(18,intr18, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(19,intr19, IO_ICU2, ENABLE_ICU1_AND_2, ah)
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INTR(20,intr20, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
|
INTR(21,intr21, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
|
INTR(22,intr22, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
|
INTR(23,intr23, IO_ICU2, ENABLE_ICU1_AND_2, ah)
|
|
#endif /* APIC_IO */
|
|
MCOUNT_LABEL(eintr)
|
|
|
|
.data
|
|
ihandlers: /* addresses of interrupt handlers */
|
|
/* actually resumption addresses for HWI's */
|
|
.long Xresume0, Xresume1, Xresume2, Xresume3
|
|
.long Xresume4, Xresume5, Xresume6, Xresume7
|
|
.long Xresume8, Xresume9, Xresume10, Xresume11
|
|
.long Xresume12, Xresume13, Xresume14, Xresume15
|
|
#if defined(APIC_IO)
|
|
.long Xresume16, Xresume17, Xresume18, Xresume19
|
|
.long Xresume20, Xresume21, Xresume22, Xresume23
|
|
.long 0, 0, 0, 0, swi_tty, swi_net, _softclock, swi_ast
|
|
#else
|
|
.long swi_tty, swi_net, 0, 0, 0, 0, 0, 0
|
|
.long 0, 0, 0, 0, 0, 0, _softclock, swi_ast
|
|
#endif /* APIC_IO */
|
|
|
|
imasks: /* masks for interrupt handlers */
|
|
.space NHWI*4 /* padding; HWI masks are elsewhere */
|
|
|
|
#if defined(APIC_IO)
|
|
.long 0, 0, 0, 0 /* padding */
|
|
.long SWI_TTY_MASK, SWI_NET_MASK, SWI_CLOCK_MASK, SWI_AST_MASK
|
|
#else
|
|
.long SWI_TTY_MASK, SWI_NET_MASK, 0, 0, 0, 0, 0, 0
|
|
.long 0, 0, 0, 0, 0, 0, SWI_CLOCK_MASK, SWI_AST_MASK
|
|
#endif /* APIC_IO */
|
|
|
|
.globl _intr_nesting_level
|
|
_intr_nesting_level:
|
|
.byte 0
|
|
.space 3
|
|
|
|
#if defined(APIC_IO)
|
|
|
|
.globl _ivectors
|
|
_ivectors:
|
|
.long _Xintr0, _Xintr1, _Xintr2, _Xintr3
|
|
.long _Xintr4, _Xintr5, _Xintr6, _Xintr7
|
|
.long _Xintr8, _Xintr9, _Xintr10, _Xintr11
|
|
.long _Xintr12, _Xintr13, _Xintr14, _Xintr15
|
|
.long _Xintr16, _Xintr17, _Xintr18, _Xintr19
|
|
.long _Xintr20, _Xintr21, _Xintr22, _Xintr23
|
|
|
|
/* active flag for lazy masking */
|
|
iactive:
|
|
.long 0
|
|
|
|
.globl _ipihits
|
|
_ipihits:
|
|
.long 0
|
|
|
|
#if defined(TEST_CPUHITS)
|
|
.globl _cpuhits
|
|
_cpuhits:
|
|
#if !defined(NCPU)
|
|
/**
|
|
* FIXME: need a way to pass NCPU to .s files.
|
|
* NCPU currently defined in smp.h IF NOT defined in opt_smp.h.
|
|
*/
|
|
#define NCPU 4
|
|
#endif /* NCPU */
|
|
.space NCPU*4
|
|
#endif /* TEST_CPUHITS */
|
|
|
|
#endif /* APIC_IO */
|
|
|
|
/*
|
|
* Interrupt counters and names. The format of these and the label names
|
|
* must agree with what vmstat expects. The tables are indexed by device
|
|
* ids so that we don't have to move the names around as devices are
|
|
* attached.
|
|
*/
|
|
#include "vector.h"
|
|
.globl _intrcnt, _eintrcnt
|
|
_intrcnt:
|
|
.space (NR_DEVICES + ICU_LEN) * 4
|
|
_eintrcnt:
|
|
|
|
.globl _intrnames, _eintrnames
|
|
_intrnames:
|
|
.ascii DEVICE_NAMES
|
|
.asciz "stray irq0"
|
|
.asciz "stray irq1"
|
|
.asciz "stray irq2"
|
|
.asciz "stray irq3"
|
|
.asciz "stray irq4"
|
|
.asciz "stray irq5"
|
|
.asciz "stray irq6"
|
|
.asciz "stray irq7"
|
|
.asciz "stray irq8"
|
|
.asciz "stray irq9"
|
|
.asciz "stray irq10"
|
|
.asciz "stray irq11"
|
|
.asciz "stray irq12"
|
|
.asciz "stray irq13"
|
|
.asciz "stray irq14"
|
|
.asciz "stray irq15"
|
|
#if defined(APIC_IO)
|
|
.asciz "stray irq16"
|
|
.asciz "stray irq17"
|
|
.asciz "stray irq18"
|
|
.asciz "stray irq19"
|
|
.asciz "stray irq20"
|
|
.asciz "stray irq21"
|
|
.asciz "stray irq22"
|
|
.asciz "stray irq23"
|
|
#endif /* APIC_IO */
|
|
_eintrnames:
|
|
|
|
.text
|