Adrian Chadd 1455de1775 The i8259 controller is initialized incorrectly on MALTA. It writes ... mask bits to control register and control bits to mask register. The former causes ICW1_RESET|ICW1_LTIM combination to be written to control register, which on QEMU results in "level sensitive irq not supported" error. Submitted by: Robert Millan <rmh@debian.org>		2011-07-16 00:30:23 +00:00
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files.malta	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00
gt_pci.c	The i8259 controller is initialized incorrectly on MALTA. It writes	2011-07-16 00:30:23 +00:00
gt.c	Fix path in all includes: remove /mips32 subdirectory	2008-09-10 03:49:08 +00:00
gtreg.h	The NetBSD Foundation has granted permission to remove clause 3 and 4 from	2010-03-03 17:55:51 +00:00
gtvar.h
malta_machdep.c	- dump_avail layout should be sequence of [start, end)	2010-12-09 07:47:40 +00:00
maltareg.h	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00
obio.c	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00
obiovar.h
std.malta	Switch the GENERIC kernels for all architectures to the new CAM-based ATA	2011-04-24 08:58:58 +00:00
uart_bus_maltausart.c	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00
uart_cpu_maltausart.c	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00
yamon.c	Fix copyrights to reflect the origin of these files.	2009-06-29 16:45:50 +00:00
yamon.h	Merge from projects/mips to head by hand:	2010-01-10 20:06:14 +00:00