f7c13d78db
- recognize ports and vlangroups based on DTS file - support multi-chip addresing mode (required in upcoming Armada-388-Clearfog support) - refactor attachment function Each port in 'dsa' node should have 'vlangroup' property. Otherwise, e6000sw will fail to attach. Submitted by: Bartosz Szczepanek <bsz@semihalf.com> Konrad Adamczyk <ka@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential revision: https://reviews.freebsd.org/D7328
186 lines
4.8 KiB
C
186 lines
4.8 KiB
C
/*-
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* Copyright (c) 2015 Semihalf
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* Copyright (c) 2015 Stormshield
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _E6000SWREG_H_
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#define _E6000SWREG_H_
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struct atu_opt {
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uint16_t mac_01;
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uint16_t mac_23;
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uint16_t mac_45;
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uint16_t fid;
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};
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/*
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* Definitions for the Marvell 88E6000 series Ethernet Switch.
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*/
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/*
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* Switch Registers
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*/
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#define REG_GLOBAL 0x1b
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#define REG_GLOBAL2 0x1c
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#define REG_PORT(p) (0x10 + (p))
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#define REG_NUM_MAX 31
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/*
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* Per-Port Switch Registers
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*/
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#define PORT_STATUS 0x0
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#define PSC_CONTROL 0x1
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#define SWITCH_ID 0x3
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#define PORT_CONTROL 0x4
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#define PORT_CONTROL_1 0x5
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#define PORT_VLAN_MAP 0x6
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#define PORT_VID 0x7
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#define PORT_ASSOCIATION_VECTOR 0xb
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#define PORT_ATU_CTRL 0xc
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#define RX_COUNTER 0x12
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#define TX_COUNTER 0x13
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#define PORT_VID_DEF_VID 0
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#define PORT_VID_DEF_VID_MASK 0xfff
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#define PORT_VID_PRIORITY_MASK 0xc00
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#define PORT_CONTROL_ENABLE 0x3
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/* PORT_VLAN fields */
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#define PORT_VLAN_MAP_TABLE_MASK 0x7f
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#define PORT_VLAN_MAP_FID 12
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#define PORT_VLAN_MAP_FID_MASK 0xf000
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/*
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* Switch Global Register 1 accessed via REG_GLOBAL_ADDR
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*/
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#define SWITCH_GLOBAL_STATUS 0
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#define SWITCH_GLOBAL_CONTROL 4
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#define SWITCH_GLOBAL_CONTROL2 28
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#define MONITOR_CONTROL 26
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/* ATU operation */
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#define ATU_FID 1
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#define ATU_CONTROL 10
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#define ATU_OPERATION 11
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#define ATU_DATA 12
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#define ATU_MAC_ADDR01 13
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#define ATU_MAC_ADDR23 14
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#define ATU_MAC_ADDR45 15
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#define ATU_UNIT_BUSY (1 << 15)
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#define ENTRY_STATE 0xf
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/* ATU_CONTROL fields */
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#define ATU_CONTROL_AGETIME 4
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#define ATU_CONTROL_AGETIME_MASK 0xff0
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#define ATU_CONTROL_LEARN2ALL 3
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/* ATU opcode */
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#define NO_OPERATION (0 << 0)
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#define FLUSH_ALL (1 << 0)
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#define FLUSH_NON_STATIC (1 << 1)
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#define LOAD_FROM_FIB (3 << 0)
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#define PURGE_FROM_FIB (3 << 0)
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#define GET_NEXT_IN_FIB (1 << 2)
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#define FLUSH_ALL_IN_FIB (5 << 0)
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#define FLUSH_NON_STATIC_IN_FIB (3 << 1)
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#define GET_VIOLATION_DATA (7 << 0)
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#define CLEAR_VIOLATION_DATA (7 << 0)
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/* ATU Stats */
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#define COUNT_ALL (0 << 0)
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/*
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* Switch Global Register 2 accessed via REG_GLOBAL2_ADDR
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*/
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#define MGMT_EN_2x 2
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#define MGMT_EN_0x 3
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#define SWITCH_MGMT 5
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#define ATU_STATS 14
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#define MGMT_EN_ALL 0xffff
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/* SWITCH_MGMT fields */
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#define SWITCH_MGMT_PRI 0
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#define SWITCH_MGMT_PRI_MASK 7
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#define SWITCH_MGMT_RSVD2CPU 3
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#define SWITCH_MGMT_FC_PRI 4
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#define SWITCH_MGMT_FC_PRI_MASK (7 << 4)
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#define SWITCH_MGMT_FORCEFLOW 7
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/* ATU_STATS fields */
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#define ATU_STATS_BIN 14
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#define ATU_STATS_FLAG 12
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/*
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* PHY registers accessed via 'Switch Global Registers' (REG_GLOBAL2).
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*/
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#define SMI_PHY_CMD_REG 0x18
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#define SMI_PHY_DATA_REG 0x19
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#define PHY_CMD 0x18
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#define PHY_DATA 0x19
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#define PHY_DATA_MASK 0xffff
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#define PHY_CMD_SMI_BUSY 15
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#define PHY_CMD_MODE 12
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#define PHY_CMD_MODE_MDIO 1
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#define PHY_CMD_MODE_XMDIO 0
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#define PHY_CMD_OPCODE 10
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#define PHY_CMD_OPCODE_WRITE 1
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#define PHY_CMD_OPCODE_READ 2
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#define PHY_CMD_DEV_ADDR 5
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#define PHY_CMD_DEV_ADDR_MASK 0x3e0
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#define PHY_CMD_REG_ADDR 0
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#define PHY_CMD_REG_ADDR_MASK 0x1f
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#define PHY_PAGE_REG 22
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/*
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* Scratch and Misc register accessed via
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* 'Switch Global Registers' (REG_GLOBAL2)
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*/
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#define SCR_AND_MISC_REG 0x1a
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#define SCR_AND_MISC_PTR_CFG 0x7000
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#define SCR_AND_MISC_DATA_CFG_MASK 0xf0
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#define E6000SW_NUM_PHY_REGS 29
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#define E6000SW_NUM_VGROUPS 8
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#define E6000SW_MAX_PORTS 10
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#define E6000SW_PORT_NO_VGROUP -1
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#define E6000SW_DEFAULT_AGETIME 20
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#define E6000SW_RETRIES 100
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#define E6000SW_SMI_TIMEOUT 16
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#endif /* _E6000SWREG_H_ */
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