1d4fd9f5a8
The platform that supports SMP currently is a SWARM with a dual-core Sibyte processor. The kernel config file to use is SWARM_SMP. Reviewed by: imp, rrs
270 lines
6.9 KiB
C
270 lines
6.9 KiB
C
/*-
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* Copyright (c) 2006 Oleksandr Tymoshenko
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <machine/clock.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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static struct intr_event *hardintr_events[NHARD_IRQS];
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static struct intr_event *softintr_events[NSOFT_IRQS];
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static mips_intrcnt_t mips_intr_counters[NSOFT_IRQS + NHARD_IRQS];
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static int intrcnt_index;
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static cpu_intr_mask_t hardintr_mask_func;
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static cpu_intr_unmask_t hardintr_unmask_func;
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mips_intrcnt_t
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mips_intrcnt_create(const char* name)
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{
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mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
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mips_intrcnt_setname(counter, name);
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return counter;
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}
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void
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mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
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{
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int idx = counter - intrcnt;
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KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
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snprintf(intrnames + (MAXCOMLEN + 1) * idx,
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MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
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}
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static void
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mips_mask_hard_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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mips_wr_status(mips_rd_status() & ~(((1 << irq) << 8) << 2));
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}
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static void
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mips_unmask_hard_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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mips_wr_status(mips_rd_status() | (((1 << irq) << 8) << 2));
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}
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static void
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mips_mask_soft_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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mips_wr_status(mips_rd_status() & ~((1 << irq) << 8));
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}
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static void
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mips_unmask_soft_irq(void *source)
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{
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uintptr_t irq = (uintptr_t)source;
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mips_wr_status(mips_rd_status() | ((1 << irq) << 8));
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}
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/*
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* Perform initialization of interrupts prior to setting
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* handlings
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*/
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void
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cpu_init_interrupts()
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{
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int i;
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char name[MAXCOMLEN + 1];
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/*
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* Initialize all available vectors so spare IRQ
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* would show up in systat output
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*/
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for (i = 0; i < NSOFT_IRQS; i++) {
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snprintf(name, MAXCOMLEN + 1, "sint%d:", i);
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mips_intr_counters[i] = mips_intrcnt_create(name);
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}
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for (i = 0; i < NHARD_IRQS; i++) {
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snprintf(name, MAXCOMLEN + 1, "int%d:", i);
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mips_intr_counters[NSOFT_IRQS + i] = mips_intrcnt_create(name);
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}
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}
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void
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cpu_set_hardintr_mask_func(cpu_intr_mask_t func)
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{
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hardintr_mask_func = func;
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}
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void
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cpu_set_hardintr_unmask_func(cpu_intr_unmask_t func)
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{
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hardintr_unmask_func = func;
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}
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void
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cpu_establish_hardintr(const char *name, driver_filter_t *filt,
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void (*handler)(void*), void *arg, int irq, int flags, void **cookiep)
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{
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struct intr_event *event;
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int error;
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/*
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* We have 6 levels, but thats 0 - 5 (not including 6)
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*/
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if (irq < 0 || irq >= NHARD_IRQS)
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panic("%s called for unknown hard intr %d", __func__, irq);
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if (hardintr_mask_func == NULL)
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hardintr_mask_func = mips_mask_hard_irq;
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if (hardintr_unmask_func == NULL)
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hardintr_unmask_func = mips_unmask_hard_irq;
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event = hardintr_events[irq];
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if (event == NULL) {
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error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
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irq, hardintr_mask_func, hardintr_unmask_func,
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NULL, NULL, "int%d", irq);
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if (error)
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return;
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hardintr_events[irq] = event;
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mips_unmask_hard_irq((void*)(uintptr_t)irq);
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}
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intr_event_add_handler(event, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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mips_intrcnt_setname(mips_intr_counters[NSOFT_IRQS + irq],
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event->ie_fullname);
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}
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void
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cpu_establish_softintr(const char *name, driver_filter_t *filt,
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void (*handler)(void*), void *arg, int irq, int flags,
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void **cookiep)
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{
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struct intr_event *event;
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int error;
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#if 0
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printf("Establish SOFT IRQ %d: filt %p handler %p arg %p\n",
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irq, filt, handler, arg);
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#endif
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if (irq < 0 || irq > NSOFT_IRQS)
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panic("%s called for unknown hard intr %d", __func__, irq);
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event = softintr_events[irq];
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if (event == NULL) {
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error = intr_event_create(&event, (void *)(uintptr_t)irq, 0,
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irq, mips_mask_soft_irq, mips_unmask_soft_irq,
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NULL, NULL, "sint%d:", irq);
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if (error)
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return;
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softintr_events[irq] = event;
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mips_unmask_soft_irq((void*)(uintptr_t)irq);
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}
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intr_event_add_handler(event, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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mips_intrcnt_setname(mips_intr_counters[irq], event->ie_fullname);
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}
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void
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cpu_intr(struct trapframe *tf)
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{
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struct intr_event *event;
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register_t cause, status;
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int hard, i, intr;
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critical_enter();
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cause = mips_rd_cause();
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status = mips_rd_status();
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intr = (cause & MIPS_INT_MASK) >> 8;
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/*
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* Do not handle masked interrupts. They were masked by
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* pre_ithread function (mips_mask_XXX_intr) and will be
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* unmasked once ithread is through with handler
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*/
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intr &= (status & MIPS_INT_MASK) >> 8;
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while ((i = fls(intr)) != 0) {
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intr &= ~(1 << (i - 1));
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switch (i) {
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case 1: case 2:
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/* Software interrupt. */
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i--; /* Get a 0-offset interrupt. */
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hard = 0;
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event = softintr_events[i];
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mips_intrcnt_inc(mips_intr_counters[i]);
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break;
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default:
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/* Hardware interrupt. */
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i -= 2; /* Trim software interrupt bits. */
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i--; /* Get a 0-offset interrupt. */
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hard = 1;
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event = hardintr_events[i];
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mips_intrcnt_inc(mips_intr_counters[NSOFT_IRQS + i]);
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break;
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}
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if (!event || TAILQ_EMPTY(&event->ie_handlers)) {
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printf("stray %s interrupt %d\n",
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hard ? "hard" : "soft", i);
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continue;
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}
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if (intr_event_handle(event, tf) != 0) {
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printf("stray %s interrupt %d\n",
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hard ? "hard" : "soft", i);
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}
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}
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KASSERT(i == 0, ("all interrupts handled"));
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critical_exit();
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}
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