718cf2ccb9
Mainly focus on files that use BSD 2-Clause license, however the tool I was using misidentified many licenses so this was mostly a manual - error prone - task. The Software Package Data Exchange (SPDX) group provides a specification to make it easier for automated tools to detect and summarize well known opensource licenses. We are gradually adopting the specification, noting that the tags are considered only advisory and do not, in any way, superceed or replace the license texts.
338 lines
9.6 KiB
C
338 lines
9.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-4-Clause
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*
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* Copyright (c) 1994 Charles Hannum.
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* Copyright (c) 1994 Jarle Greipsland.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Jarle Greipsland
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* 4. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#define SCSISEQ 0x00 /* SCSI sequence control */
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#define SXFRCTL0 0x01 /* SCSI transfer control 0 */
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#define SXFRCTL1 0x02 /* SCSI transfer control 1 */
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#define SCSISIGI 0x03 /* SCSI signal in */
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#define SCSISIGO 0x03 /* SCSI signal out */
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#define SCSIRATE 0x04 /* SCSI rate control */
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#define SCSIID 0x05 /* SCSI ID */
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#define SELID 0x05 /* Selection/Reselection ID */
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#define SCSIDAT 0x06 /* SCSI Latched Data */
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#define SCSIBUS 0x07 /* SCSI Data Bus*/
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#define STCNT0 0x08 /* SCSI transfer count */
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#define STCNT1 0x09
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#define STCNT2 0x0a
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#define CLRSINT0 0x0b /* Clear SCSI interrupts 0 */
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#define SSTAT0 0x0b /* SCSI interrupt status 0 */
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#define CLRSINT1 0x0c /* Clear SCSI interrupts 1 */
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#define SSTAT1 0x0c /* SCSI status 1 */
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#define SSTAT2 0x0d /* SCSI status 2 */
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#define SCSITEST 0x0e /* SCSI test control */
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#define SSTAT3 0x0e /* SCSI status 3 */
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#define CLRSERR 0x0f /* Clear SCSI errors */
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#define SSTAT4 0x0f /* SCSI status 4 */
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#define SIMODE0 0x10 /* SCSI interrupt mode 0 */
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#define SIMODE1 0x11 /* SCSI interrupt mode 1 */
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#define DMACNTRL0 0x12 /* DMA control 0 */
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#define DMACNTRL1 0x13 /* DMA control 1 */
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#define DMASTAT 0x14 /* DMA status */
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#define FIFOSTAT 0x15 /* FIFO status */
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#define DMADATA 0x16 /* DMA data */
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#define DMADATAL 0x16 /* DMA data low byte */
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#define DMADATAH 0x17 /* DMA data high byte */
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#define BRSTCNTRL 0x18 /* Burst Control */
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#define DMADATALONG 0x18
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#define PORTA 0x1a /* Port A */
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#define PORTB 0x1b /* Port B */
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#define REV 0x1c /* Revision (001 for 6360) */
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#define STACK 0x1d /* Stack */
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#define TEST 0x1e /* Test register */
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#define ID 0x1f /* ID register */
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#define IDSTRING_AIC6360 "(C)1991ADAPTECAIC6360 "
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#define IDSTRING_AIC6370 "(C)1994ADAPTECAIC6370"
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#define IDSTRING_GM82C700 "(C)1993 GoldStarGM82C700 "
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/* What all the bits do */
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/* SCSISEQ */
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#define TEMODEO 0x80
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#define ENSELO 0x40
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#define ENSELI 0x20
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#define ENRESELI 0x10
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#define ENAUTOATNO 0x08
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#define ENAUTOATNI 0x04
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#define ENAUTOATNP 0x02
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#define SCSIRSTO 0x01
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/* SXFRCTL0 */
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#define SCSIEN 0x80
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#define DMAEN 0x40
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#define CHEN 0x20
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#define CLRSTCNT 0x10
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#define SPIOEN 0x08
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#define CLRCH 0x02
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/* SXFRCTL1 */
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#define BITBUCKET 0x80
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#define SWRAPEN 0x40
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#define ENSPCHK 0x20
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#define STIMESEL1 0x10
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#define STIMESEL0 0x08
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#define STIMO_256ms 0x00
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#define STIMO_128ms 0x08
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#define STIMO_64ms 0x10
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#define STIMO_32ms 0x18
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#define ENSTIMER 0x04
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#define BYTEALIGN 0x02
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/* SCSISIGI */
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#define CDI 0x80
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#define IOI 0x40
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#define MSGI 0x20
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#define ATNI 0x10
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#define SELI 0x08
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#define BSYI 0x04
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#define REQI 0x02
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#define ACKI 0x01
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/* Important! The 3 most significant bits of this register, in initiator mode,
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* represents the "expected" SCSI bus phase and can be used to trigger phase
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* mismatch and phase change interrupts. But more important: If there is a
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* phase mismatch the chip will not transfer any data! This is actually a nice
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* feature as it gives us a bit more control over what is happening when we are
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* bursting data (in) through the FIFOs and the phase suddenly changes from
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* DATA IN to STATUS or MESSAGE IN. The transfer will stop and wait for the
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* proper phase to be set in this register instead of dumping the bits into the
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* FIFOs.
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*/
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/* SCSISIGO */
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#define CDO 0x80
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#define IOO 0x40
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#define MSGO 0x20
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#define ATNO 0x10
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#define SELO 0x08
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#define BSYO 0x04
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#define REQO 0x02
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#define ACKO 0x01
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/* Information transfer phases */
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#define PH_DATAOUT (0)
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#define PH_DATAIN (IOI)
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#define PH_CMD (CDI)
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#define PH_STAT (CDI|IOI)
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#define PH_MSGOUT (MSGI|CDI)
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#define PH_MSGIN (MSGI|CDI|IOI)
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#define PH_MASK (MSGI|CDI|IOI)
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/* SCSIRATE */
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#define SXFR2 0x40
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#define SXFR1 0x20
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#define SXFR0 0x10
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#define SOFS3 0x08
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#define SOFS2 0x04
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#define SOFS1 0x02
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#define SOFS0 0x01
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/* SCSI ID */
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#define OID2 0x40
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#define OID1 0x20
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#define OID0 0x10
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#define OID_S 4 /* shift value */
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#define TID2 0x04
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#define TID1 0x02
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#define TID0 0x01
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#define SCSI_ID_MASK 0x7
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/* SCSI selection/reselection ID (both target *and* initiator) */
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#define SELID7 0x80
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#define SELID6 0x40
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#define SELID5 0x20
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#define SELID4 0x10
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#define SELID3 0x08
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#define SELID2 0x04
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#define SELID1 0x02
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#define SELID0 0x01
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/* CLRSINT0 Clears what? (interrupt and/or status bit) */
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#define SETSDONE 0x80
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#define CLRSELDO 0x40 /* I */
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#define CLRSELDI 0x20 /* I+ */
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#define CLRSELINGO 0x10 /* I */
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#define CLRSWRAP 0x08 /* I+S */
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#define CLRSDONE 0x04 /* I+S */
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#define CLRSPIORDY 0x02 /* I */
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#define CLRDMADONE 0x01 /* I */
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/* SSTAT0 Howto clear */
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#define TARGET 0x80
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#define SELDO 0x40 /* Selfclearing */
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#define SELDI 0x20 /* Selfclearing when CLRSELDI is set */
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#define SELINGO 0x10 /* Selfclearing */
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#define SWRAP 0x08 /* CLRSWAP */
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#define SDONE 0x04 /* Not used in initiator mode */
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#define SPIORDY 0x02 /* Selfclearing (op on SCSIDAT) */
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#define DMADONE 0x01 /* Selfclearing (all FIFOs empty & T/C */
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/* CLRSINT1 Clears what? */
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#define CLRSELTIMO 0x80 /* I+S */
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#define CLRATNO 0x40
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#define CLRSCSIRSTI 0x20 /* I+S */
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#define CLRBUSFREE 0x08 /* I+S */
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#define CLRSCSIPERR 0x04 /* I+S */
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#define CLRPHASECHG 0x02 /* I+S */
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#define CLRREQINIT 0x01 /* I+S */
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/* SSTAT1 How to clear? When set?*/
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#define SELTO 0x80 /* C select out timeout */
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#define ATNTARG 0x40 /* Not used in initiator mode */
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#define SCSIRSTI 0x20 /* C RST asserted */
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#define PHASEMIS 0x10 /* Selfclearing */
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#define BUSFREE 0x08 /* C bus free condition */
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#define SCSIPERR 0x04 /* C parity error on inbound data */
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#define PHASECHG 0x02 /* C phase in SCSISIGI doesn't match */
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#define REQINIT 0x01 /* C or ACK asserting edge of REQ */
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/* SSTAT2 */
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#define SOFFSET 0x20
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#define SEMPTY 0x10
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#define SFULL 0x08
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#define SFCNT2 0x04
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#define SFCNT1 0x02
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#define SFCNT0 0x01
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/* SCSITEST */
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#define SCTESTU 0x08
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#define SCTESTD 0x04
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#define STCTEST 0x01
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/* SSTAT3 */
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#define SCSICNT3 0x80
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#define SCSICNT2 0x40
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#define SCSICNT1 0x20
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#define SCSICNT0 0x10
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#define OFFCNT3 0x08
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#define OFFCNT2 0x04
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#define OFFCNT1 0x02
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#define OFFCNT0 0x01
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/* CLRSERR */
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#define CLRSYNCERR 0x04
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#define CLRFWERR 0x02
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#define CLRFRERR 0x01
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/* SSTAT4 */
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#define SYNCERR 0x04
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#define FWERR 0x02
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#define FRERR 0x01
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/* SIMODE0 */
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#define ENSELDO 0x40
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#define ENSELDI 0x20
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#define ENSELINGO 0x10
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#define ENSWRAP 0x08
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#define ENSDONE 0x04
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#define ENSPIORDY 0x02
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#define ENDMADONE 0x01
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/* SIMODE1 */
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#define ENSELTIMO 0x80
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#define ENATNTARG 0x40
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#define ENSCSIRST 0x20
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#define ENPHASEMIS 0x10
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#define ENBUSFREE 0x08
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#define ENSCSIPERR 0x04
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#define ENPHASECHG 0x02
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#define ENREQINIT 0x01
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/* DMACNTRL0 */
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#define ENDMA 0x80
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#define B8MODE 0x40
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#define DMA 0x20
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#define DWORDPIO 0x10
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#define WRITE 0x08
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#define INTEN 0x04
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#define RSTFIFO 0x02
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#define SWINT 0x01
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/* DMACNTRL1 */
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#define PWRDWN 0x80
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#define ENSTK32 0x40
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#define STK4 0x10
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#define STK3 0x08
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#define STK2 0x04
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#define STK1 0x02
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#define STK0 0x01
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/* DMASTAT */
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#define ATDONE 0x80
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#define WORDRDY 0x40
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#define INTSTAT 0x20
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#define DFIFOFULL 0x10
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#define DFIFOEMP 0x08
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#define DFIFOHF 0x04
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#define DWORDRDY 0x02
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/* BRSTCNTRL */
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#define BON3 0x80
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#define BON2 0x40
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#define BON1 0x20
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#define BON0 0x10
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#define BOFF3 0x08
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#define BOFF2 0x04
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#define BOFF1 0x02
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#define BOFF0 0x01
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/* TEST */
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#define BOFFTMR 0x40
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#define BONTMR 0x20
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#define STCNTH 0x10
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#define STCNTM 0x08
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#define STCNTL 0x04
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#define SCSIBLK 0x02
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#define DMABLK 0x01
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/* PORTA */
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#define PORTA_ID(a) ((a) & 7)
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#define PORTA_IRQ(a) ((((a) >> 3) & 3) + 9)
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#define PORTA_DRQ(a) ((((a) >> 5) & 3) ? (((a) >> 5) & 3) + 4 : 0)
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#define PORTA_PARITY(a) ((a) & 0x80)
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/* PORTB */
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#define PORTB_EXTTRAN(b)((b) & 1)
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#define PORTB_DISC(b) ((b) & 4)
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#define PORTB_SYNC(b) ((b) & 8)
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#define PORTB_FSYNC(b) ((b) & 0x10)
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#define PORTB_BOOT(b) ((b) & 0x40)
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#define PORTB_DMA(b) ((b) & 0x80)
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/* How to behave on the (E)ISA bus when/if DMAing (on<<4) + off in us */
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#define EISA_BRST_TIM ((15<<4) + 1) /* 15us on, 1us off */
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#define FIFOSIZE 128
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