This updates llvm, clang, compiler-rt, libc++, libunwind, lld, lldb and openmp to llvmorg-15-init-16436-g18a6ab5b8d1f. PR: 265425 MFC after: 2 weeks
537 lines
18 KiB
C++
537 lines
18 KiB
C++
//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// CodeEmitterGen uses the descriptions of instructions and their fields to
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// construct an automated code emitter: a function that, given a MachineInstr,
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// returns the (currently, 32-bit unsigned) value of the instruction.
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//
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//===----------------------------------------------------------------------===//
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#include "CodeGenInstruction.h"
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#include "CodeGenTarget.h"
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#include "SubtargetFeatureInfo.h"
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#include "Types.h"
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#include "VarLenCodeEmitterGen.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/ADT/ArrayRef.h"
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#include "llvm/ADT/StringExtras.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/raw_ostream.h"
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#include "llvm/TableGen/Error.h"
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#include "llvm/TableGen/Record.h"
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#include "llvm/TableGen/TableGenBackend.h"
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#include <cassert>
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#include <cstdint>
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#include <map>
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#include <set>
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#include <string>
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#include <utility>
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#include <vector>
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using namespace llvm;
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namespace {
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class CodeEmitterGen {
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RecordKeeper &Records;
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public:
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CodeEmitterGen(RecordKeeper &R) : Records(R) {}
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void run(raw_ostream &o);
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private:
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int getVariableBit(const std::string &VarName, BitsInit *BI, int bit);
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std::string getInstructionCase(Record *R, CodeGenTarget &Target);
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std::string getInstructionCaseForEncoding(Record *R, Record *EncodingDef,
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CodeGenTarget &Target);
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void AddCodeToMergeInOperand(Record *R, BitsInit *BI,
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const std::string &VarName,
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unsigned &NumberedOp,
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std::set<unsigned> &NamedOpIndices,
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std::string &Case, CodeGenTarget &Target);
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void emitInstructionBaseValues(
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raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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CodeGenTarget &Target, int HwMode = -1);
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unsigned BitWidth;
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bool UseAPInt;
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};
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// If the VarBitInit at position 'bit' matches the specified variable then
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// return the variable bit position. Otherwise return -1.
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int CodeEmitterGen::getVariableBit(const std::string &VarName,
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BitsInit *BI, int bit) {
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if (VarBitInit *VBI = dyn_cast<VarBitInit>(BI->getBit(bit))) {
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if (VarInit *VI = dyn_cast<VarInit>(VBI->getBitVar()))
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if (VI->getName() == VarName)
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return VBI->getBitNum();
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} else if (VarInit *VI = dyn_cast<VarInit>(BI->getBit(bit))) {
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if (VI->getName() == VarName)
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return 0;
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}
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return -1;
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}
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void CodeEmitterGen::
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AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName,
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unsigned &NumberedOp,
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std::set<unsigned> &NamedOpIndices,
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std::string &Case, CodeGenTarget &Target) {
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CodeGenInstruction &CGI = Target.getInstruction(R);
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// Determine if VarName actually contributes to the Inst encoding.
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int bit = BI->getNumBits()-1;
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// Scan for a bit that this contributed to.
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for (; bit >= 0; ) {
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if (getVariableBit(VarName, BI, bit) != -1)
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break;
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--bit;
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}
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// If we found no bits, ignore this value, otherwise emit the call to get the
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// operand encoding.
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if (bit < 0) return;
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// If the operand matches by name, reference according to that
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// operand number. Non-matching operands are assumed to be in
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// order.
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unsigned OpIdx;
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if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) {
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// Get the machine operand number for the indicated operand.
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OpIdx = CGI.Operands[OpIdx].MIOperandNo;
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assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) &&
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"Explicitly used operand also marked as not emitted!");
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} else {
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unsigned NumberOps = CGI.Operands.size();
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/// If this operand is not supposed to be emitted by the
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/// generated emitter, skip it.
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while (NumberedOp < NumberOps &&
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(CGI.Operands.isFlatOperandNotEmitted(NumberedOp) ||
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(!NamedOpIndices.empty() && NamedOpIndices.count(
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CGI.Operands.getSubOperandNumber(NumberedOp).first)))) {
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++NumberedOp;
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}
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if (NumberedOp >=
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CGI.Operands.back().MIOperandNo + CGI.Operands.back().MINumOperands) {
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std::string E;
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raw_string_ostream S(E);
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S << "Too few operands in record " << R->getName()
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<< " (no match for variable " << VarName << "):\n";
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S << *R;
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PrintFatalError(R, E);
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}
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OpIdx = NumberedOp++;
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}
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std::pair<unsigned, unsigned> SO = CGI.Operands.getSubOperandNumber(OpIdx);
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std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName;
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if (UseAPInt)
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Case += " op.clearAllBits();\n";
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// If the source operand has a custom encoder, use it. This will
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// get the encoding for all of the suboperands.
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if (!EncoderMethodName.empty()) {
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// A custom encoder has all of the information for the
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// sub-operands, if there are more than one, so only
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// query the encoder once per source operand.
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if (SO.second == 0) {
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Case += " // op: " + VarName + "\n";
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if (UseAPInt) {
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Case += " " + EncoderMethodName + "(MI, " + utostr(OpIdx);
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Case += ", op";
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} else {
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Case += " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx);
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}
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Case += ", Fixups, STI);\n";
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}
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} else {
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Case += " // op: " + VarName + "\n";
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if (UseAPInt) {
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Case += " getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
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Case += ", op, Fixups, STI";
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} else {
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Case += " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")";
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Case += ", Fixups, STI";
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}
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Case += ");\n";
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}
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// Precalculate the number of lits this variable contributes to in the
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// operand. If there is a single lit (consecutive range of bits) we can use a
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// destructive sequence on APInt that reduces memory allocations.
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int numOperandLits = 0;
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for (int tmpBit = bit; tmpBit >= 0;) {
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int varBit = getVariableBit(VarName, BI, tmpBit);
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// If this bit isn't from a variable, skip it.
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if (varBit == -1) {
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--tmpBit;
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continue;
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}
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// Figure out the consecutive range of bits covered by this operand, in
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// order to generate better encoding code.
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int beginVarBit = varBit;
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int N = 1;
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for (--tmpBit; tmpBit >= 0;) {
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varBit = getVariableBit(VarName, BI, tmpBit);
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if (varBit == -1 || varBit != (beginVarBit - N))
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break;
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++N;
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--tmpBit;
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}
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++numOperandLits;
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}
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for (; bit >= 0; ) {
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int varBit = getVariableBit(VarName, BI, bit);
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// If this bit isn't from a variable, skip it.
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if (varBit == -1) {
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--bit;
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continue;
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}
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// Figure out the consecutive range of bits covered by this operand, in
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// order to generate better encoding code.
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int beginInstBit = bit;
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int beginVarBit = varBit;
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int N = 1;
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for (--bit; bit >= 0;) {
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varBit = getVariableBit(VarName, BI, bit);
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if (varBit == -1 || varBit != (beginVarBit - N)) break;
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++N;
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--bit;
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}
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std::string maskStr;
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int opShift;
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unsigned loBit = beginVarBit - N + 1;
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unsigned hiBit = loBit + N;
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unsigned loInstBit = beginInstBit - N + 1;
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if (UseAPInt) {
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std::string extractStr;
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if (N >= 64) {
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extractStr = "op.extractBits(" + itostr(hiBit - loBit) + ", " +
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itostr(loBit) + ")";
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Case += " Value.insertBits(" + extractStr + ", " +
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itostr(loInstBit) + ");\n";
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} else {
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extractStr = "op.extractBitsAsZExtValue(" + itostr(hiBit - loBit) +
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", " + itostr(loBit) + ")";
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Case += " Value.insertBits(" + extractStr + ", " +
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itostr(loInstBit) + ", " + itostr(hiBit - loBit) + ");\n";
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}
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} else {
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uint64_t opMask = ~(uint64_t)0 >> (64 - N);
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opShift = beginVarBit - N + 1;
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opMask <<= opShift;
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maskStr = "UINT64_C(" + utostr(opMask) + ")";
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opShift = beginInstBit - beginVarBit;
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if (numOperandLits == 1) {
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Case += " op &= " + maskStr + ";\n";
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if (opShift > 0) {
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Case += " op <<= " + itostr(opShift) + ";\n";
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} else if (opShift < 0) {
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Case += " op >>= " + itostr(-opShift) + ";\n";
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}
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Case += " Value |= op;\n";
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} else {
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if (opShift > 0) {
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Case += " Value |= (op & " + maskStr + ") << " +
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itostr(opShift) + ";\n";
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} else if (opShift < 0) {
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Case += " Value |= (op & " + maskStr + ") >> " +
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itostr(-opShift) + ";\n";
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} else {
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Case += " Value |= (op & " + maskStr + ");\n";
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}
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}
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}
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}
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}
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std::string CodeEmitterGen::getInstructionCase(Record *R,
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CodeGenTarget &Target) {
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std::string Case;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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const CodeGenHwModes &HWM = Target.getHwModes();
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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Case += " switch (HwMode) {\n";
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Case += " default: llvm_unreachable(\"Unhandled HwMode\");\n";
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for (auto &KV : EBM) {
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Case += " case " + itostr(KV.first) + ": {\n";
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Case += getInstructionCaseForEncoding(R, KV.second, Target);
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Case += " break;\n";
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Case += " }\n";
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}
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Case += " }\n";
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return Case;
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}
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}
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return getInstructionCaseForEncoding(R, R, Target);
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}
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std::string CodeEmitterGen::getInstructionCaseForEncoding(Record *R, Record *EncodingDef,
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CodeGenTarget &Target) {
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std::string Case;
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BitsInit *BI = EncodingDef->getValueAsBitsInit("Inst");
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unsigned NumberedOp = 0;
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std::set<unsigned> NamedOpIndices;
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// Collect the set of operand indices that might correspond to named
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// operand, and skip these when assigning operands based on position.
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if (Target.getInstructionSet()->
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getValueAsBit("noNamedPositionallyEncodedOperands")) {
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CodeGenInstruction &CGI = Target.getInstruction(R);
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for (const RecordVal &RV : R->getValues()) {
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unsigned OpIdx;
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if (!CGI.Operands.hasOperandNamed(RV.getName(), OpIdx))
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continue;
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NamedOpIndices.insert(OpIdx);
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}
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}
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// Loop over all of the fields in the instruction, determining which are the
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// operands to the instruction.
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for (const RecordVal &RV : EncodingDef->getValues()) {
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// Ignore fixed fields in the record, we're looking for values like:
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// bits<5> RST = { ?, ?, ?, ?, ? };
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if (RV.isNonconcreteOK() || RV.getValue()->isComplete())
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continue;
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AddCodeToMergeInOperand(R, BI, std::string(RV.getName()), NumberedOp,
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NamedOpIndices, Case, Target);
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}
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StringRef PostEmitter = R->getValueAsString("PostEncoderMethod");
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if (!PostEmitter.empty()) {
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Case += " Value = ";
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Case += PostEmitter;
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Case += "(MI, Value";
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Case += ", STI";
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Case += ");\n";
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}
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return Case;
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}
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static void emitInstBits(raw_ostream &OS, const APInt &Bits) {
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for (unsigned I = 0; I < Bits.getNumWords(); ++I)
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OS << ((I > 0) ? ", " : "") << "UINT64_C(" << utostr(Bits.getRawData()[I])
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<< ")";
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}
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void CodeEmitterGen::emitInstructionBaseValues(
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raw_ostream &o, ArrayRef<const CodeGenInstruction *> NumberedInstructions,
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CodeGenTarget &Target, int HwMode) {
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const CodeGenHwModes &HWM = Target.getHwModes();
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if (HwMode == -1)
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o << " static const uint64_t InstBits[] = {\n";
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else
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o << " static const uint64_t InstBits_" << HWM.getMode(HwMode).Name
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<< "[] = {\n";
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo")) {
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o << " "; emitInstBits(o, APInt(BitWidth, 0)); o << ",\n";
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continue;
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}
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Record *EncodingDef = R;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (auto *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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if (EBM.hasMode(HwMode))
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EncodingDef = EBM.get(HwMode);
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}
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}
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BitsInit *BI = EncodingDef->getValueAsBitsInit("Inst");
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// Start by filling in fixed values.
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APInt Value(BitWidth, 0);
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for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) {
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if (BitInit *B = dyn_cast<BitInit>(BI->getBit(e - i - 1)))
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Value |= APInt(BitWidth, (uint64_t)B->getValue()) << (e - i - 1);
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}
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o << " ";
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emitInstBits(o, Value);
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o << "," << '\t' << "// " << R->getName() << "\n";
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}
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o << " UINT64_C(0)\n };\n";
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}
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void CodeEmitterGen::run(raw_ostream &o) {
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CodeGenTarget Target(Records);
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std::vector<Record*> Insts = Records.getAllDerivedDefinitions("Instruction");
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// For little-endian instruction bit encodings, reverse the bit order
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Target.reverseBitsForLittleEndianEncoding();
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ArrayRef<const CodeGenInstruction*> NumberedInstructions =
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Target.getInstructionsByEnumValue();
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if (any_of(NumberedInstructions, [](const CodeGenInstruction *CGI) {
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Record *R = CGI->TheDef;
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return R->getValue("Inst") && isa<DagInit>(R->getValueInit("Inst"));
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})) {
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emitVarLenCodeEmitter(Records, o);
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} else {
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const CodeGenHwModes &HWM = Target.getHwModes();
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// The set of HwModes used by instruction encodings.
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std::set<unsigned> HwModes;
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BitWidth = 0;
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for (const CodeGenInstruction *CGI : NumberedInstructions) {
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Record *R = CGI->TheDef;
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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if (const RecordVal *RV = R->getValue("EncodingInfos")) {
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if (DefInit *DI = dyn_cast_or_null<DefInit>(RV->getValue())) {
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EncodingInfoByHwMode EBM(DI->getDef(), HWM);
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for (auto &KV : EBM) {
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BitsInit *BI = KV.second->getValueAsBitsInit("Inst");
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BitWidth = std::max(BitWidth, BI->getNumBits());
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HwModes.insert(KV.first);
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}
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continue;
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}
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}
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BitsInit *BI = R->getValueAsBitsInit("Inst");
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BitWidth = std::max(BitWidth, BI->getNumBits());
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}
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UseAPInt = BitWidth > 64;
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// Emit function declaration
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if (UseAPInt) {
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o << "void " << Target.getName()
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<< "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
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<< " SmallVectorImpl<MCFixup> &Fixups,\n"
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<< " APInt &Inst,\n"
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<< " APInt &Scratch,\n"
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<< " const MCSubtargetInfo &STI) const {\n";
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} else {
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o << "uint64_t " << Target.getName();
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o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n"
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<< " SmallVectorImpl<MCFixup> &Fixups,\n"
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<< " const MCSubtargetInfo &STI) const {\n";
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}
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// Emit instruction base values
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if (HwModes.empty()) {
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emitInstructionBaseValues(o, NumberedInstructions, Target, -1);
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} else {
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for (unsigned HwMode : HwModes)
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emitInstructionBaseValues(o, NumberedInstructions, Target, (int)HwMode);
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}
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if (!HwModes.empty()) {
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o << " const uint64_t *InstBits;\n";
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o << " unsigned HwMode = STI.getHwMode();\n";
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o << " switch (HwMode) {\n";
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o << " default: llvm_unreachable(\"Unknown hardware mode!\"); break;\n";
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for (unsigned I : HwModes) {
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o << " case " << I << ": InstBits = InstBits_" << HWM.getMode(I).Name
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<< "; break;\n";
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}
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o << " };\n";
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}
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// Map to accumulate all the cases.
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std::map<std::string, std::vector<std::string>> CaseMap;
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// Construct all cases statement for each opcode
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for (Record *R : Insts) {
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if (R->getValueAsString("Namespace") == "TargetOpcode" ||
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R->getValueAsBit("isPseudo"))
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continue;
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std::string InstName =
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(R->getValueAsString("Namespace") + "::" + R->getName()).str();
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std::string Case = getInstructionCase(R, Target);
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CaseMap[Case].push_back(std::move(InstName));
|
|
}
|
|
|
|
// Emit initial function code
|
|
if (UseAPInt) {
|
|
int NumWords = APInt::getNumWords(BitWidth);
|
|
o << " const unsigned opcode = MI.getOpcode();\n"
|
|
<< " if (Scratch.getBitWidth() != " << BitWidth << ")\n"
|
|
<< " Scratch = Scratch.zext(" << BitWidth << ");\n"
|
|
<< " Inst = APInt(" << BitWidth
|
|
<< ", makeArrayRef(InstBits + opcode * " << NumWords << ", " << NumWords
|
|
<< "));\n"
|
|
<< " APInt &Value = Inst;\n"
|
|
<< " APInt &op = Scratch;\n"
|
|
<< " switch (opcode) {\n";
|
|
} else {
|
|
o << " const unsigned opcode = MI.getOpcode();\n"
|
|
<< " uint64_t Value = InstBits[opcode];\n"
|
|
<< " uint64_t op = 0;\n"
|
|
<< " (void)op; // suppress warning\n"
|
|
<< " switch (opcode) {\n";
|
|
}
|
|
|
|
// Emit each case statement
|
|
std::map<std::string, std::vector<std::string>>::iterator IE, EE;
|
|
for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) {
|
|
const std::string &Case = IE->first;
|
|
std::vector<std::string> &InstList = IE->second;
|
|
|
|
for (int i = 0, N = InstList.size(); i < N; i++) {
|
|
if (i)
|
|
o << "\n";
|
|
o << " case " << InstList[i] << ":";
|
|
}
|
|
o << " {\n";
|
|
o << Case;
|
|
o << " break;\n"
|
|
<< " }\n";
|
|
}
|
|
|
|
// Default case: unhandled opcode
|
|
o << " default:\n"
|
|
<< " std::string msg;\n"
|
|
<< " raw_string_ostream Msg(msg);\n"
|
|
<< " Msg << \"Not supported instr: \" << MI;\n"
|
|
<< " report_fatal_error(Msg.str().c_str());\n"
|
|
<< " }\n";
|
|
if (UseAPInt)
|
|
o << " Inst = Value;\n";
|
|
else
|
|
o << " return Value;\n";
|
|
o << "}\n\n";
|
|
}
|
|
}
|
|
|
|
} // end anonymous namespace
|
|
|
|
namespace llvm {
|
|
|
|
void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) {
|
|
emitSourceFileHeader("Machine Code Emitter", OS);
|
|
CodeEmitterGen(RK).run(OS);
|
|
}
|
|
|
|
} // end namespace llvm
|