483 lines
12 KiB
C
483 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2018, 2019 Rubicon Communications, LLC (Netgate)
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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/*
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* Driver for Armada 37x0 i2c controller.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/bus.h>
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#include <machine/resource.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/mv/a37x0_iicreg.h>
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#include "iicbus_if.h"
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struct a37x0_iic_softc {
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boolean_t sc_fast_mode;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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device_t sc_dev;
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device_t sc_iicbus;
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struct mtx sc_mtx;
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struct resource *sc_mem_res;
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struct resource *sc_irq_res;
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void *sc_intrhand;
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};
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#define A37X0_IIC_WRITE(_sc, _off, _val) \
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bus_space_write_4((_sc)->sc_bst, (_sc)->sc_bsh, _off, _val)
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#define A37X0_IIC_READ(_sc, _off) \
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bus_space_read_4((_sc)->sc_bst, (_sc)->sc_bsh, _off)
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#define A37X0_IIC_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define A37X0_IIC_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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static struct ofw_compat_data compat_data[] = {
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{ "marvell,armada-3700-i2c", 1 },
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{ NULL, 0 }
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};
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#undef A37x0_IIC_DEBUG
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static void a37x0_iic_intr(void *);
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static int a37x0_iic_detach(device_t);
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static void
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a37x0_iic_rmw(struct a37x0_iic_softc *sc, uint32_t off, uint32_t mask,
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uint32_t value)
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{
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uint32_t reg;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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reg = A37X0_IIC_READ(sc, off);
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reg &= ~mask;
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reg |= value;
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A37X0_IIC_WRITE(sc, off, reg);
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}
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static int
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a37x0_iic_wait_clear(struct a37x0_iic_softc *sc, uint32_t mask)
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{
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int timeout;
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uint32_t status;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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timeout = 1000;
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do {
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DELAY(10);
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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if (--timeout == 0)
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return (0);
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} while ((status & mask) != 0);
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return (1);
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}
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static int
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a37x0_iic_wait_set(struct a37x0_iic_softc *sc, uint32_t mask)
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{
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int timeout;
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uint32_t status;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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timeout = 1000;
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do {
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DELAY(10);
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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if (--timeout == 0)
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return (0);
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} while ((status & mask) != mask);
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return (1);
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}
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#ifdef A37x0_IIC_DEBUG
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static void
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a37x0_iic_regdump(struct a37x0_iic_softc *sc)
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{
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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printf("%s: IBMR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_IBMR));
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printf("%s: ICR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ICR));
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printf("%s: ISR: %#x\n", __func__, A37X0_IIC_READ(sc, A37X0_IIC_ISR));
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}
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#endif
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static void
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a37x0_iic_reset(struct a37x0_iic_softc *sc)
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{
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uint32_t mode, reg;
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mtx_assert(&sc->sc_mtx, MA_OWNED);
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/* Disable the controller. */
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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mode = reg & ICR_MODE_MASK;
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_UR);
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DELAY(100);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg & ~ICR_IUE);
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/* Enable the controller. */
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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reg |= mode | ICR_IUE | ICR_GCD | ICR_SCLE;
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
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#ifdef A37x0_IIC_DEBUG
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a37x0_iic_regdump(sc);
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#endif
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}
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static int
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a37x0_iic_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Marvell Armada 37x0 IIC controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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a37x0_iic_attach(device_t dev)
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{
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int rid;
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phandle_t node;
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struct a37x0_iic_softc *sc;
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sc = device_get_softc(dev);
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sc->sc_dev = dev;
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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return (ENXIO);
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (!sc->sc_irq_res) {
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot allocate interrupt\n");
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return (ENXIO);
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}
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/* Hook up our interrupt handler. */
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
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NULL, a37x0_iic_intr, sc, &sc->sc_intrhand)) {
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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device_printf(dev, "cannot setup the interrupt handler\n");
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return (ENXIO);
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}
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mtx_init(&sc->sc_mtx, "a37x0_iic", NULL, MTX_DEF);
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node = ofw_bus_get_node(dev);
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if (OF_hasprop(node, "mrvl,i2c-fast-mode"))
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sc->sc_fast_mode = true;
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/* Enable the controller. */
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A37X0_IIC_LOCK(sc);
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a37x0_iic_reset(sc);
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A37X0_IIC_UNLOCK(sc);
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sc->sc_iicbus = device_add_child(dev, "iicbus", -1);
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if (sc->sc_iicbus == NULL) {
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a37x0_iic_detach(dev);
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return (ENXIO);
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}
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/* Probe and attach the iicbus. */
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return (bus_generic_attach(dev));
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}
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static int
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a37x0_iic_detach(device_t dev)
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{
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struct a37x0_iic_softc *sc;
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bus_generic_detach(dev);
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sc = device_get_softc(dev);
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if (sc->sc_iicbus != NULL)
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device_delete_child(dev, sc->sc_iicbus);
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mtx_destroy(&sc->sc_mtx);
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (0);
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}
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static void
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a37x0_iic_intr(void *arg)
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{
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struct a37x0_iic_softc *sc;
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uint32_t status;
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/* Not used, the interrupts are not enabled. */
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sc = (struct a37x0_iic_softc *)arg;
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A37X0_IIC_LOCK(sc);
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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#ifdef A37x0_IIC_DEBUG
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a37x0_iic_regdump(sc);
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#endif
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/* Clear pending interrrupts. */
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A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status);
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A37X0_IIC_UNLOCK(sc);
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}
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static int
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a37x0_iic_stop(device_t dev)
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{
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struct a37x0_iic_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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A37X0_IIC_LOCK(sc);
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/* Clear the STOP condition. */
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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if (reg & (ICR_ACKNAK | ICR_STOP)) {
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reg &= ~(ICR_START | ICR_ACKNAK | ICR_STOP);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg);
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}
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/* Clear interrupts. */
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, reg);
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A37X0_IIC_UNLOCK(sc);
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return (IIC_NOERR);
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}
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static int
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a37x0_iic_start(device_t dev, u_char slave, int timeout)
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{
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int rv;
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struct a37x0_iic_softc *sc;
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uint32_t reg, status;
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sc = device_get_softc(dev);
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A37X0_IIC_LOCK(sc);
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/* Wait for the bus to be free before start a transaction. */
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if (a37x0_iic_wait_clear(sc, ISR_IBB) == 0) {
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A37X0_IIC_UNLOCK(sc);
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return (IIC_ETIMEOUT);
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}
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/* Write the slave address. */
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A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, slave);
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/* Send Start condition (with slave address). */
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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reg &= ~(ICR_STOP | ICR_ACKNAK);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_START | ICR_TB);
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rv = IIC_NOERR;
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if (a37x0_iic_wait_set(sc, ISR_ITE) == 0)
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rv = IIC_ETIMEOUT;
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if (rv == IIC_NOERR) {
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
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if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0)
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rv = IIC_ENOACK;
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}
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A37X0_IIC_UNLOCK(sc);
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if (rv != IIC_NOERR)
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a37x0_iic_stop(dev);
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return (rv);
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}
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static int
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a37x0_iic_bus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
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{
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struct a37x0_iic_softc *sc;
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uint32_t busfreq;
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sc = device_get_softc(dev);
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A37X0_IIC_LOCK(sc);
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a37x0_iic_reset(sc);
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if (sc->sc_iicbus == NULL)
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busfreq = 100000;
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else
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busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
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a37x0_iic_rmw(sc, A37X0_IIC_ICR, ICR_MODE_MASK,
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(busfreq > 100000) ? ICR_FAST_MODE : 0);
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A37X0_IIC_UNLOCK(sc);
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return (IIC_ENOADDR);
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}
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static int
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a37x0_iic_read(device_t dev, char *buf, int len, int *read, int last, int delay)
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{
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int rv;
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struct a37x0_iic_softc *sc;
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uint32_t reg, status;
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sc = device_get_softc(dev);
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A37X0_IIC_LOCK(sc);
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
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A37X0_IIC_UNLOCK(sc);
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return (IIC_EBUSERR);
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}
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*read = 0;
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rv = IIC_NOERR;
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while (*read < len) {
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
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if (*read == len - 1)
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reg |= ICR_ACKNAK | ICR_STOP;
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
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if (a37x0_iic_wait_set(sc, ISR_IRF) == 0) {
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rv = IIC_ETIMEOUT;
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break;
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}
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*buf++ = A37X0_IIC_READ(sc, A37X0_IIC_IDBR);
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(*read)++;
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_IRF);
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}
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A37X0_IIC_UNLOCK(sc);
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return (rv);
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}
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static int
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a37x0_iic_write(device_t dev, const char *buf, int len, int *sent, int timeout)
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{
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int rv;
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struct a37x0_iic_softc *sc;
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uint32_t reg, status;
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sc = device_get_softc(dev);
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A37X0_IIC_LOCK(sc);
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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if ((reg & (ISR_UB | ISR_IBB)) != ISR_UB) {
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A37X0_IIC_UNLOCK(sc);
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return (IIC_EBUSERR);
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}
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rv = IIC_NOERR;
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*sent = 0;
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while (*sent < len) {
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A37X0_IIC_WRITE(sc, A37X0_IIC_IDBR, *buf++);
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reg = A37X0_IIC_READ(sc, A37X0_IIC_ICR);
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reg &= ~(ICR_START | ICR_STOP | ICR_ACKNAK);
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if (*sent == len - 1)
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reg |= ICR_STOP;
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A37X0_IIC_WRITE(sc, A37X0_IIC_ICR, reg | ICR_TB);
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if (a37x0_iic_wait_set(sc, ISR_ITE) == 0) {
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rv = IIC_ETIMEOUT;
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break;
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}
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(*sent)++;
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status = A37X0_IIC_READ(sc, A37X0_IIC_ISR);
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A37X0_IIC_WRITE(sc, A37X0_IIC_ISR, status | ISR_ITE);
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if (a37x0_iic_wait_clear(sc, ISR_ACKNAK) == 0) {
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rv = IIC_ENOACK;
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break;
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}
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}
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A37X0_IIC_UNLOCK(sc);
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return (rv);
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}
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static phandle_t
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a37x0_iic_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_method_t a37x0_iic_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, a37x0_iic_probe),
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DEVMETHOD(device_attach, a37x0_iic_attach),
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DEVMETHOD(device_detach, a37x0_iic_detach),
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/* iicbus interface */
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DEVMETHOD(iicbus_reset, a37x0_iic_bus_reset),
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DEVMETHOD(iicbus_callback, iicbus_null_callback),
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DEVMETHOD(iicbus_transfer, iicbus_transfer_gen),
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|
DEVMETHOD(iicbus_repeated_start, a37x0_iic_start),
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|
DEVMETHOD(iicbus_start, a37x0_iic_start),
|
|
DEVMETHOD(iicbus_stop, a37x0_iic_stop),
|
|
DEVMETHOD(iicbus_read, a37x0_iic_read),
|
|
DEVMETHOD(iicbus_write, a37x0_iic_write),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, a37x0_iic_get_node),
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|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t a37x0_iic_driver = {
|
|
"iichb",
|
|
a37x0_iic_methods,
|
|
sizeof(struct a37x0_iic_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(iicbus, a37x0_iic, iicbus_driver, 0, 0);
|
|
DRIVER_MODULE(a37x0_iic, simplebus, a37x0_iic_driver, 0, 0);
|