379 lines
9.4 KiB
C
379 lines
9.4 KiB
C
/*-
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* Copyright (c) 2006 Benno Rice.
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* Copyright (C) 2007-2008 MARVELL INTERNATIONAL LTD.
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* All rights reserved.
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*
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* Adapted to Marvell SoC by Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_timer.c, rev 1
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/eventhandler.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/malloc.h>
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#include <sys/rman.h>
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#include <sys/kdb.h>
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#include <sys/timeet.h>
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#include <sys/timetc.h>
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#include <sys/watchdog.h>
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#include <machine/bus.h>
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#include <machine/cpu.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#define INITIAL_TIMECOUNTER (0xffffffff)
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#define MAX_WATCHDOG_TICKS (0xffffffff)
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#define WD_RST_OUT_EN 0x00000002
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#define MV_CLOCK_SRC_ARMV7 25000000 /* Timers' 25MHz mode */
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struct mv_wdt_config {
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enum soc_family wdt_soc;
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uint32_t wdt_timer;
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void (*wdt_enable)(void);
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void (*wdt_disable)(void);
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unsigned int wdt_clock_src;
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};
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static void mv_wdt_enable_armv5(void);
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static void mv_wdt_enable_armada_38x(void);
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static void mv_wdt_enable_armada_xp(void);
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static inline void mv_wdt_enable_armada_38x_xp_helper(void);
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static void mv_wdt_disable_armv5(void);
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static void mv_wdt_disable_armada_38x(void);
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static void mv_wdt_disable_armada_xp(void);
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static struct mv_wdt_config mv_wdt_armada_38x_config = {
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.wdt_soc = MV_SOC_ARMADA_38X,
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.wdt_timer = 4,
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.wdt_enable = &mv_wdt_enable_armada_38x,
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.wdt_disable = &mv_wdt_disable_armada_38x,
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.wdt_clock_src = MV_CLOCK_SRC_ARMV7,
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};
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static struct mv_wdt_config mv_wdt_armada_xp_config = {
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.wdt_soc = MV_SOC_ARMADA_XP,
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.wdt_timer = 2,
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.wdt_enable = &mv_wdt_enable_armada_xp,
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.wdt_disable = &mv_wdt_disable_armada_xp,
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.wdt_clock_src = MV_CLOCK_SRC_ARMV7,
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};
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static struct mv_wdt_config mv_wdt_armv5_config = {
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.wdt_soc = MV_SOC_ARMV5,
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.wdt_timer = 2,
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.wdt_enable = &mv_wdt_enable_armv5,
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.wdt_disable = &mv_wdt_disable_armv5,
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.wdt_clock_src = 0,
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};
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struct mv_wdt_softc {
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struct resource * wdt_res;
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struct mtx wdt_mtx;
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struct mv_wdt_config * wdt_config;
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};
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static struct resource_spec mv_wdt_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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static struct ofw_compat_data mv_wdt_compat[] = {
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{"marvell,armada-380-wdt", (uintptr_t)&mv_wdt_armada_38x_config},
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{"marvell,armada-xp-wdt", (uintptr_t)&mv_wdt_armada_xp_config},
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{"marvell,orion-wdt", (uintptr_t)&mv_wdt_armv5_config},
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{NULL, (uintptr_t)NULL}
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};
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static struct mv_wdt_softc *wdt_softc = NULL;
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int timers_initialized = 0;
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static int mv_wdt_probe(device_t);
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static int mv_wdt_attach(device_t);
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static uint32_t mv_get_timer_control(void);
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static void mv_set_timer_control(uint32_t);
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static void mv_set_timer(uint32_t, uint32_t);
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static void mv_watchdog_event(void *, unsigned int, int *);
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static device_method_t mv_wdt_methods[] = {
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DEVMETHOD(device_probe, mv_wdt_probe),
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DEVMETHOD(device_attach, mv_wdt_attach),
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{ 0, 0 }
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};
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static driver_t mv_wdt_driver = {
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"wdt",
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mv_wdt_methods,
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sizeof(struct mv_wdt_softc),
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};
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DRIVER_MODULE(wdt, simplebus, mv_wdt_driver, 0, 0);
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static int
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mv_wdt_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Marvell Watchdog Timer");
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return (0);
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}
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static int
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mv_wdt_attach(device_t dev)
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{
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struct mv_wdt_softc *sc;
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int error;
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if (wdt_softc != NULL)
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return (ENXIO);
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sc = device_get_softc(dev);
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wdt_softc = sc;
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error = bus_alloc_resources(dev, mv_wdt_spec, &sc->wdt_res);
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if (error) {
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device_printf(dev, "could not allocate resources\n");
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return (ENXIO);
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}
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mtx_init(&sc->wdt_mtx, "watchdog", NULL, MTX_DEF);
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sc->wdt_config = (struct mv_wdt_config *)
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ofw_bus_search_compatible(dev, mv_wdt_compat)->ocd_data;
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if (sc->wdt_config->wdt_clock_src == 0)
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sc->wdt_config->wdt_clock_src = get_tclk();
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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EVENTHANDLER_REGISTER(watchdog_list, mv_watchdog_event, sc, 0);
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return (0);
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}
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static __inline uint32_t
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mv_get_timer_control(void)
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{
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return (bus_read_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL));
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}
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static __inline void
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mv_set_timer_control(uint32_t val)
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{
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bus_write_4(wdt_softc->wdt_res, CPU_TIMER_CONTROL, val);
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}
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static __inline void
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mv_set_timer(uint32_t timer, uint32_t val)
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{
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bus_write_4(wdt_softc->wdt_res, CPU_TIMER0 + timer * 0x8, val);
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}
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static void
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mv_wdt_enable_armv5(void)
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{
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uint32_t val, irq_cause, irq_mask;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask |= IRQ_TIMER_WD_MASK;
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val |= WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO;
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mv_set_timer_control(val);
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}
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static inline void
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mv_wdt_enable_armada_38x_xp_helper(void)
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{
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uint32_t val, irq_cause;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val |= (WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val &= ~RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK_ARMV7, val);
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}
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static void
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mv_wdt_enable_armada_38x(void)
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{
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uint32_t val, irq_cause;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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mv_wdt_enable_armada_38x_xp_helper();
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val = mv_get_timer_control();
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val |= CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO | CPU_TIMER_WD_25MHZ_EN;
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mv_set_timer_control(val);
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}
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static void
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mv_wdt_enable_armada_xp(void)
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{
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uint32_t val, irq_cause;
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP);
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irq_cause &= IRQ_TIMER_WD_CLR_ARMADAXP;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE_ARMADAXP, irq_cause);
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mv_wdt_enable_armada_38x_xp_helper();
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val = mv_get_timer_control();
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val |= CPU_TIMER2_EN | CPU_TIMER2_AUTO | CPU_TIMER_WD_25MHZ_EN;
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mv_set_timer_control(val);
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}
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static void
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mv_wdt_disable_armv5(void)
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{
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uint32_t val, irq_cause, irq_mask;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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val = read_cpu_ctrl(RSTOUTn_MASK);
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val &= ~WD_RST_OUT_EN;
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write_cpu_ctrl(RSTOUTn_MASK, val);
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irq_mask = read_cpu_ctrl(BRIDGE_IRQ_MASK);
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irq_mask &= ~(IRQ_TIMER_WD_MASK);
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write_cpu_ctrl(BRIDGE_IRQ_MASK, irq_mask);
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irq_cause = read_cpu_ctrl(BRIDGE_IRQ_CAUSE);
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irq_cause &= IRQ_TIMER_WD_CLR;
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write_cpu_ctrl(BRIDGE_IRQ_CAUSE, irq_cause);
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}
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static __inline void
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mv_wdt_disable_armada_38x_xp_helper(void)
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{
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uint32_t val;
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val = read_cpu_mp_clocks(WD_RSTOUTn_MASK);
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val &= ~(WD_GLOBAL_MASK | WD_CPU0_MASK);
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write_cpu_mp_clocks(WD_RSTOUTn_MASK, val);
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val = read_cpu_misc(RSTOUTn_MASK_ARMV7);
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val |= RSTOUTn_MASK_WD;
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write_cpu_misc(RSTOUTn_MASK_ARMV7, RSTOUTn_MASK_WD);
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}
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static void
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mv_wdt_disable_armada_38x(void)
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{
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uint32_t val;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER_WD_EN | CPU_TIMER_WD_AUTO);
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mv_set_timer_control(val);
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mv_wdt_disable_armada_38x_xp_helper();
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}
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static void
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mv_wdt_disable_armada_xp(void)
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{
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uint32_t val;
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val = mv_get_timer_control();
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val &= ~(CPU_TIMER2_EN | CPU_TIMER2_AUTO);
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mv_set_timer_control(val);
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mv_wdt_disable_armada_38x_xp_helper();
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}
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/*
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* Watchdog event handler.
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*/
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static void
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mv_watchdog_event(void *arg, unsigned int cmd, int *error)
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{
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struct mv_wdt_softc *sc;
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uint64_t ns;
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uint64_t ticks;
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sc = arg;
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mtx_lock(&sc->wdt_mtx);
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if (cmd == 0) {
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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} else {
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/*
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* Watchdog timeout is in nanosecs, calculation according to
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* watchdog(9)
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*/
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ns = (uint64_t)1 << (cmd & WD_INTERVAL);
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ticks = (uint64_t)(ns * sc->wdt_config->wdt_clock_src) / 1000000000;
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if (ticks > MAX_WATCHDOG_TICKS) {
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if (wdt_softc->wdt_config->wdt_disable != NULL)
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wdt_softc->wdt_config->wdt_disable();
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}
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else {
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mv_set_timer(wdt_softc->wdt_config->wdt_timer, ticks);
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if (wdt_softc->wdt_config->wdt_enable != NULL)
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wdt_softc->wdt_config->wdt_enable();
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*error = 0;
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}
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}
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mtx_unlock(&sc->wdt_mtx);
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}
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