In GENERIC kernel choosing proper get_tclk and get_cpu_freq implementation must be done in runtime. Kernel for both SoC need to have implementation of each other functions, so common file list mv/files.arm7 is added. Marvell armv5 SoC have their own non-generic implementation of those function. Submitted by: Rafal Kozik <rk@semihalf.com> Obtained from: Semihalf Sponsored by: Stormshield Differential Revision: https://reviews.freebsd.org/D14739
227 lines
6.2 KiB
C
227 lines
6.2 KiB
C
/*-
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* Copyright (c) 2015 Semihalf.
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* Copyright (c) 2015 Stormshield.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/fdt.h>
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#include <arm/mv/mvwin.h>
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#include <arm/mv/mvreg.h>
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#include <arm/mv/mvvar.h>
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int armada38x_open_bootrom_win(void);
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int armada38x_scu_enable(void);
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int armada38x_win_set_iosync_barrier(void);
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int armada38x_mbus_optimization(void);
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static uint64_t get_sar_value_armada38x(void);
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static int hw_clockrate;
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SYSCTL_INT(_hw, OID_AUTO, clockrate, CTLFLAG_RD,
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&hw_clockrate, 0, "CPU instruction clock rate");
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static uint64_t
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get_sar_value_armada38x(void)
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{
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uint32_t sar_low, sar_high;
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sar_high = 0;
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sar_low = bus_space_read_4(fdtbus_bs_tag, MV_MISC_BASE,
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SAMPLE_AT_RESET_ARMADA38X);
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return (((uint64_t)sar_high << 32) | sar_low);
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}
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uint32_t
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get_tclk_armada38x(void)
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{
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uint32_t sar;
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/*
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* On Armada38x TCLK can be configured to 250 MHz or 200 MHz.
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* Current setting is read from Sample At Reset register.
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*/
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sar = (uint32_t)get_sar_value_armada38x();
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sar = (sar & TCLK_MASK_ARMADA38X) >> TCLK_SHIFT_ARMADA38X;
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if (sar == 0)
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return (TCLK_250MHZ);
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else
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return (TCLK_200MHZ);
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}
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uint32_t
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get_cpu_freq_armada38x(void)
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{
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uint32_t sar;
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static const uint32_t cpu_frequencies[] = {
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0, 0, 0, 0,
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1066, 0, 0, 0,
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1332, 0, 0, 0,
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1600, 0, 0, 0,
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1866, 0, 0, 2000
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};
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sar = (uint32_t)get_sar_value_armada38x();
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sar = (sar & A38X_CPU_DDR_CLK_MASK) >> A38X_CPU_DDR_CLK_SHIFT;
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if (sar >= nitems(cpu_frequencies))
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return (0);
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hw_clockrate = cpu_frequencies[sar];
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return (hw_clockrate * 1000 * 1000);
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}
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int
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armada38x_win_set_iosync_barrier(void)
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{
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bus_space_handle_t vaddr_iowind;
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int rv;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
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MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
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if (rv != 0)
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return (rv);
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/* Set Sync Barrier flags for all Mbus internal units */
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, MV_SYNC_BARRIER_CTRL,
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MV_SYNC_BARRIER_CTRL_ALL);
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bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0,
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MV_CPU_SUBSYS_REGS_LEN, BUS_SPACE_BARRIER_WRITE);
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bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
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return (rv);
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}
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int
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armada38x_open_bootrom_win(void)
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{
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bus_space_handle_t vaddr_iowind;
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uint32_t val;
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int rv;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_BRIDGE_BASE,
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MV_CPU_SUBSYS_REGS_LEN, 0, &vaddr_iowind);
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if (rv != 0)
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return (rv);
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val = (MV_BOOTROM_WIN_SIZE & IO_WIN_SIZE_MASK) << IO_WIN_SIZE_SHIFT;
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val |= (MBUS_BOOTROM_ATTR & IO_WIN_ATTR_MASK) << IO_WIN_ATTR_SHIFT;
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val |= (MBUS_BOOTROM_TGT_ID & IO_WIN_TGT_MASK) << IO_WIN_TGT_SHIFT;
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/* Enable window and Sync Barrier */
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val |= (0x1 & IO_WIN_SYNC_MASK) << IO_WIN_SYNC_SHIFT;
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val |= (0x1 & IO_WIN_ENA_MASK) << IO_WIN_ENA_SHIFT;
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/* Configure IO Window Control Register */
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_CTRL_OFFSET,
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val);
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/* Configure IO Window Base Register */
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, IO_WIN_9_BASE_OFFSET,
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MV_BOOTROM_MEM_ADDR);
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bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_CPU_SUBSYS_REGS_LEN,
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BUS_SPACE_BARRIER_WRITE);
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bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_CPU_SUBSYS_REGS_LEN);
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return (rv);
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}
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int
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armada38x_mbus_optimization(void)
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{
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bus_space_handle_t vaddr_iowind;
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int rv;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_MBUS_CTRL_BASE,
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MV_MBUS_CTRL_REGS_LEN, 0, &vaddr_iowind);
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if (rv != 0)
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return (rv);
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/*
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* MBUS Units Priority Control Register - Prioritize XOR,
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* PCIe and GbEs (ID=4,6,3,7,8) DRAM access
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* GbE is High and others are Medium.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0, 0x19180);
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/*
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* Fabric Units Priority Control Register -
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* Prioritize CPUs requests.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x4, 0x3000A);
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/*
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* MBUS Units Prefetch Control Register -
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* Pre-fetch enable for all IO masters.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0x8, 0xFFFF);
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/*
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* Fabric Units Prefetch Control Register -
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* Enable the CPUs Instruction and Data prefetch.
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*/
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bus_space_write_4(fdtbus_bs_tag, vaddr_iowind, 0xc, 0x303);
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bus_space_barrier(fdtbus_bs_tag, vaddr_iowind, 0, MV_MBUS_CTRL_REGS_LEN,
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BUS_SPACE_BARRIER_WRITE);
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bus_space_unmap(fdtbus_bs_tag, vaddr_iowind, MV_MBUS_CTRL_REGS_LEN);
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return (rv);
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}
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int
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armada38x_scu_enable(void)
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{
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bus_space_handle_t vaddr_scu;
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int rv;
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uint32_t val;
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rv = bus_space_map(fdtbus_bs_tag, (bus_addr_t)MV_SCU_BASE,
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MV_SCU_REGS_LEN, 0, &vaddr_scu);
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if (rv != 0)
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return (rv);
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/* Enable SCU */
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val = bus_space_read_4(fdtbus_bs_tag, vaddr_scu, MV_SCU_REG_CTRL);
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if (!(val & MV_SCU_ENABLE)) {
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/* Enable SCU Speculative linefills to L2 */
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val |= MV_SCU_SL_L2_ENABLE;
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bus_space_write_4(fdtbus_bs_tag, vaddr_scu, 0,
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val | MV_SCU_ENABLE);
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}
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bus_space_unmap(fdtbus_bs_tag, vaddr_scu, MV_SCU_REGS_LEN);
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return (0);
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}
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