165 lines
5.8 KiB
C
165 lines
5.8 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clkdev_if.h"
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#include "periph.h"
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#define NB_DEV_COUNT 17
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static struct clk_div_table a37x0_periph_clk_table_6 [] = {
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{ .value = 1, .divider = 1 },
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{ .value = 2, .divider = 2 },
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{ .value = 3, .divider = 3 },
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{ .value = 4, .divider = 4 },
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{ .value = 5, .divider = 5 },
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{ .value = 6, .divider = 6 },
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{ .value = 0, .divider = 0 }
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};
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static struct clk_div_table a37x0_periph_clk_table_2 [] = {
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{ .value = 0, .divider = 1 },
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{ .value = 1, .divider = 2 },
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{ .value = 2, .divider = 4 },
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{ .value = 3, .divider = 1 }
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};
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static struct a37x0_periph_clknode_def a37x0_nb_devices [] = {
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CLK_FULL_DD("mmc", 0, 2, 0, 0, DIV_SEL2, DIV_SEL2, 16, 13,
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"tbg_mux_mmc_50", "div1_mmc_51", "div2_mmc_52", "clk_mux_mmc_53"),
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CLK_FULL_DD("sata_host", 1, 3, 2, 1, DIV_SEL2, DIV_SEL2, 10, 7,
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"tbg_sata_host_mmc_55", "div1_sata_host_56", "div2_sata_host_57",
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"clk_sata_host_mmc_58"),
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CLK_FULL_DD("sec_at", 2, 6, 4, 2, DIV_SEL1, DIV_SEL1, 3, 0,
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"tbg_mux_sec_at_60", "div1_sec_at_61", "div2_sec_at_62",
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"clk_mux_sec_at_63"),
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CLK_FULL_DD("sec_dap", 3, 7, 6, 3, DIV_SEL1, DIV_SEL1, 9, 6,
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"tbg_mux_sec_dap_65", "div1_sec_dap_67", "div2_sec_dap_68",
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"clk_mux_sec_dap_69"),
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CLK_FULL_DD("tsecm", 4, 8, 8, 4, DIV_SEL1, DIV_SEL1, 15, 12,
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"tbg_mux_tsecm_71", "div1_tsecm_72", "div2_tsecm_73",
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"clk_mux_tsecm_74"),
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CLK_FULL("setm_tmx", 5, 10, 10, 5, DIV_SEL1, 18,
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a37x0_periph_clk_table_6, "tbg_mux_setm_tmx_76",
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"div1_setm_tmx_77", "clk_mux_setm_tmx_78"),
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CLK_FIXED("avs", 6, 11, 6, "mux_avs_80", "fixed1_avs_82"),
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CLK_FULL_DD("pwm", 7, 13, 14, 8, DIV_SEL0, DIV_SEL0, 3, 0,
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"tbg_mux_pwm_83", "div1_pwm_84", "div2_pwm_85", "clk_mux_pwm_86"),
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CLK_FULL_DD("sqf", 8, 12, 12, 7, DIV_SEL1, DIV_SEL1, 27, 14,
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"tbg_mux_sqf_88", "div1_sqf_89", "div2_sqf_90", "clk_mux_sqf_91"),
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CLK_GATE("i2c_2", 9, 16, NULL),
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CLK_GATE("i2c_1", 10, 17, NULL),
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CLK_MUX_GATE_FIXED("ddr_phy", 11, 19, 10, "mux_ddr_phy_95",
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"gate_ddr_phy_96", "fixed1_ddr_phy_97"),
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CLK_FULL_DD("ddr_fclk", 12, 21, 16, 11, DIV_SEL0, DIV_SEL0, 15, 12,
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"tbg_mux_ddr_fclk_99", "div1_ddr_fclk_100", "div2_ddr_fclk_101",
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"clk_mux_ddr_fclk_102"),
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CLK_FULL("trace", 13, 22, 18, 12, DIV_SEL0, 20,
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a37x0_periph_clk_table_6, "tbg_mux_trace_104", "div1_trace_105",
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"clk_mux_trace_106"),
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CLK_FULL("counter", 14, 23, 20, 13, DIV_SEL0, 23,
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a37x0_periph_clk_table_6, "tbg_mux_counter_108",
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"div1_counter_109", "clk_mux_counter_110"),
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CLK_FULL_DD("eip97", 15, 26, 24, 9, DIV_SEL2, DIV_SEL2, 22, 19,
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"tbg_mux_eip97_112", "div1_eip97_113", "div2_eip97_114",
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"clk_mux_eip97_115"),
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CLK_CPU("cpu", 16, 22, 15, DIV_SEL0, 28, a37x0_periph_clk_table_2,
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"tbg_mux_cpu_117", "div1_cpu_118"),
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};
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static struct ofw_compat_data a37x0_periph_compat_data [] = {
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{ "marvell,armada-3700-periph-clock-nb", 1 },
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{ NULL, 0 }
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};
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static int a37x0_nb_periph_clk_attach(device_t);
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static int a37x0_nb_periph_clk_probe(device_t);
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static device_method_t a37x0_nb_periph_clk_methods[] = {
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DEVMETHOD(clkdev_device_unlock, a37x0_periph_clk_device_unlock),
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DEVMETHOD(clkdev_device_lock, a37x0_periph_clk_device_lock),
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DEVMETHOD(clkdev_read_4, a37x0_periph_clk_read_4),
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DEVMETHOD(device_attach, a37x0_nb_periph_clk_attach),
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DEVMETHOD(device_detach, a37x0_periph_clk_detach),
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DEVMETHOD(device_probe, a37x0_nb_periph_clk_probe),
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DEVMETHOD_END
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};
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static driver_t a37x0_nb_periph_driver = {
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"a37x0_nb_periph_driver",
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a37x0_nb_periph_clk_methods,
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sizeof(struct a37x0_periph_clk_softc)
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};
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EARLY_DRIVER_MODULE(a37x0_nb_periph, simplebus, a37x0_nb_periph_driver, 0, 0,
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BUS_PASS_TIMER + BUS_PASS_ORDER_LATE);
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static int
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a37x0_nb_periph_clk_attach(device_t dev)
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{
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struct a37x0_periph_clk_softc *sc;
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sc = device_get_softc(dev);
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sc->devices = a37x0_nb_devices;
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sc->device_count = NB_DEV_COUNT;
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return (a37x0_periph_clk_attach(dev));
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}
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static int
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a37x0_nb_periph_clk_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev,
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a37x0_periph_compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "marvell,armada-3700-nb-periph-clock");
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return (BUS_PROBE_DEFAULT);
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}
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