07c5be33f1
This patch introduces clkgen driver for Armada38x SoCs. Clock topology consists of single coreclk which supplies clock signal to CPU cores and peripherials. Reviewed by: manu Obtained from: Semihalf Differential Revision: https://reviews.freebsd.org/D36453
101 lines
3.0 KiB
C
101 lines
3.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <dev/extres/clk/clk.h>
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#include <arm/mv/clk/armada38x_gen.h>
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#include "clkdev_if.h"
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#define SAR_A38X_TCLK_FREQ_SHIFT 15
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#define SAR_A38X_TCLK_FREQ_MASK 0x00008000
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#define TCLK_250MHZ 250 * 1000 * 1000
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#define TCLK_200MHZ 200 * 1000 * 1000
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#define WR4(_clk, offset, val) \
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CLKDEV_WRITE_4(clknode_get_device(_clk), offset, val)
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#define RD4(_clk, offset, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), offset, val)
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#define DEVICE_LOCK(_clk) \
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CLKDEV_DEVICE_LOCK(clknode_get_device(_clk))
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#define DEVICE_UNLOCK(_clk) \
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CLKDEV_DEVICE_UNLOCK(clknode_get_device(_clk))
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static int
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armada38x_gen_recalc(struct clknode *clk, uint64_t *freq)
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{
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uint32_t reg;
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DEVICE_LOCK(clk);
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RD4(clk, 0, ®);
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DEVICE_UNLOCK(clk);
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reg = (reg & SAR_A38X_TCLK_FREQ_MASK) >> SAR_A38X_TCLK_FREQ_SHIFT;
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*freq = reg ? TCLK_200MHZ : TCLK_250MHZ;
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return (0);
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}
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static int
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armada38x_gen_init(struct clknode *clk, device_t dev)
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{
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return (0);
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}
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static clknode_method_t armada38x_gen_clknode_methods[] = {
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/* Device interface */
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CLKNODEMETHOD(clknode_init, armada38x_gen_init),
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CLKNODEMETHOD(clknode_recalc_freq, armada38x_gen_recalc),
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CLKNODEMETHOD_END
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};
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DEFINE_CLASS_1(armada38x_gen_clknode, armada38x_gen_clknode_class,
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armada38x_gen_clknode_methods, 0, clknode_class);
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int
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armada38x_gen_register(struct clkdom *clkdom, const struct armada38x_gen_clknode_def *clkdef)
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{
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struct clknode *clk;
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clk = clknode_create(clkdom, &armada38x_gen_clknode_class, &clkdef->def);
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if (clk == NULL)
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return (1);
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clknode_register(clkdom, clk);
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return(0);
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}
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