f21c469dbc
Add driver for Marvell, Armada-37xx peripheral clock. Register clocks for various peripheral devices in north bridge or south bridge domain. Dump clock's domain while verbose boot. Reviewed by: Obtained from: Semihalf Differential revision: https://reviews.freebsd.org/D32294
423 lines
15 KiB
C
423 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*
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*/
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#ifndef _PERIPH_H_
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#define _PERIPH_H_
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_gate.h>
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#define TBG_SEL 0x0
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#define DIV_SEL0 0x4
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#define DIV_SEL1 0x8
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#define DIV_SEL2 0xC
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#define CLK_SEL 0x10
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#define CLK_DIS 0x14
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#define DIV_MASK 0x7
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#define MUX_POS 1
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#define DIV1_POS 2
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#define DIV2_POS 3
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#define GATE_POS 4
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#define FIXED1_POS 5
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#define FIXED2_POS 6
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#define CLK_MUX_POS 7
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#define RD4(_clk, offset, val) \
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CLKDEV_READ_4(clknode_get_device(_clk), offset, val)
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#define A37x0_INTERNAL_CLK_ID(_base, _pos) \
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((_base * 10) + (_pos))
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#define CLK_FULL_DD(_name, _id, _gate_shift, _tbg_mux_shift, \
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_clk_mux_shift, _div1_reg, _div2_reg, _div1_shift, _div2_shift, \
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_tbg_mux_name, _div1_name, _div2_name, _clk_mux_name) \
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{ \
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.type = CLK_FULL_DD, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.full_dd.tbg_mux.clkdef.name = _tbg_mux_name, \
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.clk_def.full_dd.tbg_mux.offset = TBG_SEL, \
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.clk_def.full_dd.tbg_mux.shift = _tbg_mux_shift, \
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.clk_def.full_dd.tbg_mux.width = 0x2, \
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.clk_def.full_dd.tbg_mux.mux_flags = 0x0, \
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.clk_def.full_dd.div1.clkdef.name = _div1_name, \
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.clk_def.full_dd.div1.offset = _div1_reg, \
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.clk_def.full_dd.div1.i_shift = _div1_shift, \
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.clk_def.full_dd.div1.i_width = 0x3, \
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.clk_def.full_dd.div1.f_shift = 0x0, \
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.clk_def.full_dd.div1.f_width = 0x0, \
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.clk_def.full_dd.div1.div_flags = 0x0, \
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.clk_def.full_dd.div1.div_table = NULL, \
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.clk_def.full_dd.div2.clkdef.name = _div2_name, \
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.clk_def.full_dd.div2.offset = _div2_reg, \
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.clk_def.full_dd.div2.i_shift = _div2_shift, \
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.clk_def.full_dd.div2.i_width = 0x3, \
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.clk_def.full_dd.div2.f_shift = 0x0, \
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.clk_def.full_dd.div2.f_width = 0x0, \
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.clk_def.full_dd.div2.div_flags = 0x0, \
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.clk_def.full_dd.div2.div_table = NULL, \
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.clk_def.full_dd.clk_mux.clkdef.name = _clk_mux_name, \
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.clk_def.full_dd.clk_mux.offset = CLK_SEL, \
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.clk_def.full_dd.clk_mux.shift = _clk_mux_shift, \
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.clk_def.full_dd.clk_mux.width = 0x1, \
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.clk_def.full_dd.clk_mux.mux_flags = 0x0, \
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.clk_def.full_dd.gate.clkdef.name = _name, \
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.clk_def.full_dd.gate.offset = CLK_DIS, \
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.clk_def.full_dd.gate.shift = _gate_shift, \
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.clk_def.full_dd.gate.on_value = 0, \
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.clk_def.full_dd.gate.off_value = 1, \
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.clk_def.full_dd.gate.mask = 0x1, \
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.clk_def.full_dd.gate.gate_flags = 0x0 \
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}
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#define CLK_FULL(_name, _id, _gate_shift, _tbg_mux_shift, \
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_clk_mux_shift, _div1_reg, _div1_shift, _div_table, _tbg_mux_name, \
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_div1_name, _clk_mux_name) \
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{ \
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.type = CLK_FULL, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.full_d.tbg_mux.clkdef.name = _tbg_mux_name, \
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.clk_def.full_d.tbg_mux.offset = TBG_SEL, \
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.clk_def.full_d.tbg_mux.shift = _tbg_mux_shift, \
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.clk_def.full_d.tbg_mux.width = 0x2, \
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.clk_def.full_d.tbg_mux.mux_flags = 0x0, \
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.clk_def.full_d.div.clkdef.name = _div1_name, \
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.clk_def.full_d.div.offset = _div1_reg, \
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.clk_def.full_d.div.i_shift = _div1_shift, \
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.clk_def.full_d.div.i_width = 0x3, \
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.clk_def.full_d.div.f_shift = 0x0, \
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.clk_def.full_d.div.f_width = 0x0, \
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.clk_def.full_d.div.div_flags = 0x0, \
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.clk_def.full_d.div.div_table = _div_table, \
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.clk_def.full_d.clk_mux.clkdef.name = _clk_mux_name, \
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.clk_def.full_d.clk_mux.offset = CLK_SEL, \
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.clk_def.full_d.clk_mux.shift = _clk_mux_shift, \
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.clk_def.full_d.clk_mux.width = 0x1, \
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.clk_def.full_d.clk_mux.mux_flags = 0x0, \
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.clk_def.full_d.gate.clkdef.name = _name, \
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.clk_def.full_d.gate.offset = CLK_DIS, \
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.clk_def.full_d.gate.shift = _gate_shift, \
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.clk_def.full_d.gate.on_value = 0, \
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.clk_def.full_d.gate.off_value = 1, \
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.clk_def.full_d.gate.mask = 0x1, \
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.clk_def.full_d.gate.gate_flags = 0x0 \
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}
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#define CLK_CPU(_name, _id, _tbg_mux_shift, _clk_mux_shift, _div1_reg, \
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_div1_shift, _div_table, _tbg_mux_name, _div1_name) \
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{ \
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.type = CLK_CPU, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.cpu.tbg_mux.clkdef.name = _tbg_mux_name, \
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.clk_def.cpu.tbg_mux.offset = TBG_SEL, \
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.clk_def.cpu.tbg_mux.shift = _tbg_mux_shift, \
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.clk_def.cpu.tbg_mux.width = 0x2, \
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.clk_def.cpu.tbg_mux.mux_flags = 0x0, \
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.clk_def.cpu.div.clkdef.name = _div1_name, \
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.clk_def.cpu.div.offset = _div1_reg, \
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.clk_def.cpu.div.i_shift = _div1_shift, \
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.clk_def.cpu.div.i_width = 0x3, \
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.clk_def.cpu.div.f_shift = 0x0, \
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.clk_def.cpu.div.f_width = 0x0, \
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.clk_def.cpu.div.div_flags = 0x0, \
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.clk_def.cpu.div.div_table = _div_table, \
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.clk_def.cpu.clk_mux.clkdef.name = _name, \
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.clk_def.cpu.clk_mux.offset = CLK_SEL, \
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.clk_def.cpu.clk_mux.shift = _clk_mux_shift, \
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.clk_def.cpu.clk_mux.width = 0x1, \
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.clk_def.cpu.clk_mux.mux_flags = 0x0, \
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}
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#define CLK_GATE(_name, _id, _gate_shift, _pname) \
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{ \
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.type = CLK_GATE, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.common_def.pname = _pname, \
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.clk_def.gate.gate.clkdef.name = _name, \
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.clk_def.gate.gate.clkdef.parent_cnt = 1, \
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.clk_def.gate.gate.offset = CLK_DIS, \
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.clk_def.gate.gate.shift = _gate_shift, \
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.clk_def.gate.gate.on_value = 0, \
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.clk_def.gate.gate.off_value = 1, \
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.clk_def.gate.gate.mask = 0x1, \
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.clk_def.gate.gate.gate_flags = 0x0 \
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}
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#define CLK_MDD(_name, _id, _tbg_mux_shift, _clk_mux_shift, _div1_reg, \
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_div2_reg, _div1_shift, _div2_shift, _tbg_mux_name, _div1_name, \
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_div2_name) \
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{ \
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.type = CLK_MDD, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.mdd.tbg_mux.clkdef.name = _tbg_mux_name, \
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.clk_def.mdd.tbg_mux.offset = TBG_SEL, \
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.clk_def.mdd.tbg_mux.shift = _tbg_mux_shift, \
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.clk_def.mdd.tbg_mux.width = 0x2, \
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.clk_def.mdd.tbg_mux.mux_flags = 0x0, \
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.clk_def.mdd.div1.clkdef.name = _div1_name, \
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.clk_def.mdd.div1.offset = _div1_reg, \
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.clk_def.mdd.div1.i_shift = _div1_shift, \
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.clk_def.mdd.div1.i_width = 0x3, \
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.clk_def.mdd.div1.f_shift = 0x0, \
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.clk_def.mdd.div1.f_width = 0x0, \
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.clk_def.mdd.div1.div_flags = 0x0, \
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.clk_def.mdd.div1.div_table = NULL, \
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.clk_def.mdd.div2.clkdef.name = _div2_name, \
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.clk_def.mdd.div2.offset = _div2_reg, \
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.clk_def.mdd.div2.i_shift = _div2_shift, \
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.clk_def.mdd.div2.i_width = 0x3, \
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.clk_def.mdd.div2.f_shift = 0x0, \
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.clk_def.mdd.div2.f_width = 0x0, \
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.clk_def.mdd.div2.div_flags = 0x0, \
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.clk_def.mdd.div2.div_table = NULL, \
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.clk_def.mdd.clk_mux.clkdef.name = _name, \
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.clk_def.mdd.clk_mux.offset = CLK_SEL, \
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.clk_def.mdd.clk_mux.shift = _clk_mux_shift, \
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.clk_def.mdd.clk_mux.width = 0x1, \
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.clk_def.mdd.clk_mux.mux_flags = 0x0 \
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}
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#define CLK_MUX_GATE(_name, _id, _gate_shift, _mux_shift, _pname, \
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_mux_name, _fixed_name) \
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{ \
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.type = CLK_MUX_GATE, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.common_def.pname = _pname, \
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.clk_def.mux_gate.mux.clkdef.name = _mux_name, \
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.clk_def.mux_gate.mux.offset = TBG_SEL, \
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.clk_def.mux_gate.mux.shift = _mux_shift, \
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.clk_def.mux_gate.mux.width = 0x1, \
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.clk_def.mux_gate.mux.mux_flags = 0x0, \
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.clk_def.mux_gate.gate.clkdef.name = _name, \
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.clk_def.mux_gate.gate.offset = CLK_DIS, \
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.clk_def.mux_gate.gate.shift = _gate_shift, \
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.clk_def.mux_gate.gate.on_value = 0, \
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.clk_def.mux_gate.gate.off_value = 1, \
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.clk_def.mux_gate.gate.mask = 0x1, \
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.clk_def.mux_gate.gate.gate_flags = 0x0, \
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.clk_def.mux_gate.fixed.clkdef.name = _fixed_name \
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}
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#define CLK_MUX_GATE_FIXED(_name, _id, _gate_shift, _mux_shift, \
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_mux_name, _gate_name, _fixed1_name) \
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{ \
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.type = CLK_MUX_GATE_FIXED, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.mux_gate_fixed.mux.clkdef.name = _mux_name, \
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.clk_def.mux_gate_fixed.mux.offset = TBG_SEL, \
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.clk_def.mux_gate_fixed.mux.shift = _mux_shift, \
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.clk_def.mux_gate_fixed.mux.width = 0x1, \
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.clk_def.mux_gate_fixed.mux.mux_flags = 0x0, \
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.clk_def.mux_gate_fixed.gate.clkdef.name = _gate_name, \
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.clk_def.mux_gate_fixed.gate.offset = CLK_DIS, \
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.clk_def.mux_gate_fixed.gate.shift = _gate_shift, \
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.clk_def.mux_gate_fixed.gate.on_value = 0, \
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.clk_def.mux_gate_fixed.gate.off_value = 1, \
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.clk_def.mux_gate_fixed.gate.mask = 0x1, \
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.clk_def.mux_gate_fixed.gate.gate_flags = 0x0, \
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.clk_def.mux_gate_fixed.fixed1.clkdef.name = _fixed1_name, \
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.clk_def.mux_gate_fixed.fixed2.clkdef.name = _name \
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}
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#define CLK_FIXED(_name, _id, _gate_shift, _mux_shift, _mux_name, \
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_fixed_name) \
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{ \
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.type = CLK_FIXED, \
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.common_def.device_name = _name, \
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.common_def.device_id = _id, \
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.clk_def.fixed.mux.clkdef.name = _mux_name, \
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.clk_def.fixed.mux.offset = TBG_SEL, \
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.clk_def.fixed.mux.shift = _mux_shift, \
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.clk_def.fixed.mux.width = 0x1, \
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.clk_def.fixed.mux.mux_flags = 0x0, \
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.clk_def.fixed.gate.clkdef.name = _name, \
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.clk_def.fixed.gate.offset = CLK_DIS, \
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.clk_def.fixed.gate.shift = _gate_shift, \
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.clk_def.fixed.gate.on_value = 0, \
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.clk_def.fixed.gate.off_value = 1, \
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.clk_def.fixed.gate.mask = 0x1, \
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.clk_def.fixed.gate.gate_flags = 0x0, \
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.clk_def.fixed.fixed.clkdef.name = _fixed_name \
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}
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struct a37x0_periph_clk_softc {
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device_t dev;
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struct resource *res;
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struct clkdom *clkdom;
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struct mtx mtx;
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struct a37x0_periph_clknode_def *devices;
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int device_count;
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};
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struct a37x0_periph_clk_dd_def {
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struct clk_mux_def tbg_mux;
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struct clk_div_def div1;
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struct clk_div_def div2;
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struct clk_mux_def clk_mux;
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struct clk_gate_def gate;
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};
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struct a37x0_periph_clk_cpu_def {
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struct clk_mux_def tbg_mux;
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struct clk_div_def div;
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struct clk_mux_def clk_mux;
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};
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struct a37x0_periph_clk_d_def {
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struct clk_mux_def tbg_mux;
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struct clk_div_def div;
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struct clk_mux_def clk_mux;
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struct clk_gate_def gate;
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};
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struct a37x0_periph_clk_fixed_def {
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struct clk_mux_def mux;
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struct clk_fixed_def fixed;
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struct clk_gate_def gate;
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};
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struct a37x0_periph_clk_gate_def {
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struct clk_gate_def gate;
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};
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struct a37x0_periph_clk_mux_dd_def {
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struct clk_mux_def tbg_mux;
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struct clk_div_def div1;
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struct clk_div_def div2;
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struct clk_mux_def clk_mux;
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};
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struct a37x0_periph_clk_mux_div_def {
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struct clk_mux_def mux;
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struct clk_div_def div;
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};
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struct a37x0_periph_clk_mux_gate_def {
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struct clk_mux_def mux;
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struct clk_fixed_def fixed;
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struct clk_gate_def gate;
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};
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struct a37x0_periph_clk_mux_gate_fixed_def {
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struct clk_fixed_def fixed1;
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struct clk_mux_def mux;
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struct clk_gate_def gate;
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struct clk_fixed_def fixed2;
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};
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enum a37x0_periph_clk_type {
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/* Double divider clock */
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CLK_FULL_DD,
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/* Single divider clock */
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CLK_FULL,
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/* Gate clock */
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CLK_GATE,
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/* Mux, gate clock */
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CLK_MUX_GATE,
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/* CPU clock */
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CLK_CPU,
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/* Clock with fixed frequency divider */
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CLK_FIXED,
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/* Clock with double divider, without gate */
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CLK_MDD,
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/* Clock with two fixed frequency dividers */
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CLK_MUX_GATE_FIXED
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};
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struct a37x0_periph_common_defs {
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char *device_name;
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int device_id;
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int tbg_cnt;
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const char *pname;
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const char **tbgs;
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const char *xtal;
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};
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union a37x0_periph_clocks_defs {
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struct a37x0_periph_clk_dd_def full_dd;
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struct a37x0_periph_clk_d_def full_d;
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struct a37x0_periph_clk_gate_def gate;
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struct a37x0_periph_clk_mux_gate_def mux_gate;
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struct a37x0_periph_clk_cpu_def cpu;
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struct a37x0_periph_clk_fixed_def fixed;
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struct a37x0_periph_clk_mux_dd_def mdd;
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struct a37x0_periph_clk_mux_gate_fixed_def mux_gate_fixed;
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};
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struct a37x0_periph_clknode_def {
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enum a37x0_periph_clk_type type;
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struct a37x0_periph_common_defs common_def;
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union a37x0_periph_clocks_defs clk_def;
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};
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int a37x0_periph_create_mux(struct clkdom *,
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struct clk_mux_def *, int);
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int a37x0_periph_create_div(struct clkdom *,
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struct clk_div_def *, int);
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int a37x0_periph_create_gate(struct clkdom *,
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struct clk_gate_def *, int);
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void a37x0_periph_set_props(struct clknode_init_def *, const char **,
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unsigned int);
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int a37x0_periph_d_register_full_clk_dd(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_d_register_full_clk(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_d_register_periph_cpu(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_fixed_register_fixed(struct clkdom*,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_gate_register_gate(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_d_register_mdd(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_d_register_mux_div_clk(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_register_mux_gate(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_register_mux_gate_fixed(struct clkdom *,
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struct a37x0_periph_clknode_def *);
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int a37x0_periph_clk_read_4(device_t, bus_addr_t, uint32_t *);
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void a37x0_periph_clk_device_unlock(device_t);
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void a37x0_periph_clk_device_lock(device_t);
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int a37x0_periph_clk_attach(device_t);
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int a37x0_periph_clk_detach(device_t);
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#endif
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