275 lines
8.0 KiB
C
275 lines
8.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Semihalf.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_gate.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "clkdev_if.h"
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#include "periph.h"
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#define PARENT_CNT 2
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/*
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* Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
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* div2 (second frequency divider) -> mux (select divided freq.
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* or xtal output) -> gate (enable or disable clock), which is also final node
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*/
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int
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a37x0_periph_d_register_full_clk_dd(struct clkdom *clkdom,
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struct a37x0_periph_clknode_def *device_def)
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{
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const char *parent_names[PARENT_CNT];
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struct clk_mux_def *clk_mux;
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struct clk_mux_def *tbg_mux;
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struct clk_gate_def *gate;
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struct clk_div_def *div1;
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struct clk_div_def *div2;
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int error, dev_id;
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dev_id = device_def->common_def.device_id;
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tbg_mux = &device_def->clk_def.full_dd.tbg_mux;
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div1 = &device_def->clk_def.full_dd.div1;
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div2 = &device_def->clk_def.full_dd.div2;
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gate = &device_def->clk_def.full_dd.gate;
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clk_mux = &device_def->clk_def.full_dd.clk_mux;
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a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,
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device_def->common_def.tbg_cnt);
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error = a37x0_periph_create_mux(clkdom,
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tbg_mux, A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div1,
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A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div2,
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A37x0_INTERNAL_CLK_ID(dev_id, DIV2_POS));
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if (error)
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goto fail;
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parent_names[0] = device_def->common_def.xtal;
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parent_names[1] = div2->clkdef.name;
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a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);
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error = a37x0_periph_create_mux(clkdom, clk_mux,
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A37x0_INTERNAL_CLK_ID(dev_id, CLK_MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1);
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error = a37x0_periph_create_gate(clkdom, gate,
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dev_id);
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if (error)
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goto fail;
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fail:
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return (error);
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}
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/*
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* Register chain: mux (select proper TBG) -> div1 (first frequency divider) ->
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* mux (select divided freq. or xtal output) -> gate (enable or disable clock),
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* which is also final node
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*/
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int
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a37x0_periph_d_register_full_clk(struct clkdom *clkdom,
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struct a37x0_periph_clknode_def *device_def)
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{
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const char *parent_names[PARENT_CNT];
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struct clk_mux_def *tbg_mux;
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struct clk_mux_def *clk_mux;
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struct clk_gate_def *gate;
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struct clk_div_def *div;
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int error, dev_id;
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dev_id = device_def->common_def.device_id;
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tbg_mux = &device_def->clk_def.full_d.tbg_mux;
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div = &device_def->clk_def.full_d.div;
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gate = &device_def->clk_def.full_d.gate;
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clk_mux = &device_def->clk_def.full_d. clk_mux;
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a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,
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device_def->common_def.tbg_cnt);
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error = a37x0_periph_create_mux(clkdom, tbg_mux,
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A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div,
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A37x0_INTERNAL_CLK_ID(device_def->common_def.device_id, DIV1_POS));
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if (error)
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goto fail;
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parent_names[0] = device_def->common_def.xtal;
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parent_names[1] = div->clkdef.name;
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a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);
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error = a37x0_periph_create_mux(clkdom, clk_mux,
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A37x0_INTERNAL_CLK_ID(dev_id, CLK_MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&gate->clkdef, &clk_mux->clkdef.name, 1);
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error = a37x0_periph_create_gate(clkdom, gate,
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dev_id);
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if (error)
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goto fail;
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fail:
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return (error);
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}
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/*
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* Register CPU clock. It consists of mux (select proper TBG) -> div (frequency
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* divider) -> mux (choose divided or xtal output).
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*/
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int
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a37x0_periph_d_register_periph_cpu(struct clkdom *clkdom,
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struct a37x0_periph_clknode_def *device_def)
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{
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const char *parent_names[PARENT_CNT];
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struct clk_mux_def *clk_mux;
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struct clk_mux_def *tbg_mux;
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struct clk_div_def *div;
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int error, dev_id;
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dev_id = device_def->common_def.device_id;
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tbg_mux = &device_def->clk_def.cpu.tbg_mux;
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div = &device_def->clk_def.cpu.div;
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clk_mux = &device_def->clk_def.cpu.clk_mux;
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a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,
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device_def->common_def.tbg_cnt);
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error = a37x0_periph_create_mux(clkdom, tbg_mux,
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A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div->clkdef, &tbg_mux->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div,
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A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS));
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if (error)
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goto fail;
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parent_names[0] = device_def->common_def.xtal;
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parent_names[1] = div->clkdef.name;
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a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);
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error = a37x0_periph_create_mux(clkdom, clk_mux,
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dev_id);
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fail:
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return (error);
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}
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/*
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* Register chain: mux (choose proper TBG) -> div1 (first frequency divider) ->
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* div2 (second frequency divider) -> mux (choose divided or xtal output).
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*/
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int
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a37x0_periph_d_register_mdd(struct clkdom *clkdom,
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struct a37x0_periph_clknode_def *device_def)
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{
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const char *parent_names[PARENT_CNT];
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struct clk_mux_def *tbg_mux;
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struct clk_mux_def *clk_mux;
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struct clk_div_def *div1;
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struct clk_div_def *div2;
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int error, dev_id;
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dev_id = device_def->common_def.device_id;
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tbg_mux = &device_def->clk_def.mdd.tbg_mux;
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div1 = &device_def->clk_def.mdd.div1;
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div2 = &device_def->clk_def.mdd.div2;
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clk_mux = &device_def->clk_def.mdd.clk_mux;
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a37x0_periph_set_props(&tbg_mux->clkdef, device_def->common_def.tbgs,
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device_def->common_def.tbg_cnt);
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error = a37x0_periph_create_mux(clkdom, tbg_mux,
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A37x0_INTERNAL_CLK_ID(dev_id, MUX_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div1->clkdef, &tbg_mux->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div1,
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A37x0_INTERNAL_CLK_ID(dev_id, DIV1_POS));
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if (error)
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goto fail;
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a37x0_periph_set_props(&div2->clkdef, &div1->clkdef.name, 1);
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error = a37x0_periph_create_div(clkdom, div2,
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A37x0_INTERNAL_CLK_ID(dev_id, DIV2_POS));
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if (error)
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goto fail;
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parent_names[0] = device_def->common_def.xtal;
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parent_names[1] = div2->clkdef.name;
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a37x0_periph_set_props(&clk_mux->clkdef, parent_names, PARENT_CNT);
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error = a37x0_periph_create_mux(clkdom, clk_mux,
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dev_id);
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if (error)
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goto fail;
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fail:
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return (error);
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}
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