c0e5e270a5
Sponsored by: Juniper Networks, Inc. Differential Revision: https://reviews.freebsd.org/D37791
628 lines
26 KiB
C
628 lines
26 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2003 Stuart Walsh
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 'AS IS' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/* $FreeBSD$ */
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#ifndef _BFE_H
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#define _BFE_H
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/* PCI registers */
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#define BFE_PCI_MEMLO 0x10
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#define BFE_PCI_MEMHIGH 0x14
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#define BFE_PCI_INTLINE 0x3C
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/* Register layout. */
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#define BFE_DEVCTRL 0x00000000 /* Device Control */
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#define BFE_PFE 0x00000080 /* Pattern Filtering Enable */
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#define BFE_IPP 0x00000400 /* Internal EPHY Present */
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#define BFE_EPR 0x00008000 /* EPHY Reset */
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#define BFE_PME 0x00001000 /* PHY Mode Enable */
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#define BFE_PMCE 0x00002000 /* PHY Mode Clocks Enable */
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#define BFE_PADDR 0x0007c000 /* PHY Address */
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#define BFE_PADDR_SHIFT 18
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#define BFE_BIST_STAT 0x0000000C /* Built-In Self-Test Status */
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#define BFE_WKUP_LEN 0x00000010 /* Wakeup Length */
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#define BFE_ISTAT 0x00000020 /* Interrupt Status */
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#define BFE_ISTAT_PME 0x00000040 /* Power Management Event */
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#define BFE_ISTAT_TO 0x00000080 /* General Purpose Timeout */
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#define BFE_ISTAT_DSCE 0x00000400 /* Descriptor Error */
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#define BFE_ISTAT_DATAE 0x00000800 /* Data Error */
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#define BFE_ISTAT_DPE 0x00001000 /* Descr. Protocol Error */
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#define BFE_ISTAT_RDU 0x00002000 /* Receive Descr. Underflow */
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#define BFE_ISTAT_RFO 0x00004000 /* Receive FIFO Overflow */
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#define BFE_ISTAT_TFU 0x00008000 /* Transmit FIFO Underflow */
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#define BFE_ISTAT_RX 0x00010000 /* RX Interrupt */
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#define BFE_ISTAT_TX 0x01000000 /* TX Interrupt */
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#define BFE_ISTAT_EMAC 0x04000000 /* EMAC Interrupt */
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#define BFE_ISTAT_MII_WRITE 0x08000000 /* MII Write Interrupt */
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#define BFE_ISTAT_MII_READ 0x10000000 /* MII Read Interrupt */
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#define BFE_ISTAT_ERRORS (BFE_ISTAT_DSCE | BFE_ISTAT_DATAE | BFE_ISTAT_DPE |\
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BFE_ISTAT_RDU | BFE_ISTAT_RFO | BFE_ISTAT_TFU)
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#define BFE_IMASK 0x00000024 /* Interrupt Mask */
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#define BFE_IMASK_DEF (BFE_ISTAT_ERRORS | BFE_ISTAT_TO | BFE_ISTAT_RX | \
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BFE_ISTAT_TX)
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#define BFE_MAC_CTRL 0x000000A8 /* MAC Control */
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#define BFE_CTRL_CRC32_ENAB 0x00000001 /* CRC32 Generation Enable */
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#define BFE_CTRL_PDOWN 0x00000004 /* Onchip EPHY Powerdown */
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#define BFE_CTRL_EDET 0x00000008 /* Onchip EPHY Energy Detected */
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#define BFE_CTRL_LED 0x000000e0 /* Onchip EPHY LED Control */
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#define BFE_CTRL_LED_SHIFT 5
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#define BFE_MAC_FLOW 0x000000AC /* MAC Flow Control */
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#define BFE_FLOW_RX_HIWAT 0x000000ff /* Onchip FIFO HI Water Mark */
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#define BFE_FLOW_PAUSE_ENAB 0x00008000 /* Enable Pause Frame Generation */
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#define BFE_RCV_LAZY 0x00000100 /* Lazy Interrupt Control */
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#define BFE_LAZY_TO_MASK 0x00ffffff /* Timeout */
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#define BFE_LAZY_FC_MASK 0xff000000 /* Frame Count */
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#define BFE_LAZY_FC_SHIFT 24
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#define BFE_DMATX_CTRL 0x00000200 /* DMA TX Control */
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#define BFE_TX_CTRL_ENABLE 0x00000001 /* Enable */
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#define BFE_TX_CTRL_SUSPEND 0x00000002 /* Suepend Request */
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#define BFE_TX_CTRL_LPBACK 0x00000004 /* Loopback Enable */
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#define BFE_TX_CTRL_FAIRPRI 0x00000008 /* Fair Priority */
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#define BFE_TX_CTRL_FLUSH 0x00000010 /* Flush Request */
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#define BFE_DMATX_ADDR 0x00000204 /* DMA TX Descriptor Ring Address */
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#define BFE_DMATX_PTR 0x00000208 /* DMA TX Last Posted Descriptor */
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#define BFE_DMATX_STAT 0x0000020C /* DMA TX Current Active Desc. + Status */
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#define BFE_STAT_CDMASK 0x00000fff /* Current Descriptor Mask */
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#define BFE_STAT_SMASK 0x0000f000 /* State Mask */
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#define BFE_STAT_DISABLE 0x00000000 /* State Disabled */
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#define BFE_STAT_SACTIVE 0x00001000 /* State Active */
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#define BFE_STAT_SIDLE 0x00002000 /* State Idle Wait */
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#define BFE_STAT_STOPPED 0x00003000 /* State Stopped */
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#define BFE_STAT_SSUSP 0x00004000 /* State Suspend Pending */
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#define BFE_STAT_EMASK 0x000f0000 /* Error Mask */
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#define BFE_STAT_ENONE 0x00000000 /* Error None */
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#define BFE_STAT_EDPE 0x00010000 /* Error Desc. Protocol Error */
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#define BFE_STAT_EDFU 0x00020000 /* Error Data FIFO Underrun */
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#define BFE_STAT_EBEBR 0x00030000 /* Error Bus Error on Buffer Read */
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#define BFE_STAT_EBEDA 0x00040000 /* Error Bus Error on Desc. Access */
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#define BFE_STAT_FLUSHED 0x00100000 /* Flushed */
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#define BFE_DMARX_CTRL 0x00000210 /* DMA RX Control */
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#define BFE_RX_CTRL_ENABLE 0x00000001 /* Enable */
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#define BFE_RX_CTRL_ROMASK 0x000000fe /* Receive Offset Mask */
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#define BFE_RX_CTRL_ROSHIFT 1 /* Receive Offset Shift */
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#define BFE_DMARX_ADDR 0x00000214 /* DMA RX Descriptor Ring Address */
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#define BFE_DMARX_PTR 0x00000218 /* DMA RX Last Posted Descriptor */
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#define BFE_DMARX_STAT 0x0000021C /* DMA RX Current Active Desc. + Status */
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#define BFE_RXCONF 0x00000400 /* EMAC RX Config */
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#define BFE_RXCONF_DBCAST 0x00000001 /* Disable Broadcast */
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#define BFE_RXCONF_ALLMULTI 0x00000002 /* Accept All Multicast */
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#define BFE_RXCONF_NORXTX 0x00000004 /* Receive Disable While Transmitting */
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#define BFE_RXCONF_PROMISC 0x00000008 /* Promiscuous Enable */
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#define BFE_RXCONF_LPBACK 0x00000010 /* Loopback Enable */
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#define BFE_RXCONF_FLOW 0x00000020 /* Flow Control Enable */
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#define BFE_RXCONF_ACCEPT 0x00000040 /* Accept Unicast Flow Control Frame */
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#define BFE_RXCONF_RFILT 0x00000080 /* Reject Filter */
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#define BFE_RXMAXLEN 0x00000404 /* EMAC RX Max Packet Length */
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#define BFE_TXMAXLEN 0x00000408 /* EMAC TX Max Packet Length */
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#define BFE_MDIO_CTRL 0x00000410 /* EMAC MDIO Control */
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#define BFE_MDIO_MAXF_MASK 0x0000007f /* MDC Frequency */
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#define BFE_MDIO_PREAMBLE 0x00000080 /* MII Preamble Enable */
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#define BFE_MDIO_DATA 0x00000414 /* EMAC MDIO Data */
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#define BFE_MDIO_DATA_DATA 0x0000ffff /* R/W Data */
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#define BFE_MDIO_TA_MASK 0x00030000 /* Turnaround Value */
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#define BFE_MDIO_TA_SHIFT 16
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#define BFE_MDIO_TA_VALID 2
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#define BFE_MDIO_RA_MASK 0x007c0000 /* Register Address */
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#define BFE_MDIO_PMD_MASK 0x0f800000 /* Physical Media Device */
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#define BFE_MDIO_OP_MASK 0x30000000 /* Opcode */
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#define BFE_MDIO_SB_MASK 0xc0000000 /* Start Bits */
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#define BFE_MDIO_SB_START 0x40000000 /* Start Of Frame */
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#define BFE_MDIO_RA_SHIFT 18
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#define BFE_MDIO_PMD_SHIFT 23
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#define BFE_MDIO_OP_SHIFT 28
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#define BFE_MDIO_OP_WRITE 1
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#define BFE_MDIO_OP_READ 2
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#define BFE_MDIO_SB_SHIFT 30
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#define BFE_EMAC_IMASK 0x00000418 /* EMAC Interrupt Mask */
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#define BFE_EMAC_ISTAT 0x0000041C /* EMAC Interrupt Status */
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#define BFE_EMAC_INT_MII 0x00000001 /* MII MDIO Interrupt */
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#define BFE_EMAC_INT_MIB 0x00000002 /* MIB Interrupt */
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#define BFE_EMAC_INT_FLOW 0x00000003 /* Flow Control Interrupt */
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#define BFE_CAM_DATA_LO 0x00000420 /* EMAC CAM Data Low */
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#define BFE_CAM_DATA_HI 0x00000424 /* EMAC CAM Data High */
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#define BFE_CAM_HI_VALID 0x00010000 /* Valid Bit */
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#define BFE_CAM_CTRL 0x00000428 /* EMAC CAM Control */
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#define BFE_CAM_ENABLE 0x00000001 /* CAM Enable */
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#define BFE_CAM_MSEL 0x00000002 /* Mask Select */
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#define BFE_CAM_READ 0x00000004 /* Read */
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#define BFE_CAM_WRITE 0x00000008 /* Read */
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#define BFE_CAM_INDEX_MASK 0x003f0000 /* Index Mask */
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#define BFE_CAM_BUSY 0x80000000 /* CAM Busy */
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#define BFE_CAM_INDEX_SHIFT 16
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#define BFE_ENET_CTRL 0x0000042C /* EMAC ENET Control */
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#define BFE_ENET_ENABLE 0x00000001 /* EMAC Enable */
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#define BFE_ENET_DISABLE 0x00000002 /* EMAC Disable */
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#define BFE_ENET_SRST 0x00000004 /* EMAC Soft Reset */
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#define BFE_ENET_EPSEL 0x00000008 /* External PHY Select */
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#define BFE_TX_CTRL 0x00000430 /* EMAC TX Control */
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#define BFE_TX_DUPLEX 0x00000001 /* Full Duplex */
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#define BFE_TX_FMODE 0x00000002 /* Flow Mode */
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#define BFE_TX_SBENAB 0x00000004 /* Single Backoff Enable */
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#define BFE_TX_SMALL_SLOT 0x00000008 /* Small Slottime */
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#define BFE_TX_WMARK 0x00000434 /* EMAC TX Watermark */
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#define BFE_MIB_CTRL 0x00000438 /* EMAC MIB Control */
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#define BFE_MIB_CLR_ON_READ 0x00000001 /* Autoclear on Read */
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/* Status registers */
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#define BFE_TX_GOOD_O 0x00000500 /* MIB TX Good Octets */
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#define BFE_TX_GOOD_P 0x00000504 /* MIB TX Good Packets */
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#define BFE_TX_O 0x00000508 /* MIB TX Octets */
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#define BFE_TX_P 0x0000050C /* MIB TX Packets */
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#define BFE_TX_BCAST 0x00000510 /* MIB TX Broadcast Packets */
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#define BFE_TX_MCAST 0x00000514 /* MIB TX Multicast Packets */
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#define BFE_TX_64 0x00000518 /* MIB TX <= 64 byte Packets */
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#define BFE_TX_65_127 0x0000051C /* MIB TX 65 to 127 byte Packets */
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#define BFE_TX_128_255 0x00000520 /* MIB TX 128 to 255 byte Packets */
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#define BFE_TX_256_511 0x00000524 /* MIB TX 256 to 511 byte Packets */
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#define BFE_TX_512_1023 0x00000528 /* MIB TX 512 to 1023 byte Packets */
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#define BFE_TX_1024_MAX 0x0000052C /* MIB TX 1024 to max byte Packets */
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#define BFE_TX_JABBER 0x00000530 /* MIB TX Jabber Packets */
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#define BFE_TX_OSIZE 0x00000534 /* MIB TX Oversize Packets */
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#define BFE_TX_FRAG 0x00000538 /* MIB TX Fragment Packets */
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#define BFE_TX_URUNS 0x0000053C /* MIB TX Underruns */
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#define BFE_TX_TCOLS 0x00000540 /* MIB TX Total Collisions */
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#define BFE_TX_SCOLS 0x00000544 /* MIB TX Single Collisions */
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#define BFE_TX_MCOLS 0x00000548 /* MIB TX Multiple Collisions */
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#define BFE_TX_ECOLS 0x0000054C /* MIB TX Excessive Collisions */
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#define BFE_TX_LCOLS 0x00000550 /* MIB TX Late Collisions */
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#define BFE_TX_DEFERED 0x00000554 /* MIB TX Defered Packets */
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#define BFE_TX_CLOST 0x00000558 /* MIB TX Carrier Lost */
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#define BFE_TX_PAUSE 0x0000055C /* MIB TX Pause Packets */
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#define BFE_RX_GOOD_O 0x00000580 /* MIB RX Good Octets */
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#define BFE_RX_GOOD_P 0x00000584 /* MIB RX Good Packets */
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#define BFE_RX_O 0x00000588 /* MIB RX Octets */
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#define BFE_RX_P 0x0000058C /* MIB RX Packets */
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#define BFE_RX_BCAST 0x00000590 /* MIB RX Broadcast Packets */
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#define BFE_RX_MCAST 0x00000594 /* MIB RX Multicast Packets */
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#define BFE_RX_64 0x00000598 /* MIB RX <= 64 byte Packets */
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#define BFE_RX_65_127 0x0000059C /* MIB RX 65 to 127 byte Packets */
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#define BFE_RX_128_255 0x000005A0 /* MIB RX 128 to 255 byte Packets */
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#define BFE_RX_256_511 0x000005A4 /* MIB RX 256 to 511 byte Packets */
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#define BFE_RX_512_1023 0x000005A8 /* MIB RX 512 to 1023 byte Packets */
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#define BFE_RX_1024_MAX 0x000005AC /* MIB RX 1024 to max byte Packets */
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#define BFE_RX_JABBER 0x000005B0 /* MIB RX Jabber Packets */
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#define BFE_RX_OSIZE 0x000005B4 /* MIB RX Oversize Packets */
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#define BFE_RX_FRAG 0x000005B8 /* MIB RX Fragment Packets */
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#define BFE_RX_MISS 0x000005BC /* MIB RX Missed Packets */
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#define BFE_RX_CRCA 0x000005C0 /* MIB RX CRC Align Errors */
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#define BFE_RX_USIZE 0x000005C4 /* MIB RX Undersize Packets */
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#define BFE_RX_CRC 0x000005C8 /* MIB RX CRC Errors */
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#define BFE_RX_ALIGN 0x000005CC /* MIB RX Align Errors */
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#define BFE_RX_SYM 0x000005D0 /* MIB RX Symbol Errors */
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#define BFE_RX_PAUSE 0x000005D4 /* MIB RX Pause Packets */
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#define BFE_RX_NPAUSE 0x000005D8 /* MIB RX Non-Pause Packets */
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#define BFE_SBIMSTATE 0x00000F90 /* BFE_SB Initiator Agent State */
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#define BFE_PC 0x0000000f /* Pipe Count */
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#define BFE_AP_MASK 0x00000030 /* Arbitration Priority */
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#define BFE_AP_BOTH 0x00000000 /* Use both timeslices and token */
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#define BFE_AP_TS 0x00000010 /* Use timeslices only */
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#define BFE_AP_TK 0x00000020 /* Use token only */
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#define BFE_AP_RSV 0x00000030 /* Reserved */
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#define BFE_IBE 0x00020000 /* In Band Error */
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#define BFE_TO 0x00040000 /* Timeout */
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/* Seems the bcm440x has a fairly generic core, we only need be concerned with
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* a couple of these
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*/
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#define BFE_SBINTVEC 0x00000F94 /* BFE_SB Interrupt Mask */
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#define BFE_INTVEC_PCI 0x00000001 /* Enable interrupts for PCI */
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#define BFE_INTVEC_ENET0 0x00000002 /* Enable interrupts for enet 0 */
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#define BFE_INTVEC_ILINE20 0x00000004 /* Enable interrupts for iline20 */
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#define BFE_INTVEC_CODEC 0x00000008 /* Enable interrupts for v90 codec */
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#define BFE_INTVEC_USB 0x00000010 /* Enable interrupts for usb */
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#define BFE_INTVEC_EXTIF 0x00000020 /* Enable interrupts for external i/f */
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#define BFE_INTVEC_ENET1 0x00000040 /* Enable interrupts for enet 1 */
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#define BFE_SBTMSLOW 0x00000F98 /* BFE_SB Target State Low */
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#define BFE_RESET 0x00000001 /* Reset */
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#define BFE_REJECT 0x00000002 /* Reject */
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#define BFE_CLOCK 0x00010000 /* Clock Enable */
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#define BFE_FGC 0x00020000 /* Force Gated Clocks On */
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#define BFE_PE 0x40000000 /* Power Management Enable */
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#define BFE_BE 0x80000000 /* BIST Enable */
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#define BFE_SBTMSHIGH 0x00000F9C /* BFE_SB Target State High */
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#define BFE_SERR 0x00000001 /* S-error */
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#define BFE_INT 0x00000002 /* Interrupt */
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#define BFE_BUSY 0x00000004 /* Busy */
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#define BFE_GCR 0x20000000 /* Gated Clock Request */
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#define BFE_BISTF 0x40000000 /* BIST Failed */
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#define BFE_BISTD 0x80000000 /* BIST Done */
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#define BFE_SBBWA0 0x00000FA0 /* BFE_SB Bandwidth Allocation Table 0 */
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#define BFE_TAB0_MASK 0x0000ffff /* Lookup Table 0 */
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#define BFE_TAB1_MASK 0xffff0000 /* Lookup Table 0 */
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#define BFE_TAB0_SHIFT 0
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#define BFE_TAB1_SHIFT 16
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#define BFE_SBIMCFGLOW 0x00000FA8 /* BFE_SB Initiator Configuration Low */
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#define BFE_STO_MASK 0x00000003 /* Service Timeout */
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#define BFE_RTO_MASK 0x00000030 /* Request Timeout */
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#define BFE_CID_MASK 0x00ff0000 /* Connection ID */
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#define BFE_RTO_SHIFT 4
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#define BFE_CID_SHIFT 16
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#define BFE_SBIMCFGHIGH 0x00000FAC /* BFE_SB Initiator Configuration High */
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#define BFE_IEM_MASK 0x0000000c /* Inband Error Mode */
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#define BFE_TEM_MASK 0x00000030 /* Timeout Error Mode */
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#define BFE_BEM_MASK 0x000000c0 /* Bus Error Mode */
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#define BFE_TEM_SHIFT 4
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#define BFE_BEM_SHIFT 6
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#define BFE_SBTMCFGLOW 0x00000FB8 /* BFE_SB Target Configuration Low */
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#define BFE_LOW_CD_MASK 0x000000ff /* Clock Divide Mask */
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#define BFE_LOW_CO_MASK 0x0000f800 /* Clock Offset Mask */
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#define BFE_LOW_IF_MASK 0x00fc0000 /* Interrupt Flags Mask */
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#define BFE_LOW_IM_MASK 0x03000000 /* Interrupt Mode Mask */
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#define BFE_LOW_CO_SHIFT 11
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#define BFE_LOW_IF_SHIFT 18
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#define BFE_LOW_IM_SHIFT 24
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#define BFE_SBTMCFGHIGH 0x00000FBC /* BFE_SB Target Configuration High */
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#define BFE_HIGH_BM_MASK 0x00000003 /* Busy Mode */
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#define BFE_HIGH_RM_MASK 0x0000000C /* Retry Mode */
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#define BFE_HIGH_SM_MASK 0x00000030 /* Stop Mode */
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#define BFE_HIGH_EM_MASK 0x00000300 /* Error Mode */
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#define BFE_HIGH_IM_MASK 0x00000c00 /* Interrupt Mode */
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#define BFE_HIGH_RM_SHIFT 2
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#define BFE_HIGH_SM_SHIFT 4
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#define BFE_HIGH_EM_SHIFT 8
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#define BFE_HIGH_IM_SHIFT 10
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#define BFE_SBBCFG 0x00000FC0 /* BFE_SB Broadcast Configuration */
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#define BFE_LAT_MASK 0x00000003 /* BFE_SB Latency */
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#define BFE_MAX0_MASK 0x000f0000 /* MAX Counter 0 */
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#define BFE_MAX1_MASK 0x00f00000 /* MAX Counter 1 */
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#define BFE_MAX0_SHIFT 16
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#define BFE_MAX1_SHIFT 20
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#define BFE_SBBSTATE 0x00000FC8 /* BFE_SB Broadcast State */
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#define BFE_SBBSTATE_SRD 0x00000001 /* ST Reg Disable */
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#define BFE_SBBSTATE_HRD 0x00000002 /* Hold Reg Disable */
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#define BFE_SBACTCNFG 0x00000FD8 /* BFE_SB Activate Configuration */
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#define BFE_SBFLAGST 0x00000FE8 /* BFE_SB Current BFE_SBFLAGS */
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#define BFE_SBIDLOW 0x00000FF8 /* BFE_SB Identification Low */
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#define BFE_CS_MASK 0x00000003 /* Config Space Mask */
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#define BFE_AR_MASK 0x00000038 /* Num Address Ranges Supported */
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#define BFE_SYNCH 0x00000040 /* Sync */
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#define BFE_INIT 0x00000080 /* Initiator */
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#define BFE_MINLAT_MASK 0x00000f00 /* Minimum Backplane Latency */
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#define BFE_MAXLAT_MASK 0x0000f000 /* Maximum Backplane Latency */
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#define BFE_FIRST 0x00010000 /* This Initiator is First */
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#define BFE_CW_MASK 0x000c0000 /* Cycle Counter Width */
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#define BFE_TP_MASK 0x00f00000 /* Target Ports */
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#define BFE_IP_MASK 0x0f000000 /* Initiator Ports */
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#define BFE_AR_SHIFT 3
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#define BFE_MINLAT_SHIFT 8
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#define BFE_MAXLAT_SHIFT 12
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#define BFE_CW_SHIFT 18
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#define BFE_TP_SHIFT 20
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#define BFE_IP_SHIFT 24
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#define BFE_SBIDHIGH 0x00000FFC /* BFE_SB Identification High */
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#define BFE_RC_MASK 0x0000000f /* Revision Code */
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#define BFE_CC_MASK 0x0000fff0 /* Core Code */
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#define BFE_VC_MASK 0xffff0000 /* Vendor Code */
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#define BFE_CC_SHIFT 4
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#define BFE_VC_SHIFT 16
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#define BFE_CORE_ILINE20 0x801
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#define BFE_CORE_SDRAM 0x803
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#define BFE_CORE_PCI 0x804
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#define BFE_CORE_MIPS 0x805
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#define BFE_CORE_ENET 0x806
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#define BFE_CORE_CODEC 0x807
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#define BFE_CORE_USB 0x808
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#define BFE_CORE_ILINE100 0x80a
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#define BFE_CORE_EXTIF 0x811
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/* SSB PCI config space registers. */
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#define BFE_BAR0_WIN 0x80
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#define BFE_BAR1_WIN 0x84
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#define BFE_SPROM_CONTROL 0x88
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#define BFE_BAR1_CONTROL 0x8c
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/* SSB core and hsot control registers. */
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#define BFE_SSB_CONTROL 0x00000000
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#define BFE_SSB_ARBCONTROL 0x00000010
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#define BFE_SSB_ISTAT 0x00000020
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#define BFE_SSB_IMASK 0x00000024
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#define BFE_SSB_MBOX 0x00000028
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#define BFE_SSB_BCAST_ADDR 0x00000050
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#define BFE_SSB_BCAST_DATA 0x00000054
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#define BFE_SSB_PCI_TRANS_0 0x00000100
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#define BFE_SSB_PCI_TRANS_1 0x00000104
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#define BFE_SSB_PCI_TRANS_2 0x00000108
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#define BFE_SSB_SPROM 0x00000800
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#define BFE_SSB_PCI_MEM 0x00000000
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#define BFE_SSB_PCI_IO 0x00000001
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#define BFE_SSB_PCI_CFG0 0x00000002
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#define BFE_SSB_PCI_CFG1 0x00000003
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#define BFE_SSB_PCI_PREF 0x00000004
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#define BFE_SSB_PCI_BURST 0x00000008
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#define BFE_SSB_PCI_MASK0 0xfc000000
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#define BFE_SSB_PCI_MASK1 0xfc000000
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#define BFE_SSB_PCI_MASK2 0xc0000000
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#define BFE_DESC_LEN 0x00001fff
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#define BFE_DESC_CMASK 0x0ff00000 /* Core specific bits */
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#define BFE_DESC_EOT 0x10000000 /* End of Table */
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#define BFE_DESC_IOC 0x20000000 /* Interrupt On Completion */
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#define BFE_DESC_EOF 0x40000000 /* End of Frame */
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#define BFE_DESC_SOF 0x80000000 /* Start of Frame */
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#define BFE_RX_CP_THRESHOLD 256
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#define BFE_RX_HEADER_LEN 28
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#define BFE_RX_FLAG_OFIFO 0x00000001 /* FIFO Overflow */
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#define BFE_RX_FLAG_CRCERR 0x00000002 /* CRC Error */
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#define BFE_RX_FLAG_SERR 0x00000004 /* Receive Symbol Error */
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#define BFE_RX_FLAG_ODD 0x00000008 /* Frame has odd number of nibbles */
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#define BFE_RX_FLAG_LARGE 0x00000010 /* Frame is > RX MAX Length */
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#define BFE_RX_FLAG_MCAST 0x00000020 /* Dest is Multicast Address */
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#define BFE_RX_FLAG_BCAST 0x00000040 /* Dest is Broadcast Address */
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#define BFE_RX_FLAG_MISS 0x00000080 /* Received due to promisc mode */
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#define BFE_RX_FLAG_LAST 0x00000800 /* Last buffer in frame */
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#define BFE_RX_FLAG_ERRORS (BFE_RX_FLAG_ODD | BFE_RX_FLAG_SERR | \
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BFE_RX_FLAG_CRCERR | BFE_RX_FLAG_OFIFO)
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#define BFE_MCAST_TBL_SIZE 32
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#define BFE_PCI_DMA 0x40000000
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#define BFE_REG_PCI 0x18002000
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#define BCOM_VENDORID 0x14E4
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#define BCOM_DEVICEID_BCM4401 0x4401
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#define BCOM_DEVICEID_BCM4401B0 0x170c
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#define PCI_SETBIT(dev, reg, x, s) \
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pci_write_config(dev, reg, (pci_read_config(dev, reg, s) | (x)), s)
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#define PCI_CLRBIT(dev, reg, x, s) \
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pci_write_config(dev, reg, (pci_read_config(dev, reg, s) & ~(x)), s)
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#define BFE_TX_LIST_CNT 128
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#define BFE_RX_LIST_CNT 128
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#define BFE_TX_LIST_SIZE BFE_TX_LIST_CNT * sizeof(struct bfe_desc)
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#define BFE_RX_LIST_SIZE BFE_RX_LIST_CNT * sizeof(struct bfe_desc)
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#define BFE_RX_OFFSET 30
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#define BFE_TX_QLEN 256
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#define BFE_RX_RING_ALIGN 4096
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#define BFE_TX_RING_ALIGN 4096
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#define BFE_MAXTXSEGS 16
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#define BFE_DMA_MAXADDR 0x3FFFFFFF /* 1GB DMA address limit. */
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#define BFE_ADDR_LO(x) ((uint64_t)(x) & 0xFFFFFFFF)
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#define CSR_READ_4(sc, reg) bus_read_4(sc->bfe_res, reg)
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#define CSR_WRITE_4(sc, reg, val) bus_write_4(sc->bfe_res, reg, val)
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#define BFE_OR(sc, name, val) \
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CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) | val)
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#define BFE_AND(sc, name, val) \
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CSR_WRITE_4(sc, name, CSR_READ_4(sc, name) & val)
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#define BFE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->bfe_mtx, MA_OWNED)
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#define BFE_LOCK(_sc) mtx_lock(&(_sc)->bfe_mtx)
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#define BFE_UNLOCK(_sc) mtx_unlock(&(_sc)->bfe_mtx)
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#define BFE_INC(x, y) (x) = ((x) == ((y)-1)) ? 0 : (x)+1
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struct bfe_tx_data {
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struct mbuf *bfe_mbuf;
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bus_dmamap_t bfe_map;
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};
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struct bfe_rx_data {
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struct mbuf *bfe_mbuf;
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bus_dmamap_t bfe_map;
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u_int32_t bfe_ctrl;
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};
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struct bfe_desc {
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u_int32_t bfe_ctrl;
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u_int32_t bfe_addr;
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};
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struct bfe_rxheader {
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u_int16_t len;
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u_int16_t flags;
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u_int16_t pad[12];
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};
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#define MIB_TX_GOOD_O 0
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#define MIB_TX_GOOD_P 1
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#define MIB_TX_O 2
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#define MIB_TX_P 3
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#define MIB_TX_BCAST 4
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#define MIB_TX_MCAST 5
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#define MIB_TX_64 6
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#define MIB_TX_65_127 7
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#define MIB_TX_128_255 8
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#define MIB_TX_256_511 9
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#define MIB_TX_512_1023 10
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#define MIB_TX_1024_MAX 11
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#define MIB_TX_JABBER 12
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#define MIB_TX_OSIZE 13
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#define MIB_TX_FRAG 14
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#define MIB_TX_URUNS 15
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#define MIB_TX_TCOLS 16
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#define MIB_TX_SCOLS 17
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#define MIB_TX_MCOLS 18
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#define MIB_TX_ECOLS 19
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#define MIB_TX_LCOLS 20
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#define MIB_TX_DEFERED 21
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#define MIB_TX_CLOST 22
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#define MIB_TX_PAUSE 23
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#define MIB_RX_GOOD_O 24
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#define MIB_RX_GOOD_P 25
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#define MIB_RX_O 26
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#define MIB_RX_P 27
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#define MIB_RX_BCAST 28
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#define MIB_RX_MCAST 29
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#define MIB_RX_64 30
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#define MIB_RX_65_127 31
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#define MIB_RX_128_255 32
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#define MIB_RX_256_511 33
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#define MIB_RX_512_1023 34
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#define MIB_RX_1024_MAX 35
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#define MIB_RX_JABBER 36
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#define MIB_RX_OSIZE 37
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#define MIB_RX_FRAG 38
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#define MIB_RX_MISS 39
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#define MIB_RX_CRCA 40
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#define MIB_RX_USIZE 41
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#define MIB_RX_CRC 42
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#define MIB_RX_ALIGN 43
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#define MIB_RX_SYM 44
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#define MIB_RX_PAUSE 45
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#define MIB_RX_NPAUSE 46
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#define BFE_MIB_CNT (MIB_RX_NPAUSE - MIB_TX_GOOD_O + 1)
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struct bfe_hw_stats {
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uint64_t tx_good_octets;
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uint64_t tx_good_frames;
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uint64_t tx_octets;
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uint64_t tx_frames;
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uint64_t tx_bcast_frames;
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uint64_t tx_mcast_frames;
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uint64_t tx_pkts_64;
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uint64_t tx_pkts_65_127;
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uint64_t tx_pkts_128_255;
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uint64_t tx_pkts_256_511;
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uint64_t tx_pkts_512_1023;
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uint64_t tx_pkts_1024_max;
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uint32_t tx_jabbers;
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uint64_t tx_oversize_frames;
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uint64_t tx_frag_frames;
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uint32_t tx_underruns;
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uint32_t tx_colls;
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uint32_t tx_single_colls;
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uint32_t tx_multi_colls;
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uint32_t tx_excess_colls;
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uint32_t tx_late_colls;
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uint32_t tx_deferrals;
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uint32_t tx_carrier_losts;
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uint32_t tx_pause_frames;
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uint64_t rx_good_octets;
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uint64_t rx_good_frames;
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uint64_t rx_octets;
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uint64_t rx_frames;
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uint64_t rx_bcast_frames;
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uint64_t rx_mcast_frames;
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uint64_t rx_pkts_64;
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uint64_t rx_pkts_65_127;
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uint64_t rx_pkts_128_255;
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uint64_t rx_pkts_256_511;
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uint64_t rx_pkts_512_1023;
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uint64_t rx_pkts_1024_max;
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uint32_t rx_jabbers;
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uint64_t rx_oversize_frames;
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uint64_t rx_frag_frames;
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uint32_t rx_missed_frames;
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uint32_t rx_crc_align_errs;
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uint32_t rx_runts;
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uint32_t rx_crc_errs;
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uint32_t rx_align_errs;
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uint32_t rx_symbol_errs;
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uint32_t rx_pause_frames;
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uint32_t rx_control_frames;
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};
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struct bfe_softc
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{
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if_t bfe_ifp; /* interface info */
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device_t bfe_dev;
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device_t bfe_miibus;
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bus_dma_tag_t bfe_tag;
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bus_dma_tag_t bfe_parent_tag;
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bus_dma_tag_t bfe_tx_tag, bfe_rx_tag;
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bus_dmamap_t bfe_tx_map, bfe_rx_map;
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bus_dma_tag_t bfe_txmbuf_tag, bfe_rxmbuf_tag;
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bus_dmamap_t bfe_rx_sparemap;
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void *bfe_intrhand;
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struct resource *bfe_irq;
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|
struct resource *bfe_res;
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|
struct callout bfe_stat_co;
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|
struct bfe_hw_stats bfe_stats;
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|
struct bfe_desc *bfe_tx_list, *bfe_rx_list;
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|
struct bfe_tx_data bfe_tx_ring[BFE_TX_LIST_CNT]; /* XXX */
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|
struct bfe_rx_data bfe_rx_ring[BFE_RX_LIST_CNT]; /* XXX */
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|
struct mtx bfe_mtx;
|
|
u_int32_t bfe_flags;
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|
#define BFE_FLAG_DETACH 0x4000
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|
#define BFE_FLAG_LINK 0x8000
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u_int32_t bfe_imask;
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|
u_int32_t bfe_dma_offset;
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|
u_int32_t bfe_tx_cnt, bfe_tx_cons, bfe_tx_prod;
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u_int32_t bfe_rx_prod, bfe_rx_cons;
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u_int32_t bfe_tx_dma, bfe_rx_dma;
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int bfe_watchdog_timer;
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|
u_int8_t bfe_phyaddr; /* Address of the card's PHY */
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|
u_int8_t bfe_mdc_port;
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|
u_int8_t bfe_core_unit;
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|
u_char bfe_enaddr[6];
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|
int bfe_if_flags;
|
|
};
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|
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struct bfe_type
|
|
{
|
|
u_int16_t bfe_vid;
|
|
u_int16_t bfe_did;
|
|
char *bfe_name;
|
|
};
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#endif /* _BFE_H */
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