e388de98bd
Summary: This switch is based off of the AR8327/AR8337 external switch/PHY. However unlike the AR8327/AR8337 it itself doesn't have any PHYs; instead an external PHY connects to it using the PSGMII port. Differential Revision: https://reviews.freebsd.org/D34112 Reviewed by: manu This code is inspired by the ar40xx code in openwrt, which itself is based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly, BSD licenced - and thus I have included some of the comments in the hardware workaround paths to document some of the magic numbers.
358 lines
9.3 KiB
C
358 lines
9.3 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/ar40xx/ar40xx_var.h>
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#include <dev/etherswitch/ar40xx/ar40xx_reg.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw.h>
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#include <dev/etherswitch/ar40xx/ar40xx_debug.h>
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/*
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* XXX these are here for now; move the code using these
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* into main.c once this is all done!
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*/
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#include <dev/etherswitch/ar40xx/ar40xx_hw_vtu.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_port.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_mirror.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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/*
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* Reset the ESS switch. This also resets the ESS ethernet
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* and PSGMII block.
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*/
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int
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ar40xx_hw_ess_reset(struct ar40xx_softc *sc)
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{
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int ret;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_RESET, "%s: called\n", __func__);
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ret = hwreset_assert(sc->sc_ess_rst);
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if (ret != 0) {
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device_printf(sc->sc_dev, "ERROR: failed to assert reset\n");
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return ret;
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}
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DELAY(10*1000);
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ret = hwreset_deassert(sc->sc_ess_rst);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: failed to deassert reset\n");
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return ret;
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}
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DELAY(10*1000);
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return (0);
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}
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int
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ar40xx_hw_init_globals(struct ar40xx_softc *sc)
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{
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uint32_t reg;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_INIT, "%s: called\n", __func__);
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/* enable CPU port and disable mirror port */
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reg = AR40XX_FWD_CTRL0_CPU_PORT_EN
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| AR40XX_FWD_CTRL0_MIRROR_PORT;
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AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL0, reg);
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/* forward multicast and broadcast frames to CPU */
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reg = (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_UC_FLOOD_S)
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| (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_MC_FLOOD_S)
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| (AR40XX_PORTS_ALL << AR40XX_FWD_CTRL1_BC_FLOOD_S);
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AR40XX_REG_WRITE(sc, AR40XX_REG_FWD_CTRL1, reg);
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/* enable jumbo frames */
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reg = AR40XX_REG_READ(sc, AR40XX_REG_MAX_FRAME_SIZE);
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reg &= ~AR40XX_MAX_FRAME_SIZE_MTU;
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reg |= 9018 + 8 + 2;
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AR40XX_REG_WRITE(sc, AR40XX_REG_MAX_FRAME_SIZE, reg);
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/* Enable MIB counters */
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reg = AR40XX_REG_READ(sc, AR40XX_REG_MODULE_EN);
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reg |= AR40XX_MODULE_EN_MIB;
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AR40XX_REG_WRITE(sc, AR40XX_REG_MODULE_EN, reg);
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/* Disable AZ */
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AR40XX_REG_WRITE(sc, AR40XX_REG_EEE_CTRL, 0);
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/* set flowctrl thershold for cpu port */
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reg = (AR40XX_PORT0_FC_THRESH_ON_DFLT << 16)
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| AR40XX_PORT0_FC_THRESH_OFF_DFLT;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_FLOWCTRL_THRESH(0), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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int
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ar40xx_hw_vlan_init(struct ar40xx_softc *sc)
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{
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int i;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_INIT, "%s: called\n", __func__);
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/* Enable VLANs by default */
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sc->sc_vlan.vlan = 1;
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/* Configure initial LAN/WAN bitmap and include CPU port as tagged */
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sc->sc_vlan.vlan_id[AR40XX_LAN_VLAN] = AR40XX_LAN_VLAN
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| ETHERSWITCH_VID_VALID;
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sc->sc_vlan.vlan_id[AR40XX_WAN_VLAN] = AR40XX_WAN_VLAN
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| ETHERSWITCH_VID_VALID;
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sc->sc_vlan.vlan_ports[AR40XX_LAN_VLAN] =
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sc->sc_config.switch_cpu_bmp | sc->sc_config.switch_lan_bmp;
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sc->sc_vlan.vlan_untagged[AR40XX_LAN_VLAN] =
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sc->sc_config.switch_lan_bmp;
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sc->sc_vlan.vlan_ports[AR40XX_WAN_VLAN] =
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sc->sc_config.switch_cpu_bmp | sc->sc_config.switch_wan_bmp;
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sc->sc_vlan.vlan_untagged[AR40XX_WAN_VLAN] =
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sc->sc_config.switch_wan_bmp;
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/* Populate the per-port PVID - pvid[] is an index into vlan_id[] */
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for (i = 0; i < AR40XX_NUM_PORTS; i++) {
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if (sc->sc_config.switch_lan_bmp & (1U << i))
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sc->sc_vlan.pvid[i] = AR40XX_LAN_VLAN;
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if (sc->sc_config.switch_wan_bmp & (1U << i))
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sc->sc_vlan.pvid[i] = AR40XX_WAN_VLAN;
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}
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return (0);
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}
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/*
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* Apply the per-port and global configuration from software.
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*
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* This is useful if we ever start doing the linux switch framework
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* thing of updating the config in one hit and pushing it to the
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* hardware. For now it's just used in the reset path.
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*/
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int
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ar40xx_hw_sw_hw_apply(struct ar40xx_softc *sc)
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{
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uint8_t portmask[AR40XX_NUM_PORTS];
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int i, j, ret;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_INIT, "%s: called\n", __func__);
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/*
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* Flush the VTU configuration.
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*/
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ret = ar40xx_hw_vtu_flush(sc);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: couldn't apply config; vtu flush failed (%d)\n",
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ret);
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return (ret);
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}
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memset(portmask, 0, sizeof(portmask));
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/*
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* Configure the ports based on whether it's 802.1q
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* VLANs, or just straight up per-port VLANs.
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*/
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if (sc->sc_vlan.vlan) {
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device_printf(sc->sc_dev, "%s: configuring 802.1q VLANs\n",
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__func__);
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for (j = 0; j < AR40XX_NUM_VTU_ENTRIES; j++) {
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uint8_t vp = sc->sc_vlan.vlan_ports[j];
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if (!vp)
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continue;
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if ((sc->sc_vlan.vlan_id[j]
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& ETHERSWITCH_VID_VALID) == 0)
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continue;
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for (i = 0; i < AR40XX_NUM_PORTS; i++) {
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uint8_t mask = (1U << i);
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if (vp & mask)
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portmask[i] |= vp & ~mask;
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}
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ar40xx_hw_vtu_load_vlan(sc,
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sc->sc_vlan.vlan_id[j] & ETHERSWITCH_VID_MASK,
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sc->sc_vlan.vlan_ports[j],
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sc->sc_vlan.vlan_untagged[j]);
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}
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} else {
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device_printf(sc->sc_dev, "%s: configuring per-port VLANs\n",
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__func__);
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for (i = 0; i < AR40XX_NUM_PORTS; i++) {
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if (i == AR40XX_PORT_CPU)
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continue;
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portmask[i] = (1U << AR40XX_PORT_CPU);
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portmask[AR40XX_PORT_CPU] |= (1U << i);
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}
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}
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/*
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* Update per-port destination mask, vlan tag settings
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*/
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for (i = 0; i < AR40XX_NUM_PORTS; i++)
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(void) ar40xx_hw_port_setup(sc, i, portmask[i]);
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/* Set the mirror register config */
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ret = ar40xx_hw_mirror_set_registers(sc);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"ERROR: couldn't apply config; mirror config failed"
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" (%d)\n",
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ret);
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return (ret);
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}
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return (0);
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}
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int
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ar40xx_hw_wait_bit(struct ar40xx_softc *sc, int reg, uint32_t mask,
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uint32_t val)
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{
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int timeout = 20;
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uint32_t t;
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while (true) {
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AR40XX_REG_BARRIER_READ(sc);
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t = AR40XX_REG_READ(sc, reg);
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if ((t & mask) == val)
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return 0;
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if (timeout-- <= 0)
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break;
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DELAY(20);
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}
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device_printf(sc->sc_dev, "ERROR: timeout for reg "
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"%08x: %08x & %08x != %08x\n",
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(unsigned int)reg, t, mask, val);
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return (ETIMEDOUT);
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}
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/*
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* Read the switch MAC address.
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*/
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int
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ar40xx_hw_read_switch_mac_address(struct ar40xx_softc *sc,
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struct ether_addr *ea)
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{
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uint32_t ret0, ret1;
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char *s;
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s = (void *) ea;
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AR40XX_LOCK_ASSERT(sc);
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AR40XX_REG_BARRIER_READ(sc);
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ret0 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR0);
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ret1 = AR40XX_REG_READ(sc, AR40XX_REG_SW_MAC_ADDR1);
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s[5] = MS(ret0, AR40XX_REG_SW_MAC_ADDR0_BYTE5);
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s[4] = MS(ret0, AR40XX_REG_SW_MAC_ADDR0_BYTE4);
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s[3] = MS(ret1, AR40XX_REG_SW_MAC_ADDR1_BYTE3);
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s[2] = MS(ret1, AR40XX_REG_SW_MAC_ADDR1_BYTE2);
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s[1] = MS(ret1, AR40XX_REG_SW_MAC_ADDR1_BYTE1);
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s[0] = MS(ret1, AR40XX_REG_SW_MAC_ADDR1_BYTE0);
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return (0);
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}
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/*
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* Set the switch MAC address.
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*/
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int
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ar40xx_hw_write_switch_mac_address(struct ar40xx_softc *sc,
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struct ether_addr *ea)
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{
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uint32_t ret0 = 0, ret1 = 0;
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char *s;
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s = (void *) ea;
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AR40XX_LOCK_ASSERT(sc);
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ret0 |= SM(s[5], AR40XX_REG_SW_MAC_ADDR0_BYTE5);
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ret0 |= SM(s[4], AR40XX_REG_SW_MAC_ADDR0_BYTE4);
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ret1 |= SM(s[3], AR40XX_REG_SW_MAC_ADDR1_BYTE3);
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ret1 |= SM(s[2], AR40XX_REG_SW_MAC_ADDR1_BYTE2);
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ret1 |= SM(s[1], AR40XX_REG_SW_MAC_ADDR1_BYTE1);
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ret1 |= SM(s[0], AR40XX_REG_SW_MAC_ADDR1_BYTE0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR0, ret0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_SW_MAC_ADDR1, ret1);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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