e388de98bd
Summary: This switch is based off of the AR8327/AR8337 external switch/PHY. However unlike the AR8327/AR8337 it itself doesn't have any PHYs; instead an external PHY connects to it using the PSGMII port. Differential Revision: https://reviews.freebsd.org/D34112 Reviewed by: manu This code is inspired by the ar40xx code in openwrt, which itself is based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly, BSD licenced - and thus I have included some of the comments in the hardware workaround paths to document some of the magic numbers.
217 lines
5.9 KiB
C
217 lines
5.9 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/ar40xx/ar40xx_var.h>
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#include <dev/etherswitch/ar40xx/ar40xx_reg.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_atu.h>
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#include <dev/etherswitch/ar40xx/ar40xx_debug.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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int
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ar40xx_hw_atu_wait_busy(struct ar40xx_softc *sc)
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{
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int ret;
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ret = ar40xx_hw_wait_bit(sc, AR40XX_REG_ATU_FUNC,
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AR40XX_ATU_FUNC_BUSY, 0);
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return (ret);
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}
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int
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ar40xx_hw_atu_flush_all(struct ar40xx_softc *sc)
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{
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int ret;
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AR40XX_LOCK_ASSERT(sc);
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AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP, "%s: called\n", __func__);
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ret = ar40xx_hw_atu_wait_busy(sc);
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if (ret != 0)
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return (ret);
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
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AR40XX_ATU_FUNC_OP_FLUSH
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| AR40XX_ATU_FUNC_BUSY);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (ret);
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}
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int
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ar40xx_hw_atu_flush_port(struct ar40xx_softc *sc, int port)
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{
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uint32_t val;
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int ret;
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AR40XX_LOCK_ASSERT(sc);
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AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP, "%s: called, port=%d\n",
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__func__, port);
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if (port >= AR40XX_NUM_PORTS) {
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return (EINVAL);
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}
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ret = ar40xx_hw_atu_wait_busy(sc);
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if (ret != 0)
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return (ret);
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val = AR40XX_ATU_FUNC_OP_FLUSH_UNICAST;
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val |= (port << AR40XX_ATU_FUNC_PORT_NUM_S)
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& AR40XX_ATU_FUNC_PORT_NUM;
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
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val | AR40XX_ATU_FUNC_BUSY);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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int
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ar40xx_hw_atu_fetch_entry(struct ar40xx_softc *sc, etherswitch_atu_entry_t *e,
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int atu_fetch_op)
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{
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uint32_t ret0, ret1, ret2, val;
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int ret;
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AR40XX_LOCK_ASSERT(sc);
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switch (atu_fetch_op) {
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case 0:
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/* Initialise things for the first fetch */
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AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
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"%s: initializing\n", __func__);
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ret = ar40xx_hw_atu_wait_busy(sc);
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if (ret != 0)
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return (ret);
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC,
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AR40XX_ATU_FUNC_OP_GET_NEXT);
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA0, 0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA1, 0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_DATA2, 0);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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case 1:
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AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
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"%s: reading next\n", __func__);
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/*
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* Attempt to read the next address entry; don't modify what
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* is there in these registers as its used for the next fetch
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*/
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ret = ar40xx_hw_atu_wait_busy(sc);
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if (ret != 0)
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return (ret);
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/* Begin the next read event; not modifying anything */
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AR40XX_REG_BARRIER_READ(sc);
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val = AR40XX_REG_READ(sc, AR40XX_REG_ATU_FUNC);
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val |= AR40XX_ATU_FUNC_BUSY;
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AR40XX_REG_WRITE(sc, AR40XX_REG_ATU_FUNC, val);
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AR40XX_REG_BARRIER_WRITE(sc);
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/* Wait for it to complete */
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ret = ar40xx_hw_atu_wait_busy(sc);
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if (ret != 0)
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return (ret);
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/* Fetch the ethernet address and ATU status */
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AR40XX_REG_BARRIER_READ(sc);
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ret0 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA0);
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ret1 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA1);
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ret2 = AR40XX_REG_READ(sc, AR40XX_REG_ATU_DATA2);
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/* If the status is zero, then we're done */
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if (MS(ret2, AR40XX_ATU_FUNC_DATA2_STATUS) == 0)
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return (ENOENT);
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/* MAC address */
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e->es_macaddr[5] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR3);
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e->es_macaddr[4] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR2);
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e->es_macaddr[3] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR1);
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e->es_macaddr[2] = MS(ret0, AR40XX_ATU_DATA0_MAC_ADDR0);
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e->es_macaddr[0] = MS(ret1, AR40XX_ATU_DATA1_MAC_ADDR5);
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e->es_macaddr[1] = MS(ret1, AR40XX_ATU_DATA1_MAC_ADDR4);
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/* Bitmask of ports this entry is for */
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e->es_portmask = MS(ret1, AR40XX_ATU_DATA1_DEST_PORT);
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/* TODO: other flags that are interesting */
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AR40XX_DPRINTF(sc, AR40XX_DBG_ATU_OP,
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"%s: MAC %6D portmask 0x%08x\n",
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__func__,
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e->es_macaddr, ":", e->es_portmask);
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return (0);
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default:
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return (EINVAL);
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}
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return (EINVAL);
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}
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