e388de98bd
Summary: This switch is based off of the AR8327/AR8337 external switch/PHY. However unlike the AR8327/AR8337 it itself doesn't have any PHYs; instead an external PHY connects to it using the PSGMII port. Differential Revision: https://reviews.freebsd.org/D34112 Reviewed by: manu This code is inspired by the ar40xx code in openwrt, which itself is based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly, BSD licenced - and thus I have included some of the comments in the hardware workaround paths to document some of the magic numbers.
195 lines
6.0 KiB
C
195 lines
6.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/ar40xx/ar40xx_var.h>
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#include <dev/etherswitch/ar40xx/ar40xx_reg.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_mib.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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#define MIB_DESC(_s , _o, _n) \
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{ \
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.size = (_s), \
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.offset = (_o), \
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.name = (_n), \
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}
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static const struct ar40xx_mib_desc ar40xx_mibs[] = {
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MIB_DESC(1, AR40XX_STATS_RXBROAD, "RxBroad"),
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MIB_DESC(1, AR40XX_STATS_RXPAUSE, "RxPause"),
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MIB_DESC(1, AR40XX_STATS_RXMULTI, "RxMulti"),
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MIB_DESC(1, AR40XX_STATS_RXFCSERR, "RxFcsErr"),
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MIB_DESC(1, AR40XX_STATS_RXALIGNERR, "RxAlignErr"),
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MIB_DESC(1, AR40XX_STATS_RXRUNT, "RxRunt"),
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MIB_DESC(1, AR40XX_STATS_RXFRAGMENT, "RxFragment"),
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MIB_DESC(1, AR40XX_STATS_RX64BYTE, "Rx64Byte"),
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MIB_DESC(1, AR40XX_STATS_RX128BYTE, "Rx128Byte"),
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MIB_DESC(1, AR40XX_STATS_RX256BYTE, "Rx256Byte"),
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MIB_DESC(1, AR40XX_STATS_RX512BYTE, "Rx512Byte"),
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MIB_DESC(1, AR40XX_STATS_RX1024BYTE, "Rx1024Byte"),
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MIB_DESC(1, AR40XX_STATS_RX1518BYTE, "Rx1518Byte"),
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MIB_DESC(1, AR40XX_STATS_RXMAXBYTE, "RxMaxByte"),
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MIB_DESC(1, AR40XX_STATS_RXTOOLONG, "RxTooLong"),
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MIB_DESC(2, AR40XX_STATS_RXGOODBYTE, "RxGoodByte"),
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MIB_DESC(2, AR40XX_STATS_RXBADBYTE, "RxBadByte"),
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MIB_DESC(1, AR40XX_STATS_RXOVERFLOW, "RxOverFlow"),
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MIB_DESC(1, AR40XX_STATS_FILTERED, "Filtered"),
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MIB_DESC(1, AR40XX_STATS_TXBROAD, "TxBroad"),
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MIB_DESC(1, AR40XX_STATS_TXPAUSE, "TxPause"),
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MIB_DESC(1, AR40XX_STATS_TXMULTI, "TxMulti"),
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MIB_DESC(1, AR40XX_STATS_TXUNDERRUN, "TxUnderRun"),
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MIB_DESC(1, AR40XX_STATS_TX64BYTE, "Tx64Byte"),
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MIB_DESC(1, AR40XX_STATS_TX128BYTE, "Tx128Byte"),
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MIB_DESC(1, AR40XX_STATS_TX256BYTE, "Tx256Byte"),
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MIB_DESC(1, AR40XX_STATS_TX512BYTE, "Tx512Byte"),
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MIB_DESC(1, AR40XX_STATS_TX1024BYTE, "Tx1024Byte"),
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MIB_DESC(1, AR40XX_STATS_TX1518BYTE, "Tx1518Byte"),
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MIB_DESC(1, AR40XX_STATS_TXMAXBYTE, "TxMaxByte"),
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MIB_DESC(1, AR40XX_STATS_TXOVERSIZE, "TxOverSize"),
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MIB_DESC(2, AR40XX_STATS_TXBYTE, "TxByte"),
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MIB_DESC(1, AR40XX_STATS_TXCOLLISION, "TxCollision"),
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MIB_DESC(1, AR40XX_STATS_TXABORTCOL, "TxAbortCol"),
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MIB_DESC(1, AR40XX_STATS_TXMULTICOL, "TxMultiCol"),
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MIB_DESC(1, AR40XX_STATS_TXSINGLECOL, "TxSingleCol"),
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MIB_DESC(1, AR40XX_STATS_TXEXCDEFER, "TxExcDefer"),
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MIB_DESC(1, AR40XX_STATS_TXDEFER, "TxDefer"),
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MIB_DESC(1, AR40XX_STATS_TXLATECOL, "TxLateCol"),
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};
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int
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ar40xx_hw_mib_op(struct ar40xx_softc *sc, uint32_t op)
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{
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uint32_t reg;
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int ret;
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AR40XX_LOCK_ASSERT(sc);
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/* Trigger capturing statistics on all ports */
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AR40XX_REG_BARRIER_READ(sc);
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reg = AR40XX_REG_READ(sc, AR40XX_REG_MIB_FUNC);
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reg &= ~AR40XX_MIB_FUNC;
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reg |= (op << AR40XX_MIB_FUNC_S);
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AR40XX_REG_WRITE(sc, AR40XX_REG_MIB_FUNC, reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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/* Now wait */
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ret = ar40xx_hw_wait_bit(sc, AR40XX_REG_MIB_FUNC,
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AR40XX_MIB_BUSY, 0);
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if (ret != 0) {
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device_printf(sc->sc_dev,
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"%s: ERROR: timeout waiting for MIB load\n",
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__func__);
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}
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return ret;
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}
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int
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ar40xx_hw_mib_capture(struct ar40xx_softc *sc)
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{
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int ret;
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ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_CAPTURE);
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return (ret);
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}
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int
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ar40xx_hw_mib_flush(struct ar40xx_softc *sc)
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{
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int ret;
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ret = ar40xx_hw_mib_op(sc, AR40XX_MIB_FUNC_FLUSH);
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return (ret);
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}
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int
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ar40xx_hw_mib_fetch(struct ar40xx_softc *sc, int port)
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{
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uint64_t val;
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uint32_t base, reg;
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int i;
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base = AR40XX_REG_PORT_STATS_START
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+ (AR40XX_REG_PORT_STATS_LEN * port);
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/* For now just print them out, we'll store them later */
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AR40XX_REG_BARRIER_READ(sc);
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for (i = 0; i < nitems(ar40xx_mibs); i++) {
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val = 0;
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val = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset);
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if (ar40xx_mibs[i].size == 2) {
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reg = AR40XX_REG_READ(sc, base + ar40xx_mibs[i].offset + 4);
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val |= ((uint64_t) reg << 32);
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}
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device_printf(sc->sc_dev, "%s[%d] = %llu\n", ar40xx_mibs[i].name, port, val);
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}
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return (0);
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}
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