e388de98bd
Summary: This switch is based off of the AR8327/AR8337 external switch/PHY. However unlike the AR8327/AR8337 it itself doesn't have any PHYs; instead an external PHY connects to it using the PSGMII port. Differential Revision: https://reviews.freebsd.org/D34112 Reviewed by: manu This code is inspired by the ar40xx code in openwrt, which itself is based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly, BSD licenced - and thus I have included some of the comments in the hardware workaround paths to document some of the magic numbers.
288 lines
8.0 KiB
C
288 lines
8.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/ar40xx/ar40xx_var.h>
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#include <dev/etherswitch/ar40xx/ar40xx_reg.h>
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#include <dev/etherswitch/ar40xx/ar40xx_debug.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_port.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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int
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ar40xx_hw_port_init(struct ar40xx_softc *sc, int port)
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{
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uint32_t reg;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_PORT_INIT,
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"%s: called; port %d\n", __func__, port);
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_HEADER(port), 0);
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), 0);
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AR40XX_REG_BARRIER_WRITE(sc);
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DELAY(20);
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/*
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* Ok! Here is where things get super fun in the AR40xx
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* driver in uboot/linux.
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*
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* The earlier chipset switch drivers enable auto link enable here.
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* The switch will poll the PHYs too, and configure appropriately.
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*
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* The ar40xx code in linux/u-boot instead has a whole workaround
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* path that polls things directly and does some weird hijinx.
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* NOTABLY - they do NOT enable the TX/RX MAC here or autoneg -
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* it's done in the work around path.
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*
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* SO - for now the port is left off until the PHY state changes.
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* And then we flip it on and off based on the PHY state.
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*/
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#if 0
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port),
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AR40XX_PORT_AUTO_LINK_EN);
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#endif
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/*
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* Configure the VLAN egress mode (don't touch them) and
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* learning state for STP/ATU. This isn't currently
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* configurable so it's just nailed up here and left alone.
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*/
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reg = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH
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<< AR40XX_PORT_VLAN1_OUT_MODE_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);
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reg = AR40XX_PORT_LOOKUP_LEARN;
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reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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/*
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* Call when the link for a non-CPU port is down.
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*
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* This will turn off the MAC/forwarding path for this port.
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*/
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int
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ar40xx_hw_port_link_down(struct ar40xx_softc *sc, int port)
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{
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_PORT_INIT,
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"%s: called; port %d\n", __func__, port);
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), 0);
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return (0);
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}
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/*
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* Call when the link for a non-CPU port is up.
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*
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* This will turn on the default auto-link checking and
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* eventually enable the TX/RX MAC.
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*/
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int
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ar40xx_hw_port_link_up(struct ar40xx_softc *sc, int port)
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{
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uint32_t reg;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_PORT_INIT,
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"%s: called; port %d\n", __func__, port);
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/* Auto-link enable */
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AR40XX_REG_BARRIER_READ(sc);
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reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_STATUS(port));
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reg |= AR40XX_PORT_AUTO_LINK_EN;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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/*
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* Setup the CPU facing port. For this device it'll only
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* be port 0.
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*/
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int
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ar40xx_hw_port_cpuport_setup(struct ar40xx_softc *sc)
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{
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uint32_t reg;
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AR40XX_DPRINTF(sc, AR40XX_DBG_HW_PORT_INIT, "%s: called\n",
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__func__);
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reg = AR40XX_PORT_STATUS_TXFLOW
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| AR40XX_PORT_STATUS_RXFLOW
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| AR40XX_PORT_TXHALF_FLOW
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| AR40XX_PORT_DUPLEX
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| AR40XX_PORT_SPEED_1000M;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);
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DELAY(20);
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reg |= AR40XX_PORT_TX_EN | AR40XX_PORT_RX_EN;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_STATUS(0), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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/*
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* Fetch the port PVID.
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*
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* For 802.1q mode this is the default VLAN ID for the port.
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* Frames without an 802.1q VLAN will assume this VLAN ID for
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* transmit/receive.
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*/
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int
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ar40xx_hw_get_port_pvid(struct ar40xx_softc *sc, int port, int *pvid)
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{
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uint32_t reg;
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AR40XX_LOCK_ASSERT(sc);
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AR40XX_REG_BARRIER_READ(sc);
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reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_VLAN0(port));
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reg = reg >> AR40XX_PORT_VLAN0_DEF_CVID_S;
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reg = reg & 0x0fff; /* XXX */
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*pvid = reg;
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return (0);
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}
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/*
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* Set the port PVID.
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*
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* For now, since double-tagged frames aren't currently supported,
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* CVID=SVID here.
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*/
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int
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ar40xx_hw_set_port_pvid(struct ar40xx_softc *sc, int port, int pvid)
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{
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uint32_t reg;
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AR40XX_LOCK_ASSERT(sc);
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pvid &= ETHERSWITCH_VID_MASK;
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reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
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reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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/*
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* Setup the default port membership configuration.
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*
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* This configures the PVID for the port in the sc_vlan config,
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* along with a set of ports that constitute the "membership"
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* of this particular VID.
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*
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* For 802.1q mode the membership can be viewed as the default
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* learning port group, but this can be added to via VLAN membership.
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* (Eg you could in theory split two LAN ports into separate "member"
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* groups and they'd not learn MAC addresses from each other even
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* inside a VLAN; you'd then end up with the traffic being flooded to
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* the CPU port.)
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*/
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int
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ar40xx_hw_port_setup(struct ar40xx_softc *sc, int port, uint32_t members)
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{
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uint32_t egress, ingress, reg;
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uint32_t pvid = sc->sc_vlan.vlan_id[sc->sc_vlan.pvid[port]]
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& ETHERSWITCH_VID_MASK;
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if (sc->sc_vlan.vlan) {
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egress = AR40XX_PORT_VLAN1_OUT_MODE_UNMOD;
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ingress = AR40XX_IN_SECURE;
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} else {
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egress = AR40XX_PORT_VLAN1_OUT_MODE_UNTOUCH;
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ingress = AR40XX_IN_PORT_ONLY;
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}
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reg = pvid << AR40XX_PORT_VLAN0_DEF_SVID_S;
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reg |= pvid << AR40XX_PORT_VLAN0_DEF_CVID_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN0(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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reg = AR40XX_PORT_VLAN1_PORT_VLAN_PROP;
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reg |= egress << AR40XX_PORT_VLAN1_OUT_MODE_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_VLAN1(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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reg = members;
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reg |= AR40XX_PORT_LOOKUP_LEARN;
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reg |= ingress << AR40XX_PORT_LOOKUP_IN_MODE_S;
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reg |= AR40XX_PORT_STATE_FORWARD << AR40XX_PORT_LOOKUP_STATE_S;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(port), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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return (0);
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}
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