e388de98bd
Summary: This switch is based off of the AR8327/AR8337 external switch/PHY. However unlike the AR8327/AR8337 it itself doesn't have any PHYs; instead an external PHY connects to it using the PSGMII port. Differential Revision: https://reviews.freebsd.org/D34112 Reviewed by: manu This code is inspired by the ar40xx code in openwrt, which itself is based on the Qualcomm QCA-SSDK. Both of these sources are, amusingly, BSD licenced - and thus I have included some of the comments in the hardware workaround paths to document some of the magic numbers.
438 lines
12 KiB
C
438 lines
12 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2022 Adrian Chadd <adrian@FreeBSD.org>.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_var.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/ar40xx/ar40xx_var.h>
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#include <dev/etherswitch/ar40xx/ar40xx_reg.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw.h>
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#include <dev/etherswitch/ar40xx/ar40xx_phy.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_atu.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_mdio.h>
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#include <dev/etherswitch/ar40xx/ar40xx_hw_psgmii.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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/*
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* Routines that control the ess-psgmii block - the interconnect
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* between the ess-switch and the external multi-port PHY
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* (eg Maple.)
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*/
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static void
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ar40xx_hw_psgmii_reg_write(struct ar40xx_softc *sc, uint32_t reg,
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uint32_t val)
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{
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bus_space_write_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle,
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reg, val);
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bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle,
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0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_WRITE);
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}
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static int
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ar40xx_hw_psgmii_reg_read(struct ar40xx_softc *sc, uint32_t reg)
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{
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int ret;
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bus_space_barrier(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle,
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0, sc->sc_psgmii_mem_size, BUS_SPACE_BARRIER_READ);
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ret = bus_space_read_4(sc->sc_psgmii_mem_tag, sc->sc_psgmii_mem_handle,
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reg);
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return (ret);
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}
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int
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ar40xx_hw_psgmii_set_mac_mode(struct ar40xx_softc *sc, uint32_t mac_mode)
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{
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if (mac_mode == PORT_WRAPPER_PSGMII) {
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ar40xx_hw_psgmii_reg_write(sc, AR40XX_PSGMII_MODE_CONTROL,
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0x2200);
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ar40xx_hw_psgmii_reg_write(sc, AR40XX_PSGMIIPHY_TX_CONTROL,
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0x8380);
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} else {
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device_printf(sc->sc_dev, "WARNING: unknown MAC_MODE=%u\n",
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mac_mode);
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}
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return (0);
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}
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int
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ar40xx_hw_psgmii_single_phy_testing(struct ar40xx_softc *sc, int phy)
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{
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int j;
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uint32_t tx_ok, tx_error;
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uint32_t rx_ok, rx_error;
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uint32_t tx_ok_high16;
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uint32_t rx_ok_high16;
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uint32_t tx_all_ok, rx_all_ok;
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MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x9000);
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MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x4140);
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for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
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uint16_t status;
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status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);
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if (status & AR40XX_PHY_SPEC_STATUS_LINK)
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break;
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/*
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* the polling interval to check if the PHY link up
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* or not
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* maxwait_timer: 750 ms +/-10 ms
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* minwait_timer : 1 us +/- 0.1us
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* time resides in minwait_timer ~ maxwait_timer
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* see IEEE 802.3 section 40.4.5.2
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*/
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DELAY(8 * 1000);
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}
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/* enable check */
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ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0000);
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ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8029, 0x0003);
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/* start traffic */
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ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8020, 0xa000);
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/*
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*wait for all traffic end
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* 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
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*/
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DELAY(60 * 1000);
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/* check counter */
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tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);
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tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);
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tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);
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rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);
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rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);
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rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);
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tx_all_ok = tx_ok + (tx_ok_high16 << 16);
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rx_all_ok = rx_ok + (rx_ok_high16 << 16);
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if (tx_all_ok == 0x1000 && tx_error == 0) {
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/* success */
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sc->sc_psgmii.phy_t_status &= ~(1U << phy);
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} else {
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device_printf(sc->sc_dev, "TX_OK=%d, tx_error=%d RX_OK=%d"
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" rx_error=%d\n",
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tx_all_ok, tx_error, rx_all_ok, rx_error);
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device_printf(sc->sc_dev,
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"PHY %d single test PSGMII issue happen!\n", phy);
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sc->sc_psgmii.phy_t_status |= BIT(phy);
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}
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MDIO_WRITEREG(sc->sc_mdio_dev, phy, 0x0, 0x1840);
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return (0);
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}
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int
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ar40xx_hw_psgmii_all_phy_testing(struct ar40xx_softc *sc)
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{
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int phy, j;
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x9000);
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x4140);
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for (j = 0; j < AR40XX_PSGMII_CALB_NUM; j++) {
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
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uint16_t status;
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status = MDIO_READREG(sc->sc_mdio_dev, phy, 0x11);
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if (!(status & (1U << 10)))
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break;
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}
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if (phy >= (AR40XX_NUM_PORTS - 1))
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break;
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/* The polling interval to check if the PHY link up or not */
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DELAY(8*1000);
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}
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/* enable check */
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0000);
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0003);
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/* start traffic */
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8020, 0xa000);
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/*
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* wait for all traffic end
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* 4096(pkt num)*1524(size)*8ns(125MHz)=49.9ms
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*/
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DELAY(60*1000); /* was 50ms */
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
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uint32_t tx_ok, tx_error;
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uint32_t rx_ok, rx_error;
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uint32_t tx_ok_high16;
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uint32_t rx_ok_high16;
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uint32_t tx_all_ok, rx_all_ok;
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/* check counter */
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tx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802e);
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tx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802d);
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tx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802f);
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rx_ok = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802b);
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rx_ok_high16 = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802a);
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rx_error = ar40xx_hw_phy_mmd_read(sc, phy, 7, 0x802c);
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tx_all_ok = tx_ok + (tx_ok_high16<<16);
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rx_all_ok = rx_ok + (rx_ok_high16<<16);
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if (tx_all_ok == 0x1000 && tx_error == 0) {
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/* success */
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sc->sc_psgmii.phy_t_status &= ~(1U << (phy + 8));
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} else {
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device_printf(sc->sc_dev,
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"PHY%d test see issue! (tx_all_ok=%u,"
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" rx_all_ok=%u, tx_error=%u, rx_error=%u)\n",
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phy, tx_all_ok, rx_all_ok, tx_error, rx_error);
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sc->sc_psgmii.phy_t_status |= (1U << (phy + 8));
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}
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}
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device_printf(sc->sc_dev, "PHY all test 0x%x\n",
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sc->sc_psgmii.phy_t_status);
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return (0);
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}
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/*
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* Reset PSGMII in the Malibu PHY.
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*/
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int
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ar40xx_hw_malibu_psgmii_ess_reset(struct ar40xx_softc *sc)
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{
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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uint32_t i;
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/* reset phy psgmii */
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/* fix phy psgmii RX 20bit */
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005b);
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/* reset phy psgmii */
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x001b);
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/* release reset phy psgmii */
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005b);
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for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
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uint32_t status;
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status = ar40xx_hw_phy_mmd_read(sc, 5, 1, 0x28);
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if (status & (1U << 0))
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break;
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/*
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* Polling interval to check PSGMII PLL in malibu is ready
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* the worst time is 8.67ms
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* for 25MHz reference clock
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* [512+(128+2048)*49]*80ns+100us
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*/
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DELAY(2000);
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}
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/* XXX TODO ;see if it timed out? */
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/*check malibu psgmii calibration done end..*/
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/*freeze phy psgmii RX CDR*/
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x1a, 0x2230);
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ar40xx_hw_ess_reset(sc);
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/*check psgmii calibration done start*/
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for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
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uint32_t status;
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status = ar40xx_hw_psgmii_reg_read(sc, 0xa0);
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if (status & (1U << 0))
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break;
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/* Polling interval to check PSGMII PLL in ESS is ready */
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DELAY(2000);
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}
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/* XXX TODO ;see if it timed out? */
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/* check dakota psgmii calibration done end..*/
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/* release phy psgmii RX CDR */
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x1a, 0x3230);
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/* release phy psgmii RX 20bit */
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MDIO_WRITEREG(sc->sc_mdio_dev, 5, 0x0, 0x005f);
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return (0);
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}
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int
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ar40xx_hw_psgmii_self_test(struct ar40xx_softc *sc)
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{
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uint32_t i, phy, reg;
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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ar40xx_hw_malibu_psgmii_ess_reset(sc);
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/* switch to access MII reg for copper */
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MDIO_WRITEREG(sc->sc_mdio_dev, 4, 0x1f, 0x8500);
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
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/*enable phy mdio broadcast write*/
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ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x801f);
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}
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/* force no link by power down */
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x1840);
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/* packet number*/
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8021, 0x1000);
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8062, 0x05e0);
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/* fix mdi status */
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x10, 0x6800);
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for (i = 0; i < AR40XX_PSGMII_CALB_NUM; i++) {
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sc->sc_psgmii.phy_t_status = 0;
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
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/* Enable port loopback for testing */
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AR40XX_REG_BARRIER_READ(sc);
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reg = AR40XX_REG_READ(sc,
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AR40XX_REG_PORT_LOOKUP(phy + 1));
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reg |= AR40XX_PORT_LOOKUP_LOOPBACK;
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AR40XX_REG_WRITE(sc,
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AR40XX_REG_PORT_LOOKUP(phy + 1), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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}
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++)
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ar40xx_hw_psgmii_single_phy_testing(sc, phy);
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ar40xx_hw_psgmii_all_phy_testing(sc);
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if (sc->sc_psgmii.phy_t_status)
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ar40xx_hw_malibu_psgmii_ess_reset(sc);
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else
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break;
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}
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if (i >= AR40XX_PSGMII_CALB_NUM)
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device_printf(sc->sc_dev, "PSGMII cannot recover\n");
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else
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device_printf(sc->sc_dev,
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"PSGMII recovered after %d times reset\n", i);
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/* configuration recover */
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/* packet number */
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8021, 0x0);
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/* disable check */
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8029, 0x0);
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/* disable traffic */
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ar40xx_hw_phy_mmd_write(sc, 0x1f, 7, 0x8020, 0x0);
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return (0);
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}
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int
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ar40xx_hw_psgmii_self_test_clean(struct ar40xx_softc *sc)
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{
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uint32_t reg;
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int phy;
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device_printf(sc->sc_dev, "%s: called\n", __func__);
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/* disable phy internal loopback */
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x10, 0x6860);
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MDIO_WRITEREG(sc->sc_mdio_dev, 0x1f, 0x0, 0x9040);
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for (phy = 0; phy < AR40XX_NUM_PORTS - 1; phy++) {
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/* disable mac loop back */
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reg = AR40XX_REG_READ(sc, AR40XX_REG_PORT_LOOKUP(phy + 1));
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reg &= ~AR40XX_PORT_LOOKUP_LOOPBACK;
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AR40XX_REG_WRITE(sc, AR40XX_REG_PORT_LOOKUP(phy + 1), reg);
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AR40XX_REG_BARRIER_WRITE(sc);
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/* disable phy mdio broadcast write */
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ar40xx_hw_phy_mmd_write(sc, phy, 7, 0x8028, 0x001f);
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}
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/* clear fdb entry */
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ar40xx_hw_atu_flush_all(sc);
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return (0);
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}
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int
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ar40xx_hw_psgmii_init_config(struct ar40xx_softc *sc)
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{
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uint32_t reg;
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/*
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* This is based on what I found in uboot - it configures
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* the initial ESS interconnect to either be PSGMII
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* or RGMII.
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*/
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/* For now, just assume PSGMII and fix it in post. */
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/* PSGMIIPHY_PLL_VCO_RELATED_CTRL */
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reg = ar40xx_hw_psgmii_reg_read(sc, 0x78c);
|
|
device_printf(sc->sc_dev,
|
|
"%s: PSGMIIPHY_PLL_VCO_RELATED_CTRL=0x%08x\n", __func__, reg);
|
|
/* PSGMIIPHY_VCO_CALIBRATION_CTRL */
|
|
reg = ar40xx_hw_psgmii_reg_read(sc, 0x09c);
|
|
device_printf(sc->sc_dev,
|
|
"%s: PSGMIIPHY_VCO_CALIBRATION_CTRL=0x%08x\n", __func__, reg);
|
|
|
|
return (0);
|
|
}
|