* Refactor the initial learning configuration (port learning, address expiry, handling address moving between ports, etc, etc) into a separate HAL routine * and ensure that it's consistent between switch chips - the AR8216,8316,724x,9331 SoCs all share the same switch code. * .. the AR8327 needs doing - the defaults seem OK for now * .. the AR9340 is different but it's also programmed now. * Add support for flushing a single port worth of ATU entries * Add support for fetching the ATU table from AR8216 and derived chips Tested: * AR9344, Carambola 2 TODO: * Further testing on other chips * Add AR9340 support * Add AR8327 support
174 lines
5.0 KiB
C
174 lines
5.0 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2011-2012 Stefan Bethke.
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* Copyright (c) 2012 Adrian Chadd.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#include <sys/param.h>
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#include <sys/bus.h>
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#include <sys/errno.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/socket.h>
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#include <sys/sockio.h>
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#include <sys/sysctl.h>
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#include <sys/systm.h>
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#include <net/if.h>
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#include <net/if_arp.h>
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#include <net/ethernet.h>
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#include <net/if_dl.h>
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#include <net/if_media.h>
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#include <net/if_types.h>
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#include <machine/bus.h>
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#include <dev/iicbus/iic.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include <dev/mii/mii.h>
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#include <dev/mii/miivar.h>
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#include <dev/mdio/mdio.h>
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#include <dev/etherswitch/etherswitch.h>
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#include <dev/etherswitch/arswitch/arswitchreg.h>
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#include <dev/etherswitch/arswitch/arswitchvar.h>
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#include <dev/etherswitch/arswitch/arswitch_reg.h>
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#include <dev/etherswitch/arswitch/arswitch_8316.h>
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#include "mdio_if.h"
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#include "miibus_if.h"
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#include "etherswitch_if.h"
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/*
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* AR8316 specific functions
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*/
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static int
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ar8316_hw_setup(struct arswitch_softc *sc)
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{
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/*
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* Configure the switch mode based on whether:
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*
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* + The switch port is GMII/RGMII;
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* + Port 4 is either connected to the CPU or to the internal switch.
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*/
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if (sc->is_rgmii && sc->phy4cpu) {
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arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
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AR8X16_MODE_RGMII_PORT4_ISO);
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device_printf(sc->sc_dev,
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"%s: MAC port == RGMII, port 4 = dedicated PHY\n",
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__func__);
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} else if (sc->is_rgmii) {
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arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
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AR8X16_MODE_RGMII_PORT4_SWITCH);
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device_printf(sc->sc_dev,
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"%s: MAC port == RGMII, port 4 = switch port\n",
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__func__);
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} else if (sc->is_gmii) {
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arswitch_writereg(sc->sc_dev, AR8X16_REG_MODE,
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AR8X16_MODE_GMII);
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device_printf(sc->sc_dev, "%s: MAC port == GMII\n", __func__);
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} else {
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device_printf(sc->sc_dev, "%s: unknown switch PHY config\n",
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__func__);
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return (ENXIO);
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}
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DELAY(1000); /* 1ms wait for things to settle */
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/*
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* If port 4 is RGMII, force workaround
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*/
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if (sc->is_rgmii && sc->phy4cpu) {
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device_printf(sc->sc_dev,
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"%s: port 4 RGMII workaround\n",
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__func__);
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/* work around for phy4 rgmii mode */
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arswitch_writedbg(sc->sc_dev, 4, 0x12, 0x480c);
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/* rx delay */
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arswitch_writedbg(sc->sc_dev, 4, 0x0, 0x824e);
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/* tx delay */
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arswitch_writedbg(sc->sc_dev, 4, 0x5, 0x3d47);
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DELAY(1000); /* 1ms, again to let things settle */
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}
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return (0);
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}
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/*
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* Initialise other global values, for the AR8316.
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*/
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static int
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ar8316_hw_global_setup(struct arswitch_softc *sc)
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{
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ARSWITCH_LOCK(sc);
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arswitch_writereg(sc->sc_dev, 0x38, AR8X16_MAGIC);
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/* Enable CPU port and disable mirror port. */
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arswitch_writereg(sc->sc_dev, AR8X16_REG_CPU_PORT,
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AR8X16_CPU_PORT_EN | AR8X16_CPU_MIRROR_DIS);
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/* Setup TAG priority mapping. */
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arswitch_writereg(sc->sc_dev, AR8X16_REG_TAG_PRIO, 0xfa50);
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/*
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* Flood address table misses to all ports, and enable forwarding of
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* broadcasts to the cpu port.
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*/
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arswitch_writereg(sc->sc_dev, AR8X16_REG_FLOOD_MASK,
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AR8X16_FLOOD_MASK_BCAST_TO_CPU | 0x003f003f);
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/* Enable jumbo frames. */
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arswitch_modifyreg(sc->sc_dev, AR8X16_REG_GLOBAL_CTRL,
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AR8316_GLOBAL_CTRL_MTU_MASK, 9018 + 8 + 2);
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/* Setup service TAG. */
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arswitch_modifyreg(sc->sc_dev, AR8X16_REG_SERVICE_TAG,
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AR8X16_SERVICE_TAG_MASK, 0);
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ARSWITCH_UNLOCK(sc);
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return (0);
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}
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void
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ar8316_attach(struct arswitch_softc *sc)
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{
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sc->hal.arswitch_hw_setup = ar8316_hw_setup;
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sc->hal.arswitch_hw_global_setup = ar8316_hw_global_setup;
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/* Set the switch vlan capabilities. */
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sc->info.es_vlan_caps = ETHERSWITCH_VLAN_DOT1Q |
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ETHERSWITCH_VLAN_PORT | ETHERSWITCH_VLAN_DOUBLE_TAG;
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sc->info.es_nvlangroups = AR8X16_MAX_VLANS;
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}
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