4abe6533e9
The qualcomm TLMM (top level mode manager) is their gpio/pinmux hardware controller. Although the pinmux is generic enough to use for the IPQ/APQ series chips, I'm directly calling the IPQ4018 routines to expedite bring-up. Notably, I'm not yet implementing the interrupt support - it's not required at this stage of bring-up. Differential Revision: https://reviews.freebsd.org/D33554
86 lines
3.6 KiB
C
86 lines
3.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Adrian Chadd <adrian@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef __QCOM_TLMM_IPQ4018_REG_H__
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#define __QCOM_TLMM_IPQ4018_REG_H__
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/*
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* Each GPIO pin configuration block exists in a 0x1000 sized window.
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*/
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#define QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_BASE 0x0
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#define QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_SIZE 0x1000
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/*
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* Inside each configuration block are the following registers for
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* controlling the pin.
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*/
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL 0x00
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/* 1 = output gpio pin, 0 = input gpio pin */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_MASK 0x3
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_SHIFT 0x0
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_DISABLE 0
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLDOWN 1
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_PULLUP 2
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/* There's no BUSHOLD on IPQ4018 */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_PUPD_BUSHOLD 0
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_MASK 0x7
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_MUX_SHIFT 2
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/* function/mux control */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_SHIFT 6
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_DRIVE_STRENGTH_MASK 0x7
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OE_ENABLE (1U << 9)
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/* output enable */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_VM_ENABLE (1U << 11)
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/* VM passthrough enable */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_OD_ENABLE (1U << 12)
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/* open drain */
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_RES_MASK 0x3
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_RES_SHIFT 13
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_10K 0x0
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_1K5 0x1
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_35K 0x2
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#define QCOM_TLMM_IPQ4018_REG_PIN_CONTROL_20K 0x3
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#define QCOM_TLMM_IPQ4018_REG_PIN_IO 0x04
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#define QCOM_TLMM_IPQ4018_REG_PIN_IO_INPUT_STATUS (1U << 0)
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/* read gpio input status */
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#define QCOM_TLMM_IPQ4018_REG_PIN_IO_OUTPUT_EN (1U << 1)
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/* set gpio output high or low */
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#define QCOM_TLMM_IPQ4018_REG_PIN_INTR_CONFIG 0x08
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#define QCOM_TLMM_IPQ4018_REG_PIN_INTR_STATUS 0x0c
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#define QCOM_TLMM_IPQ4018_REG_PIN(p, reg) \
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(((p) * QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_SIZE) + \
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QCOM_TLMM_IPQ4018_REG_CONFIG_PIN_BASE + (reg))
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#endif /* __QCOM_TLMM_IPQ4018_REG_H__ */
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