341 lines
8.2 KiB
C
341 lines
8.2 KiB
C
/*-
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* Copyright (c) 2017 Justin Hibbits
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/cpu.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/smp.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/cpu.h>
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#include <powerpc/mpc85xx/mpc85xx.h>
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#include "cpufreq_if.h"
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/* No worries about uint32_t math overflow in here, because the highest
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* multiplier supported is 4, and the highest speed part is still well below
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* 2GHz.
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*/
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#define GUTS_PORPLLSR (CCSRBAR_VA + 0xe0000)
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#define GUTS_PMJCR (CCSRBAR_VA + 0xe007c)
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#define PMJCR_RATIO_M 0x3f
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#define PMJCR_CORE_MULT(x,y) ((x) << (16 + ((y) * 8)))
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#define PMJCR_GET_CORE_MULT(x,y) (((x) >> (16 + ((y) * 8))) & 0x3f)
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#define GUTS_POWMGTCSR (CCSRBAR_VA + 0xe0080)
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#define POWMGTCSR_JOG 0x00200000
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#define POWMGTCSR_INT_MASK 0x00000f00
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#define MHZ 1000000
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struct mpc85xx_jog_softc {
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device_t dev;
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int cpu;
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int low;
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int high;
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int min_freq;
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};
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static struct ofw_compat_data *mpc85xx_jog_devcompat(void);
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static void mpc85xx_jog_identify(driver_t *driver, device_t parent);
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static int mpc85xx_jog_probe(device_t dev);
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static int mpc85xx_jog_attach(device_t dev);
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static int mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count);
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static int mpc85xx_jog_set(device_t dev, const struct cf_setting *set);
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static int mpc85xx_jog_get(device_t dev, struct cf_setting *set);
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static int mpc85xx_jog_type(device_t dev, int *type);
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static device_method_t mpc85xx_jog_methods[] = {
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/* Device interface */
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DEVMETHOD(device_identify, mpc85xx_jog_identify),
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DEVMETHOD(device_probe, mpc85xx_jog_probe),
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DEVMETHOD(device_attach, mpc85xx_jog_attach),
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/* cpufreq interface */
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DEVMETHOD(cpufreq_drv_set, mpc85xx_jog_set),
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DEVMETHOD(cpufreq_drv_get, mpc85xx_jog_get),
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DEVMETHOD(cpufreq_drv_type, mpc85xx_jog_type),
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DEVMETHOD(cpufreq_drv_settings, mpc85xx_jog_settings),
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{0, 0}
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};
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static driver_t mpc85xx_jog_driver = {
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"jog",
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mpc85xx_jog_methods,
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sizeof(struct mpc85xx_jog_softc)
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};
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DRIVER_MODULE(mpc85xx_jog, cpu, mpc85xx_jog_driver, 0, 0);
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struct mpc85xx_constraints {
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int threshold; /* Threshold frequency, in MHz, for setting CORE_SPD bit. */
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int min_mult; /* Minimum PLL multiplier. */
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};
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static struct mpc85xx_constraints mpc8536_constraints = {
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800,
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3
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};
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static struct mpc85xx_constraints p1022_constraints = {
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500,
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2
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};
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static struct ofw_compat_data jog_compat[] = {
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{"fsl,mpc8536-guts", (uintptr_t)&mpc8536_constraints},
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{"fsl,p1022-guts", (uintptr_t)&p1022_constraints},
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{NULL, 0}
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};
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static struct ofw_compat_data *
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mpc85xx_jog_devcompat(void)
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{
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phandle_t node;
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int i;
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node = OF_finddevice("/soc");
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if (node == -1)
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return (NULL);
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for (i = 0; jog_compat[i].ocd_str != NULL; i++)
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if (ofw_bus_find_compatible(node, jog_compat[i].ocd_str) > 0)
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break;
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if (jog_compat[i].ocd_str == NULL)
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return (NULL);
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return (&jog_compat[i]);
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}
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static void
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mpc85xx_jog_identify(driver_t *driver, device_t parent)
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{
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struct ofw_compat_data *compat;
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/* Make sure we're not being doubly invoked. */
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if (device_find_child(parent, "mpc85xx_jog", -1) != NULL)
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return;
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compat = mpc85xx_jog_devcompat();
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if (compat == NULL)
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return;
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/*
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* We attach a child for every CPU since settings need to
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* be performed on every CPU in the SMP case.
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*/
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if (BUS_ADD_CHILD(parent, 10, "jog", -1) == NULL)
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device_printf(parent, "add jog child failed\n");
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}
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static int
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mpc85xx_jog_probe(device_t dev)
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{
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struct ofw_compat_data *compat;
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compat = mpc85xx_jog_devcompat();
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if (compat == NULL || compat->ocd_str == NULL)
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return (ENXIO);
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device_set_desc(dev, "Freescale CPU Jogger");
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return (0);
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}
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static int
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mpc85xx_jog_attach(device_t dev)
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{
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struct ofw_compat_data *compat;
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struct mpc85xx_jog_softc *sc;
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struct mpc85xx_constraints *constraints;
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phandle_t cpu;
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uint32_t reg;
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sc = device_get_softc(dev);
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sc->dev = dev;
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compat = mpc85xx_jog_devcompat();
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constraints = (struct mpc85xx_constraints *)compat->ocd_data;
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cpu = ofw_bus_get_node(device_get_parent(dev));
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if (cpu <= 0) {
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device_printf(dev,"No CPU device tree node!\n");
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return (ENXIO);
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}
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OF_getencprop(cpu, "reg", &sc->cpu, sizeof(sc->cpu));
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reg = ccsr_read4(GUTS_PORPLLSR);
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/*
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* Assume power-on PLL is the highest PLL config supported on the
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* board.
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*/
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sc->high = PMJCR_GET_CORE_MULT(reg, sc->cpu);
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sc->min_freq = constraints->threshold;
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sc->low = constraints->min_mult;
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cpufreq_register(dev);
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return (0);
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}
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static int
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mpc85xx_jog_settings(device_t dev, struct cf_setting *sets, int *count)
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{
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struct mpc85xx_jog_softc *sc;
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uint32_t sysclk;
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int i;
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sc = device_get_softc(dev);
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if (sets == NULL || count == NULL)
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return (EINVAL);
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if (*count < sc->high - 1)
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return (E2BIG);
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sysclk = mpc85xx_get_system_clock();
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/* Return a list of valid settings for this driver. */
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memset(sets, CPUFREQ_VAL_UNKNOWN, sizeof(*sets) * sc->high);
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for (i = sc->high; i >= sc->low; --i) {
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sets[sc->high - i].freq = sysclk * i / MHZ;
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sets[sc->high - i].dev = dev;
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sets[sc->high - i].spec[0] = i;
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}
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*count = sc->high - sc->low + 1;
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return (0);
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}
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struct jog_rv_args {
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int cpu;
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int mult;
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int slow;
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volatile int inprogress;
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};
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static void
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mpc85xx_jog_set_int(void *arg)
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{
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struct jog_rv_args *args = arg;
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uint32_t reg;
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if (PCPU_GET(cpuid) == args->cpu) {
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reg = ccsr_read4(GUTS_PMJCR);
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reg &= ~PMJCR_CORE_MULT(PMJCR_RATIO_M, args->cpu);
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reg |= PMJCR_CORE_MULT(args->mult, args->cpu);
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if (args->slow)
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reg &= ~(1 << (12 + args->cpu));
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else
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reg |= (1 << (12 + args->cpu));
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ccsr_write4(GUTS_PMJCR, reg);
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reg = ccsr_read4(GUTS_POWMGTCSR);
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reg |= POWMGTCSR_JOG | POWMGTCSR_INT_MASK;
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ccsr_write4(GUTS_POWMGTCSR, reg);
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/* Wait for completion */
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do {
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DELAY(100);
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reg = ccsr_read4(GUTS_POWMGTCSR);
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} while (reg & POWMGTCSR_JOG);
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reg = ccsr_read4(GUTS_POWMGTCSR);
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ccsr_write4(GUTS_POWMGTCSR, reg & ~POWMGTCSR_INT_MASK);
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ccsr_read4(GUTS_POWMGTCSR);
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args->inprogress = 0;
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} else {
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while (args->inprogress)
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cpu_spinwait();
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}
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}
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static int
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mpc85xx_jog_set(device_t dev, const struct cf_setting *set)
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{
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struct mpc85xx_jog_softc *sc;
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struct jog_rv_args args;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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args.slow = (set->freq <= sc->min_freq);
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args.mult = set->spec[0];
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args.cpu = PCPU_GET(cpuid);
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args.inprogress = 1;
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smp_rendezvous(smp_no_rendezvous_barrier, mpc85xx_jog_set_int,
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smp_no_rendezvous_barrier, &args);
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return (0);
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}
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static int
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mpc85xx_jog_get(device_t dev, struct cf_setting *set)
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{
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struct mpc85xx_jog_softc *sc;
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uint32_t pmjcr;
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uint32_t freq;
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if (set == NULL)
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return (EINVAL);
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sc = device_get_softc(dev);
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memset(set, CPUFREQ_VAL_UNKNOWN, sizeof(*set));
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pmjcr = ccsr_read4(GUTS_PORPLLSR);
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freq = PMJCR_GET_CORE_MULT(pmjcr, sc->cpu);
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freq *= mpc85xx_get_system_clock();
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freq /= MHZ;
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set->freq = freq;
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set->dev = dev;
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return (0);
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}
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static int
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mpc85xx_jog_type(device_t dev, int *type)
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{
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if (type == NULL)
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return (EINVAL);
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*type = CPUFREQ_TYPE_ABSOLUTE;
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return (0);
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}
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