464 lines
11 KiB
C
464 lines
11 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
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*
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* Copyright (c) 2021 Jessica Clarke <jrtc27@FreeBSD.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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/* TODO: Provide interrupt controller interface */
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/gpio.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <machine/bus.h>
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/* Registers are 32-bit so can only fit 32 pins */
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#define SFGPIO_MAX_PINS 32
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#define SFGPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)
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#define SFGPIO_INPUT_VAL 0x0
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#define SFGPIO_INPUT_EN 0x4
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#define SFGPIO_OUTPUT_EN 0x8
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#define SFGPIO_OUTPUT_VAL 0xc
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#define SFGPIO_RISE_IE 0x18
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#define SFGPIO_RISE_IP 0x1c
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#define SFGPIO_FALL_IE 0x20
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#define SFGPIO_FALL_IP 0x24
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#define SFGPIO_HIGH_IE 0x28
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#define SFGPIO_HIGH_IP 0x2c
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#define SFGPIO_LOW_IE 0x30
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#define SFGPIO_LOW_IP 0x34
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struct sfgpio_softc {
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device_t dev;
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device_t busdev;
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struct mtx mtx;
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struct resource *mem_res;
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int mem_rid;
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struct resource *irq_res;
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int irq_rid;
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int npins;
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struct gpio_pin gpio_pins[SFGPIO_MAX_PINS];
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};
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#define SFGPIO_LOCK(_sc) mtx_lock(&(_sc)->mtx)
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#define SFGPIO_UNLOCK(_sc) mtx_unlock(&(_sc)->mtx)
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#define SFGPIO_READ(_sc, _off) \
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bus_read_4((_sc)->mem_res, (_off))
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#define SFGPIO_WRITE(_sc, _off, _val) \
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bus_write_4((_sc)->mem_res, (_off), (_val))
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static struct ofw_compat_data compat_data[] = {
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{ "sifive,gpio0", 1 },
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{ NULL, 0 },
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};
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static int
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sfgpio_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "SiFive GPIO Controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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sfgpio_attach(device_t dev)
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{
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struct sfgpio_softc *sc;
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phandle_t node;
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int error, i;
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pcell_t npins;
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uint32_t input_en, output_en;
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sc = device_get_softc(dev);
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sc->dev = dev;
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node = ofw_bus_get_node(dev);
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mtx_init(&sc->mtx, device_get_nameunit(sc->dev), NULL, MTX_DEF);
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sc->mem_rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
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&sc->mem_rid, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Cannot allocate memory resource\n");
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error = ENXIO;
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goto fail;
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}
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if (OF_getencprop(node, "ngpios", &npins, sizeof(npins)) <= 0) {
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/* Optional; defaults to 16 */
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npins = 16;
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} else if (npins > SFGPIO_MAX_PINS) {
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device_printf(dev, "Too many pins: %d\n", npins);
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error = ENXIO;
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goto fail;
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}
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sc->npins = npins;
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sc->irq_rid = 0;
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sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &sc->irq_rid,
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RF_ACTIVE);
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if (sc->irq_res == NULL) {
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device_printf(dev, "Cannot allocate IRQ resource\n");
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error = ENXIO;
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goto fail;
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}
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input_en = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
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output_en = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
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for (i = 0; i < sc->npins; ++i) {
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sc->gpio_pins[i].gp_pin = i;
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sc->gpio_pins[i].gp_caps = SFGPIO_DEFAULT_CAPS;
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sc->gpio_pins[i].gp_flags =
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((input_en & (1u << i)) ? GPIO_PIN_INPUT : 0) |
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((output_en & (1u << i)) ? GPIO_PIN_OUTPUT : 0);
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snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, "GPIO%d", i);
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sc->gpio_pins[i].gp_name[GPIOMAXNAME - 1] = '\0';
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}
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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device_printf(dev, "Cannot attach gpiobus\n");
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error = ENXIO;
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goto fail;
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}
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return (0);
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fail:
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if (sc->busdev != NULL)
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gpiobus_detach_bus(dev);
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if (sc->irq_res != NULL)
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bus_release_resource(dev, SYS_RES_IRQ, sc->irq_rid,
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sc->irq_res);
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if (sc->mem_res != NULL)
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bus_release_resource(dev, SYS_RES_MEMORY, sc->mem_rid,
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sc->mem_res);
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mtx_destroy(&sc->mtx);
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return (error);
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}
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static device_t
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sfgpio_get_bus(device_t dev)
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{
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struct sfgpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->busdev);
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}
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static int
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sfgpio_pin_max(device_t dev, int *maxpin)
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{
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struct sfgpio_softc *sc;
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sc = device_get_softc(dev);
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*maxpin = sc->npins - 1;
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return (0);
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}
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static int
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sfgpio_pin_set(device_t dev, uint32_t pin, unsigned int val)
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{
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struct sfgpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
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if (val)
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reg |= (1u << pin);
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else
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reg &= ~(1u << pin);
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SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_get(device_t dev, uint32_t pin, unsigned int *val)
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{
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struct sfgpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OUTPUT)
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reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
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else
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reg = SFGPIO_READ(sc, SFGPIO_INPUT_VAL);
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*val = (reg & (1u << pin)) ? 1 : 0;
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct sfgpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
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reg ^= (1u << pin);
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SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL, reg);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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struct sfgpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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*caps = sc->gpio_pins[pin].gp_caps;
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct sfgpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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*flags = sc->gpio_pins[pin].gp_flags;
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct sfgpio_softc *sc;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct sfgpio_softc *sc;
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uint32_t reg;
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sc = device_get_softc(dev);
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if (pin >= sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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reg = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
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if (flags & GPIO_PIN_INPUT) {
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reg |= (1u << pin);
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sc->gpio_pins[pin].gp_flags |= GPIO_PIN_INPUT;
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} else {
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reg &= ~(1u << pin);
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sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_INPUT;
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}
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SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, reg);
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reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
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if (flags & GPIO_PIN_OUTPUT) {
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reg |= (1u << pin);
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sc->gpio_pins[pin].gp_flags |= GPIO_PIN_OUTPUT;
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} else {
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reg &= ~(1u << pin);
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sc->gpio_pins[pin].gp_flags &= ~GPIO_PIN_OUTPUT;
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}
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SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, reg);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins,
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uint32_t change_pins, uint32_t *orig_pins)
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{
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struct sfgpio_softc *sc;
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uint32_t reg;
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if (first_pin != 0)
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return (EINVAL);
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sc = device_get_softc(dev);
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SFGPIO_LOCK(sc);
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reg = SFGPIO_READ(sc, SFGPIO_OUTPUT_VAL);
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if (orig_pins != NULL)
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/* Only input_val is implicitly masked by input_en */
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*orig_pins = SFGPIO_READ(sc, SFGPIO_INPUT_VAL) |
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(reg & SFGPIO_READ(sc, SFGPIO_OUTPUT_EN));
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if ((clear_pins | change_pins) != 0)
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SFGPIO_WRITE(sc, SFGPIO_OUTPUT_VAL,
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(reg & ~clear_pins) ^ change_pins);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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sfgpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins,
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uint32_t *pin_flags)
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{
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struct sfgpio_softc *sc;
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uint32_t ireg, oreg;
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int i;
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sc = device_get_softc(dev);
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if (first_pin != 0 || num_pins > sc->npins)
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return (EINVAL);
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SFGPIO_LOCK(sc);
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ireg = SFGPIO_READ(sc, SFGPIO_INPUT_EN);
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oreg = SFGPIO_READ(sc, SFGPIO_OUTPUT_EN);
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for (i = 0; i < num_pins; ++i) {
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if (pin_flags[i] & GPIO_PIN_INPUT) {
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ireg |= (1u << i);
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oreg &= ~(1u << i);
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sc->gpio_pins[i].gp_flags |= GPIO_PIN_INPUT;
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sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_OUTPUT;
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} else if (pin_flags[i] & GPIO_PIN_OUTPUT) {
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ireg &= ~(1u << i);
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oreg |= (1u << i);
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sc->gpio_pins[i].gp_flags &= ~GPIO_PIN_INPUT;
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sc->gpio_pins[i].gp_flags |= GPIO_PIN_OUTPUT;
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}
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}
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SFGPIO_WRITE(sc, SFGPIO_INPUT_EN, ireg);
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SFGPIO_WRITE(sc, SFGPIO_OUTPUT_EN, oreg);
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SFGPIO_UNLOCK(sc);
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return (0);
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}
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static phandle_t
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sfgpio_get_node(device_t bus, device_t dev)
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{
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return (ofw_bus_get_node(bus));
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}
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static device_method_t sfgpio_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, sfgpio_probe),
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DEVMETHOD(device_attach, sfgpio_attach),
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/* GPIO protocol */
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DEVMETHOD(gpio_get_bus, sfgpio_get_bus),
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DEVMETHOD(gpio_pin_max, sfgpio_pin_max),
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DEVMETHOD(gpio_pin_set, sfgpio_pin_set),
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DEVMETHOD(gpio_pin_get, sfgpio_pin_get),
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DEVMETHOD(gpio_pin_toggle, sfgpio_pin_toggle),
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DEVMETHOD(gpio_pin_getcaps, sfgpio_pin_getcaps),
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DEVMETHOD(gpio_pin_getflags, sfgpio_pin_getflags),
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DEVMETHOD(gpio_pin_getname, sfgpio_pin_getname),
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DEVMETHOD(gpio_pin_setflags, sfgpio_pin_setflags),
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DEVMETHOD(gpio_pin_access_32, sfgpio_pin_access_32),
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DEVMETHOD(gpio_pin_config_32, sfgpio_pin_config_32),
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/* ofw_bus interface */
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DEVMETHOD(ofw_bus_get_node, sfgpio_get_node),
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DEVMETHOD_END
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};
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DEFINE_CLASS_0(gpio, sfgpio_driver, sfgpio_methods,
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sizeof(struct sfgpio_softc));
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EARLY_DRIVER_MODULE(gpio, simplebus, sfgpio_driver, 0, 0,
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BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
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MODULE_DEPEND(sfgpio, gpiobus, 1, 1, 1);
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