9be376cc32
Clean out some #if 0'ed debugging cruft. aic7xxx.h: Definitions for the aic7855 and aic7859.
613 lines
18 KiB
C
613 lines
18 KiB
C
/*
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* Interface to the generic driver for the aic7xxx based adaptec
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* SCSI controllers. This is used to implement product specific
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* probe and attach routines.
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*
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* Copyright (c) 1994, 1995, 1996, 1997, 1998, 1999 Justin T. Gibbs.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* Where this Software is combined with software released under the terms of
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* the GNU Public License ("GPL") and the terms of the GPL would require the
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* combined work to also be released under the terms of the GPL, the terms
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* and conditions of this License will apply in addition to those of the
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* GPL with the exception of any terms or conditions of this License that
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* conflict with, or are expressly prohibited by, the GPL.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _AIC7XXX_H_
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#define _AIC7XXX_H_
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#include "ahc.h" /* for NAHC from config */
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#include "opt_aic7xxx.h" /* for config options */
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#include <sys/bus.h> /* For device_t */
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#ifndef MAX
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#define MAX(a,b) (((a) > (b)) ? (a) : (b))
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#endif
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#ifndef MIN
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#define MIN(a,b) (((a) < (b)) ? (a) : (b))
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#endif
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/*
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* The maximum transfer per S/G segment.
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*/
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#define AHC_MAXTRANSFER_SIZE 0x00ffffff /* limited by 24bit counter */
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/*
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* The number of dma segments supported. The current implementation limits
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* us to 255 S/G entries (this may change to be unlimited at some point).
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* To reduce the driver's memory consumption, we further limit the number
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* supported to be sufficient to handle the largest mapping supported by
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* the kernel, MAXPHYS. Assuming the transfer is as fragmented as possible
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* and unaligned, this turns out to be the number of paged sized transfers
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* in MAXPHYS plus an extra element to handle any unaligned residual.
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*/
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#define AHC_NSEG (MIN(btoc(MAXPHYS) + 1, 255))
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#define AHC_SCB_MAX 255 /*
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* Up to 255 SCBs on some types of aic7xxx
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* based boards. The aic7870 have 16 internal
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* SCBs, but external SRAM bumps this to 255.
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* The aic7770 family have only 4, and the
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* aic7850 has only 3.
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*/
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#define AHC_TMODE_CMDS 256 /*
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* Ring Buffer of incoming target commands.
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* We allocate 256 to simplify the logic
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* in the sequencer by using the natural
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* wrap point of an 8bit counter.
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*/
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struct ahc_dma_seg {
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u_int32_t addr;
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u_int32_t len;
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};
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typedef enum {
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AHC_NONE = 0x0000,
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AHC_CHIPID_MASK = 0x00FF,
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AHC_AIC7770 = 0x0001,
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AHC_AIC7850 = 0x0002,
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AHC_AIC7855 = 0x0003,
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AHC_AIC7859 = 0x0004,
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AHC_AIC7860 = 0x0005,
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AHC_AIC7870 = 0x0006,
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AHC_AIC7880 = 0x0007,
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AHC_AIC7890 = 0x0008,
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AHC_AIC7895 = 0x0009,
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AHC_AIC7896 = 0x000a,
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AHC_VL = 0x0100, /* Bus type VL */
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AHC_EISA = 0x0200, /* Bus type EISA */
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AHC_PCI = 0x0400, /* Bus type PCI */
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} ahc_chip;
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typedef enum {
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AHC_FENONE = 0x0000,
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AHC_ULTRA = 0x0001, /* Supports 20MHz Transfers */
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AHC_ULTRA2 = 0x0002, /* Supports 40MHz Transfers */
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AHC_WIDE = 0x0004, /* Wide Channel */
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AHC_TWIN = 0x0008, /* Twin Channel */
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AHC_MORE_SRAM = 0x0010, /* 80 bytes instead of 64 */
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AHC_CMD_CHAN = 0x0020, /* Has a Command DMA Channel */
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AHC_QUEUE_REGS = 0x0040, /* Has Queue management registers */
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AHC_SG_PRELOAD = 0x0080, /* Can perform auto-SG preload */
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AHC_SPIOCAP = 0x0100, /* Has a Serial Port I/O Cap Register */
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AHC_MULTI_TID = 0x0200, /* Has bitmask of TIDs for select-in */
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AHC_HS_MAILBOX = 0x0400, /* Has HS_MAILBOX register */
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AHC_AIC7770_FE = AHC_FENONE,
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AHC_AIC7850_FE = AHC_FENONE|AHC_SPIOCAP,
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AHC_AIC7855_FE = AHC_FENONE|AHC_SPIOCAP,
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AHC_AIC7859_FE = AHC_ULTRA|AHC_SPIOCAP,
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AHC_AIC7860_FE = AHC_ULTRA|AHC_SPIOCAP,
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AHC_AIC7870_FE = AHC_FENONE,
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AHC_AIC7880_FE = AHC_ULTRA,
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AHC_AIC7890_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
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|AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX,
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AHC_AIC7895_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA,
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AHC_AIC7895C_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA|AHC_MULTI_TID,
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AHC_AIC7896_FE = AHC_MORE_SRAM|AHC_CMD_CHAN|AHC_ULTRA2|AHC_QUEUE_REGS
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|AHC_SG_PRELOAD|AHC_MULTI_TID|AHC_HS_MAILBOX
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} ahc_feature;
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typedef enum {
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AHC_FNONE = 0x000,
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AHC_PAGESCBS = 0x001,/* Enable SCB paging */
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AHC_CHANNEL_B_PRIMARY = 0x002,/*
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* On twin channel adapters, probe
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* channel B first since it is the
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* primary bus.
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*/
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AHC_USEDEFAULTS = 0x004,/*
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* For cards without an seeprom
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* or a BIOS to initialize the chip's
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* SRAM, we use the default target
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* settings.
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*/
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AHC_SHARED_SRAM = 0x010,
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AHC_LARGE_SEEPROM = 0x020,/* Uses C56_66 not C46 */
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AHC_RESET_BUS_A = 0x040,
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AHC_RESET_BUS_B = 0x080,
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AHC_EXTENDED_TRANS_A = 0x100,
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AHC_EXTENDED_TRANS_B = 0x200,
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AHC_TERM_ENB_A = 0x400,
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AHC_TERM_ENB_B = 0x800,
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AHC_INITIATORMODE = 0x1000,/*
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* Allow initiator operations on
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* this controller.
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*/
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AHC_TARGETMODE = 0x2000,/*
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* Allow target operations on this
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* controller.
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*/
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AHC_NEWEEPROM_FMT = 0x4000,
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AHC_RESOURCE_SHORTAGE = 0x8000,
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AHC_TQINFIFO_BLOCKED = 0x10000,/* Blocked waiting for ATIOs */
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} ahc_flag;
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typedef enum {
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SCB_FREE = 0x0000,
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SCB_OTHERTCL_TIMEOUT = 0x0002,/*
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* Another device was active
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* during the first timeout for
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* this SCB so we gave ourselves
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* an additional timeout period
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* in case it was hogging the
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* bus.
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*/
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SCB_DEVICE_RESET = 0x0004,
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SCB_SENSE = 0x0008,
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SCB_RECOVERY_SCB = 0x0040,
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SCB_ABORT = 0x1000,
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SCB_QUEUED_MSG = 0x2000,
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SCB_ACTIVE = 0x4000,
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SCB_TARGET_IMMEDIATE = 0x8000
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} scb_flag;
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/*
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* The driver keeps up to MAX_SCB scb structures per card in memory. The SCB
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* consists of a "hardware SCB" mirroring the fields availible on the card
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* and additional information the kernel stores for each transaction.
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*/
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struct hardware_scb {
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/*0*/ u_int8_t control;
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/*1*/ u_int8_t tcl; /* 4/1/3 bits */
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/*2*/ u_int8_t status;
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/*3*/ u_int8_t SG_count;
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/*4*/ u_int32_t SG_pointer;
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/*8*/ u_int8_t residual_SG_count;
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/*9*/ u_int8_t residual_data_count[3];
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/*12*/ u_int32_t data;
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/*16*/ u_int32_t datalen; /* Really only three bytes, but its
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* faster to treat it as a long on
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* a quad boundary.
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*/
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/*20*/ u_int32_t cmdpointer;
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/*24*/ u_int8_t cmdlen;
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/*25*/ u_int8_t tag; /* Index into our kernel SCB array.
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* Also used as the tag for tagged I/O
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*/
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/*26*/ u_int8_t next; /* Used for threading SCBs in the
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* "Waiting for Selection" and
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* "Disconnected SCB" lists down
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* in the sequencer.
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*/
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/*27*/ u_int8_t scsirate; /* Value for SCSIRATE register */
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/*28*/ u_int8_t scsioffset; /* Value for SCSIOFFSET register */
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/*29*/ u_int8_t spare[3]; /*
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* Spare space available on
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* all controller types.
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*/
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/*32*/ u_int8_t cmdstore[16]; /*
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* CDB storage for controllers
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* supporting 64 byte SCBs.
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*/
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/*48*/ u_int32_t cmdstore_busaddr; /*
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* Address of command store for
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* 32byte SCB adapters
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*/
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/*48*/ u_int8_t spare_64[12]; /*
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* Pad to 64 bytes.
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*/
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};
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struct scb {
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struct hardware_scb *hscb;
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SLIST_ENTRY(scb) links; /* for chaining */
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union ccb *ccb; /* the ccb for this cmd */
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scb_flag flags;
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bus_dmamap_t dmamap;
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struct ahc_dma_seg *sg_list;
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bus_addr_t sg_list_phys;
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u_int sg_count;/* How full ahc_dma_seg is */
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};
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/*
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* Connection desciptor for select-in requests in target mode.
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* The first byte is the connecting target, followed by identify
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* message and optional tag information, terminated by 0xFF. The
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* remainder is the command to execute. The cmd_valid byte is on
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* an 8 byte boundary to simplify setting it on aic7880 hardware
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* which only has limited direct access to the DMA FIFO.
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*/
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struct target_cmd {
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u_int8_t initiator_channel;
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u_int8_t targ_id; /* Target ID we were selected at */
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u_int8_t identify; /* Identify message */
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u_int8_t bytes[21];
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u_int8_t cmd_valid;
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u_int8_t pad[7];
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};
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/*
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* Number of events we can buffer up if we run out
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* of immediate notify ccbs.
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*/
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#define AHC_TMODE_EVENT_BUFFER_SIZE 8
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struct ahc_tmode_event {
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u_int8_t initiator_id;
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u_int8_t event_type; /* MSG type or EVENT_TYPE_BUS_RESET */
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#define EVENT_TYPE_BUS_RESET 0xFF
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u_int8_t event_arg;
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};
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/*
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* Per lun target mode state including accept TIO CCB
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* and immediate notify CCB pools.
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*/
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struct tmode_lstate {
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struct cam_path *path;
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struct ccb_hdr_slist accept_tios;
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struct ccb_hdr_slist immed_notifies;
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struct ahc_tmode_event event_buffer[AHC_TMODE_EVENT_BUFFER_SIZE];
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u_int8_t event_r_idx;
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u_int8_t event_w_idx;
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};
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#define AHC_TRANS_CUR 0x01 /* Modify current neogtiation status */
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#define AHC_TRANS_ACTIVE 0x03 /* Assume this is the active target */
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#define AHC_TRANS_GOAL 0x04 /* Modify negotiation goal */
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#define AHC_TRANS_USER 0x08 /* Modify user negotiation settings */
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struct ahc_transinfo {
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u_int8_t width;
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u_int8_t period;
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u_int8_t offset;
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};
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struct ahc_initiator_tinfo {
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u_int8_t scsirate;
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struct ahc_transinfo current;
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struct ahc_transinfo goal;
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struct ahc_transinfo user;
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};
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/*
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* Per target mode enabled target state. Esentially just an array of
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* pointers to lun target state as well as sync/wide negotiation information
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* for each initiator<->target mapping (including the mapping for when we
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* are the initiator).
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*/
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struct tmode_tstate {
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struct tmode_lstate* enabled_luns[8];
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struct ahc_initiator_tinfo transinfo[16];
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/*
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* Per initiator state bitmasks.
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*/
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u_int16_t ultraenb; /* Using ultra sync rate */
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u_int16_t discenable; /* Disconnection allowed */
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u_int16_t tagenable; /* Tagged Queuing allowed */
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};
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/*
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* Define the format of the aic7XX0 SEEPROM registers (16 bits).
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*/
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struct seeprom_config {
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/*
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* SCSI ID Configuration Flags
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*/
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u_int16_t device_flags[16]; /* words 0-15 */
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#define CFXFER 0x0007 /* synchronous transfer rate */
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#define CFSYNCH 0x0008 /* enable synchronous transfer */
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#define CFDISC 0x0010 /* enable disconnection */
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#define CFWIDEB 0x0020 /* wide bus device */
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#define CFSYNCHISULTRA 0x0040 /* CFSYNCH is an ultra offset (2940AU)*/
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/* UNUSED 0x0080 */
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#define CFSTART 0x0100 /* send start unit SCSI command */
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#define CFINCBIOS 0x0200 /* include in BIOS scan */
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#define CFRNFOUND 0x0400 /* report even if not found */
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#define CFMULTILUN 0x0800 /* Probe multiple luns in BIOS scan */
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/* UNUSED 0xf000 */
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/*
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* BIOS Control Bits
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*/
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u_int16_t bios_control; /* word 16 */
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#define CFSUPREM 0x0001 /* support all removeable drives */
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#define CFSUPREMB 0x0002 /* support removeable drives for boot only */
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#define CFBIOSEN 0x0004 /* BIOS enabled */
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/* UNUSED 0x0008 */
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#define CFSM2DRV 0x0010 /* support more than two drives */
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#define CF284XEXTEND 0x0020 /* extended translation (284x cards) */
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/* UNUSED 0x0060 */
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#define CFEXTEND 0x0080 /* extended translation enabled */
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/* UNUSED 0xff00 */
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/*
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* Host Adapter Control Bits
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*/
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u_int16_t adapter_control; /* word 17 */
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#define CFAUTOTERM 0x0001 /* Perform Auto termination */
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#define CFULTRAEN 0x0002 /* Ultra SCSI speed enable */
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#define CF284XSELTO 0x0003 /* Selection timeout (284x cards) */
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#define CF284XFIFO 0x000C /* FIFO Threshold (284x cards) */
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#define CFSTERM 0x0004 /* SCSI low byte termination */
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#define CFWSTERM 0x0008 /* SCSI high byte termination */
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#define CFSPARITY 0x0010 /* SCSI parity */
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#define CF284XSTERM 0x0020 /* SCSI low byte term (284x cards) */
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#define CFRESETB 0x0040 /* reset SCSI bus at boot */
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#define CFCHNLBPRIMARY 0x0100 /* aic7895 probe B channel first */
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#define CFSEAUTOTERM 0x0400 /* aic7890 Perform SE Auto Termination*/
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#define CFLVDSTERM 0x0800 /* aic7890 LVD Termination */
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/* UNUSED 0xf080 */
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/*
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* Bus Release, Host Adapter ID
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*/
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u_int16_t brtime_id; /* word 18 */
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#define CFSCSIID 0x000f /* host adapter SCSI ID */
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/* UNUSED 0x00f0 */
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#define CFBRTIME 0xff00 /* bus release time */
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/*
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* Maximum targets
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*/
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u_int16_t max_targets; /* word 19 */
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#define CFMAXTARG 0x00ff /* maximum targets */
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/* UNUSED 0xff00 */
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u_int16_t res_1[11]; /* words 20-30 */
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u_int16_t checksum; /* word 31 */
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};
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struct ahc_syncrate {
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int sxfr_ultra2;
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int sxfr;
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/* Rates in Ultra mode have bit 8 of sxfr set */
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#define ULTRA_SXFR 0x100
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u_int8_t period; /* Period to send to SCSI target */
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char *rate;
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};
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typedef enum {
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MSG_TYPE_NONE = 0x00,
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MSG_TYPE_INITIATOR_MSGOUT = 0x01,
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MSG_TYPE_INITIATOR_MSGIN = 0x02,
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MSG_TYPE_TARGET_MSGOUT = 0x03,
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MSG_TYPE_TARGET_MSGIN = 0x04
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} ahc_msg_type;
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struct sg_map_node {
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bus_dmamap_t sg_dmamap;
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bus_addr_t sg_physaddr;
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struct ahc_dma_seg* sg_vaddr;
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SLIST_ENTRY(sg_map_node) links;
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};
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struct scb_data {
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struct hardware_scb *hscbs; /* Array of hardware SCBs */
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struct scb *scbarray; /* Array of kernel SCBs */
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SLIST_HEAD(, scb) free_scbs; /*
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* Pool of SCBs ready to be assigned
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* commands to execute.
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*/
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struct scsi_sense_data *sense; /* Per SCB sense data */
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/*
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* "Bus" addresses of our data structures.
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*/
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bus_dma_tag_t hscb_dmat; /* dmat for our hardware SCB array */
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bus_dmamap_t hscb_dmamap;
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bus_addr_t hscb_busaddr;
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bus_dma_tag_t sense_dmat;
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bus_dmamap_t sense_dmamap;
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bus_addr_t sense_busaddr;
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bus_dma_tag_t sg_dmat; /* dmat for our sg segments */
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SLIST_HEAD(, sg_map_node) sg_maps;
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u_int8_t numscbs;
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u_int8_t maxhscbs; /* Number of SCBs on the card */
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u_int8_t init_level; /*
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* How far we've initialized
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* this structure.
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*/
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};
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struct ahc_softc {
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bus_space_tag_t tag;
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bus_space_handle_t bsh;
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bus_dma_tag_t buffer_dmat; /* dmat for buffer I/O */
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struct scb_data *scb_data;
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/*
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* CCBs that have been send to the controller
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*/
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LIST_HEAD(, ccb_hdr) pending_ccbs;
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/*
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* Target mode related state kept on a per enabled lun basis.
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* Targets that are not enabled will have null entries.
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* As an initiator, we keep one target entry for our initiator
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* ID to store our sync/wide transfer settings.
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*/
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struct tmode_tstate* enabled_targets[16];
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/*
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* The black hole device responsible for handling requests for
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* disabled luns on enabled targets.
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*/
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struct tmode_lstate* black_hole;
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|
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/*
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* Device instance currently on the bus awaiting a continue TIO
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* for a command that was not given the disconnect priveledge.
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*/
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struct tmode_lstate* pending_device;
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|
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/*
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* Card characteristics
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*/
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ahc_chip chip;
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ahc_feature features;
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ahc_flag flags;
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|
|
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/* Values to store in the SEQCTL register for pause and unpause */
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u_int8_t unpause;
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u_int8_t pause;
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|
|
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/* Command Queues */
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u_int8_t qoutfifonext;
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|
u_int8_t qinfifonext;
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|
u_int8_t *qoutfifo;
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u_int8_t *qinfifo;
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|
|
|
/*
|
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* 256 byte array storing the SCBID of outstanding
|
|
* untagged SCBs indexed by TCL.
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|
*/
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|
u_int8_t *untagged_scbs;
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|
|
|
/*
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|
* Hooks into the XPT.
|
|
*/
|
|
struct cam_sim *sim;
|
|
struct cam_sim *sim_b;
|
|
struct cam_path *path;
|
|
struct cam_path *path_b;
|
|
|
|
int unit;
|
|
|
|
/* Channel Names ('A', 'B', etc.) */
|
|
char channel;
|
|
char channel_b;
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|
|
|
/* Initiator Bus ID */
|
|
u_int8_t our_id;
|
|
u_int8_t our_id_b;
|
|
|
|
/* Targets that need negotiation messages */
|
|
u_int16_t targ_msg_req;
|
|
|
|
/*
|
|
* PCI error detection and data for running the
|
|
* PCI error interrupt handler.
|
|
*/
|
|
int unsolicited_ints;
|
|
device_t device;
|
|
|
|
/*
|
|
* Target incoming command FIFO.
|
|
*/
|
|
struct target_cmd *targetcmds;
|
|
u_int8_t tqinfifonext;
|
|
|
|
/*
|
|
* Incoming and outgoing message handling.
|
|
*/
|
|
u_int8_t send_msg_perror;
|
|
ahc_msg_type msg_type;
|
|
u_int8_t msgout_buf[8]; /* Message we are sending */
|
|
u_int8_t msgin_buf[8]; /* Message we are receiving */
|
|
u_int msgout_len; /* Length of message to send */
|
|
u_int msgout_index; /* Current index in msgout */
|
|
u_int msgin_index; /* Current index in msgin */
|
|
|
|
int regs_res_type;
|
|
int regs_res_id;
|
|
int irq_res_type;
|
|
struct resource *regs;
|
|
struct resource *irq;
|
|
void *ih;
|
|
bus_dma_tag_t parent_dmat;
|
|
bus_dma_tag_t shared_data_dmat;
|
|
bus_dmamap_t shared_data_dmamap;
|
|
bus_addr_t shared_data_busaddr;
|
|
|
|
/* Number of enabled target mode device on this card */
|
|
u_int enabled_luns;
|
|
|
|
/* Initialization level of this data structure */
|
|
u_int init_level;
|
|
|
|
u_int16_t user_discenable;/* Disconnection allowed */
|
|
u_int16_t user_tagenable;/* Tagged Queuing allowed */
|
|
};
|
|
|
|
struct full_ahc_softc {
|
|
struct ahc_softc softc;
|
|
struct scb_data scb_data_storage;
|
|
};
|
|
|
|
/* #define AHC_DEBUG */
|
|
#ifdef AHC_DEBUG
|
|
/* Different debugging levels used when AHC_DEBUG is defined */
|
|
#define AHC_SHOWMISC 0x0001
|
|
#define AHC_SHOWCMDS 0x0002
|
|
#define AHC_SHOWSCBS 0x0004
|
|
#define AHC_SHOWABORTS 0x0008
|
|
#define AHC_SHOWSENSE 0x0010
|
|
#define AHC_SHOWSCBCNT 0x0020
|
|
|
|
extern int ahc_debug; /* Initialized in i386/scsi/aic7xxx.c */
|
|
#endif
|
|
|
|
char *ahc_name(struct ahc_softc *ahc);
|
|
|
|
struct ahc_softc*
|
|
ahc_alloc(device_t dev, struct resource *regs, int regs_type,
|
|
int regs_id, bus_dma_tag_t parent_dmat, ahc_chip chip,
|
|
ahc_feature features, ahc_flag flags,
|
|
struct scb_data *scb_data);
|
|
int ahc_reset(struct ahc_softc *ahc);
|
|
void ahc_free(struct ahc_softc *);
|
|
int ahc_probe_scbs(struct ahc_softc *);
|
|
int ahc_init(struct ahc_softc *);
|
|
int ahc_attach(struct ahc_softc *);
|
|
void ahc_intr(void *arg);
|
|
|
|
#define ahc_inb(ahc, port) \
|
|
bus_space_read_1((ahc)->tag, (ahc)->bsh, port)
|
|
|
|
#define ahc_outb(ahc, port, value) \
|
|
bus_space_write_1((ahc)->tag, (ahc)->bsh, port, value)
|
|
|
|
#define ahc_outsb(ahc, port, valp, count) \
|
|
bus_space_write_multi_1((ahc)->tag, (ahc)->bsh, port, valp, count)
|
|
|
|
#endif /* _AIC7XXX_H_ */
|