John Baldwin 7e9f73f3ed First pass at allowing memory to be mapped using cache modes other than ... WB (write-back) on x86 via control bits in PTEs and PDEs (including making use of the PAT MSR). Changes include: - A new pmap_mapdev_attr() function for amd64 and i386 which takes an additional parameter (relative to pmap_mapdev()) specifying the cache mode for this mapping. Note that on amd64 only WB mappings are done with the direct map, all other modes result in a private mapping. - pmap_mapdev() on i386 and amd64 now defaults to using UC (uncached) mappings rather than WB. Previously we relied on the BIOS setting up MTRR's to enforce memio regions being treated as UC. This might make hw.cbb_start_memory unnecessary in some cases now for example. - A new pmap_mapbios()/pmap_unmapbios() API has been added to allow places that used pmap_mapdev() to map non-device memory (such as ACPI tables) to do so using WB as before. - A new pmap_change_attr() function for amd64 and i386 that changes the caching mode for a range of KVA. Reviewed by: alc		2006-08-11 19:22:57 +00:00
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acpica
compile
conf	Remove sio(4) and related options from MI files to amd64, i386	2006-07-29 18:38:54 +00:00
disasm
ia32	Retire SYF_ARGMASK and remove both SYF_MPSAFE and SYF_ARGMASK. sy_narg is	2006-07-28 20:22:58 +00:00
ia64	Complete the transition from pmap_page_protect() to pmap_remove_write().	2006-08-01 19:06:06 +00:00
include	First pass at allowing memory to be mapped using cache modes other than	2006-08-11 19:22:57 +00:00
isa
pci