freebsd-dev/sys/sparc64/include/intr_machdep.h
Alexander Motin a157e42516 Refactor timer management code with priority to one-shot operation mode.
The main goal of this is to generate timer interrupts only when there is
some work to do. When CPU is busy interrupts are generating at full rate
of hz + stathz to fullfill scheduler and timekeeping requirements. But
when CPU is idle, only minimum set of interrupts (down to 8 interrupts per
second per CPU now), needed to handle scheduled callouts is executed.
This allows significantly increase idle CPU sleep time, increasing effect
of static power-saving technologies. Also it should reduce host CPU load
on virtualized systems, when guest system is idle.

There is set of tunables, also available as writable sysctls, allowing to
control wanted event timer subsystem behavior:
  kern.eventtimer.timer - allows to choose event timer hardware to use.
On x86 there is up to 4 different kinds of timers. Depending on whether
chosen timer is per-CPU, behavior of other options slightly differs.
  kern.eventtimer.periodic - allows to choose periodic and one-shot
operation mode. In periodic mode, current timer hardware taken as the only
source of time for time events. This mode is quite alike to previous kernel
behavior. One-shot mode instead uses currently selected time counter
hardware to schedule all needed events one by one and program timer to
generate interrupt exactly in specified time. Default value depends of
chosen timer capabilities, but one-shot mode is preferred, until other is
forced by user or hardware.
  kern.eventtimer.singlemul - in periodic mode specifies how much times
higher timer frequency should be, to not strictly alias hardclock() and
statclock() events. Default values are 2 and 4, but could be reduced to 1
if extra interrupts are unwanted.
  kern.eventtimer.idletick - makes each CPU to receive every timer interrupt
independently of whether they busy or not. By default this options is
disabled. If chosen timer is per-CPU and runs in periodic mode, this option
has no effect - all interrupts are generating.

As soon as this patch modifies cpu_idle() on some platforms, I have also
refactored one on x86. Now it makes use of MONITOR/MWAIT instrunctions
(if supported) under high sleep/wakeup rate, as fast alternative to other
methods. It allows SMP scheduler to wake up sleeping CPUs much faster
without using IPI, significantly increasing performance on some highly
task-switching loads.

Tested by:	many (on i386, amd64, sparc64 and powerc)
H/W donated by:	Gheorghe Ardelean
Sponsored by:	iXsystems, Inc.
2010-09-13 07:25:35 +00:00

112 lines
3.3 KiB
C

/*-
* Copyright (c) 2001 Jake Burkholder.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#ifndef _MACHINE_INTR_MACHDEP_H_
#define _MACHINE_INTR_MACHDEP_H_
#define IRSR_BUSY (1 << 5)
#define PIL_MAX (1 << 4)
#define IV_MAX (1 << 11)
#define IR_FREE (PIL_MAX * 2)
#define IH_SHIFT PTR_SHIFT
#define IQE_SHIFT 5
#define IV_SHIFT 6
#define PIL_LOW 1 /* stray interrupts */
#define PIL_ITHREAD 2 /* interrupts that use ithreads */
#define PIL_RENDEZVOUS 3 /* smp rendezvous ipi */
#define PIL_AST 4 /* ast ipi */
#define PIL_STOP 5 /* stop cpu ipi */
#define PIL_PREEMPT 6 /* preempt idle thread cpu ipi */
#define PIL_HARDCLOCK 7 /* hardclock broadcast */
#define PIL_FILTER 12 /* filter interrupts */
#define PIL_FAST 13 /* fast interrupts */
#define PIL_TICK 14 /* tick interrupts */
#ifndef LOCORE
struct trapframe;
typedef void ih_func_t(struct trapframe *);
typedef void iv_func_t(void *);
struct intr_request {
struct intr_request *ir_next;
iv_func_t *ir_func;
void *ir_arg;
u_int ir_vec;
u_int ir_pri;
};
struct intr_controller {
void (*ic_enable)(void *);
void (*ic_disable)(void *);
void (*ic_assign)(void *);
void (*ic_clear)(void *);
};
struct intr_vector {
iv_func_t *iv_func;
void *iv_arg;
const struct intr_controller *iv_ic;
void *iv_icarg;
struct intr_event *iv_event;
u_int iv_pri;
u_int iv_vec;
u_int iv_mid;
u_int iv_refcnt;
u_int iv_pad[2];
};
extern ih_func_t *intr_handlers[];
extern struct intr_vector intr_vectors[];
#ifdef SMP
void intr_add_cpu(u_int cpu);
#endif
int intr_bind(int vec, u_char cpu);
int intr_describe(int vec, void *ih, const char *descr);
void intr_setup(int level, ih_func_t *ihf, int pri, iv_func_t *ivf,
void *iva);
void intr_init1(void);
void intr_init2(void);
int intr_controller_register(int vec, const struct intr_controller *ic,
void *icarg);
int inthand_add(const char *name, int vec, int (*filt)(void *),
void (*handler)(void *), void *arg, int flags, void **cookiep);
int inthand_remove(int vec, void *cookie);
ih_func_t intr_fast;
#endif /* !LOCORE */
#endif /* !_MACHINE_INTR_MACHDEP_H_ */