61ae650d55
- It was decided to change the driver name to if_ixl for FreeBSD - This release adds the VF Driver to the tree, it can be built into the kernel or as the if_ixlv module - The VF driver is independent for the first time, this will be desireable when full SRIOV capability is added to the OS. - Thanks to my new coworker Eric Joyner for his superb work in both the core and vf driver code. Enjoy everyone! Submitted by: jack.vogel@intel.com and eric.joyner@intel.com MFC after: 3 days (hoping to make 10.1)
482 lines
15 KiB
C
Executable File
482 lines
15 KiB
C
Executable File
/******************************************************************************
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Copyright (c) 2013-2014, Intel Corporation
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice,
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this list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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3. Neither the name of the Intel Corporation nor the names of its
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contributors may be used to endorse or promote products derived from
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this software without specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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******************************************************************************/
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/*$FreeBSD$*/
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#include "i40e_prototype.h"
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/**
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* i40e_init_nvm_ops - Initialize NVM function pointers
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* @hw: pointer to the HW structure
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*
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* Setup the function pointers and the NVM info structure. Should be called
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* once per NVM initialization, e.g. inside the i40e_init_shared_code().
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* Please notice that the NVM term is used here (& in all methods covered
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* in this file) as an equivalent of the FLASH part mapped into the SR.
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* We are accessing FLASH always thru the Shadow RAM.
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**/
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enum i40e_status_code i40e_init_nvm(struct i40e_hw *hw)
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{
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struct i40e_nvm_info *nvm = &hw->nvm;
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enum i40e_status_code ret_code = I40E_SUCCESS;
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u32 fla, gens;
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u8 sr_size;
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DEBUGFUNC("i40e_init_nvm");
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/* The SR size is stored regardless of the nvm programming mode
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* as the blank mode may be used in the factory line.
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*/
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gens = rd32(hw, I40E_GLNVM_GENS);
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sr_size = ((gens & I40E_GLNVM_GENS_SR_SIZE_MASK) >>
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I40E_GLNVM_GENS_SR_SIZE_SHIFT);
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/* Switching to words (sr_size contains power of 2KB) */
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nvm->sr_size = (1 << sr_size) * I40E_SR_WORDS_IN_1KB;
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/* Check if we are in the normal or blank NVM programming mode */
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fla = rd32(hw, I40E_GLNVM_FLA);
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if (fla & I40E_GLNVM_FLA_LOCKED_MASK) { /* Normal programming mode */
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/* Max NVM timeout */
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nvm->timeout = I40E_MAX_NVM_TIMEOUT;
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nvm->blank_nvm_mode = FALSE;
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} else { /* Blank programming mode */
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nvm->blank_nvm_mode = TRUE;
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ret_code = I40E_ERR_NVM_BLANK_MODE;
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DEBUGOUT("NVM init error: unsupported blank mode.\n");
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}
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return ret_code;
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}
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/**
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* i40e_acquire_nvm - Generic request for acquiring the NVM ownership
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* @hw: pointer to the HW structure
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* @access: NVM access type (read or write)
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*
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* This function will request NVM ownership for reading
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* via the proper Admin Command.
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**/
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enum i40e_status_code i40e_acquire_nvm(struct i40e_hw *hw,
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enum i40e_aq_resource_access_type access)
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{
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enum i40e_status_code ret_code = I40E_SUCCESS;
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u64 gtime, timeout;
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u64 time = 0;
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DEBUGFUNC("i40e_acquire_nvm");
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if (hw->nvm.blank_nvm_mode)
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goto i40e_i40e_acquire_nvm_exit;
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ret_code = i40e_aq_request_resource(hw, I40E_NVM_RESOURCE_ID, access,
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0, &time, NULL);
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/* Reading the Global Device Timer */
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gtime = rd32(hw, I40E_GLVFGEN_TIMER);
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/* Store the timeout */
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hw->nvm.hw_semaphore_timeout = I40E_MS_TO_GTIME(time) + gtime;
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if (ret_code != I40E_SUCCESS) {
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/* Set the polling timeout */
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if (time > I40E_MAX_NVM_TIMEOUT)
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timeout = I40E_MS_TO_GTIME(I40E_MAX_NVM_TIMEOUT)
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+ gtime;
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else
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timeout = hw->nvm.hw_semaphore_timeout;
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/* Poll until the current NVM owner timeouts */
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while (gtime < timeout) {
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i40e_msec_delay(10);
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ret_code = i40e_aq_request_resource(hw,
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I40E_NVM_RESOURCE_ID,
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access, 0, &time,
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NULL);
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if (ret_code == I40E_SUCCESS) {
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hw->nvm.hw_semaphore_timeout =
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I40E_MS_TO_GTIME(time) + gtime;
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break;
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}
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gtime = rd32(hw, I40E_GLVFGEN_TIMER);
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}
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if (ret_code != I40E_SUCCESS) {
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hw->nvm.hw_semaphore_timeout = 0;
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hw->nvm.hw_semaphore_wait =
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I40E_MS_TO_GTIME(time) + gtime;
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DEBUGOUT1("NVM acquire timed out, wait %llu ms before trying again.\n",
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time);
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}
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}
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i40e_i40e_acquire_nvm_exit:
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return ret_code;
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}
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/**
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* i40e_release_nvm - Generic request for releasing the NVM ownership
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* @hw: pointer to the HW structure
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*
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* This function will release NVM resource via the proper Admin Command.
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**/
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void i40e_release_nvm(struct i40e_hw *hw)
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{
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DEBUGFUNC("i40e_release_nvm");
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if (!hw->nvm.blank_nvm_mode)
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i40e_aq_release_resource(hw, I40E_NVM_RESOURCE_ID, 0, NULL);
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}
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/**
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* i40e_poll_sr_srctl_done_bit - Polls the GLNVM_SRCTL done bit
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* @hw: pointer to the HW structure
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*
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* Polls the SRCTL Shadow RAM register done bit.
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**/
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static enum i40e_status_code i40e_poll_sr_srctl_done_bit(struct i40e_hw *hw)
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{
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enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
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u32 srctl, wait_cnt;
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DEBUGFUNC("i40e_poll_sr_srctl_done_bit");
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/* Poll the I40E_GLNVM_SRCTL until the done bit is set */
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for (wait_cnt = 0; wait_cnt < I40E_SRRD_SRCTL_ATTEMPTS; wait_cnt++) {
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srctl = rd32(hw, I40E_GLNVM_SRCTL);
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if (srctl & I40E_GLNVM_SRCTL_DONE_MASK) {
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ret_code = I40E_SUCCESS;
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break;
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}
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i40e_usec_delay(5);
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}
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if (ret_code == I40E_ERR_TIMEOUT)
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DEBUGOUT("Done bit in GLNVM_SRCTL not set");
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return ret_code;
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}
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/**
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* i40e_read_nvm_word - Reads Shadow RAM
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF)
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* @data: word read from the Shadow RAM
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*
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* Reads one 16 bit word from the Shadow RAM using the GLNVM_SRCTL register.
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**/
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enum i40e_status_code i40e_read_nvm_word(struct i40e_hw *hw, u16 offset,
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u16 *data)
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{
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enum i40e_status_code ret_code = I40E_ERR_TIMEOUT;
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u32 sr_reg;
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DEBUGFUNC("i40e_read_nvm_srctl");
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if (offset >= hw->nvm.sr_size) {
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DEBUGOUT("NVM read error: Offset beyond Shadow RAM limit.\n");
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ret_code = I40E_ERR_PARAM;
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goto read_nvm_exit;
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}
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/* Poll the done bit first */
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ret_code = i40e_poll_sr_srctl_done_bit(hw);
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if (ret_code == I40E_SUCCESS) {
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/* Write the address and start reading */
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sr_reg = (u32)(offset << I40E_GLNVM_SRCTL_ADDR_SHIFT) |
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(1 << I40E_GLNVM_SRCTL_START_SHIFT);
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wr32(hw, I40E_GLNVM_SRCTL, sr_reg);
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/* Poll I40E_GLNVM_SRCTL until the done bit is set */
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ret_code = i40e_poll_sr_srctl_done_bit(hw);
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if (ret_code == I40E_SUCCESS) {
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sr_reg = rd32(hw, I40E_GLNVM_SRDATA);
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*data = (u16)((sr_reg &
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I40E_GLNVM_SRDATA_RDDATA_MASK)
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>> I40E_GLNVM_SRDATA_RDDATA_SHIFT);
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}
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}
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if (ret_code != I40E_SUCCESS)
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DEBUGOUT1("NVM read error: Couldn't access Shadow RAM address: 0x%x\n",
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offset);
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read_nvm_exit:
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return ret_code;
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}
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/**
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* i40e_read_nvm_buffer - Reads Shadow RAM buffer
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to read (0x000000 - 0x001FFF).
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* @words: (in) number of words to read; (out) number of words actually read
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* @data: words read from the Shadow RAM
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*
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* Reads 16 bit words (data buffer) from the SR using the i40e_read_nvm_srrd()
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* method. The buffer read is preceded by the NVM ownership take
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* and followed by the release.
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**/
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enum i40e_status_code i40e_read_nvm_buffer(struct i40e_hw *hw, u16 offset,
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u16 *words, u16 *data)
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{
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enum i40e_status_code ret_code = I40E_SUCCESS;
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u16 index, word;
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DEBUGFUNC("i40e_read_nvm_buffer");
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/* Loop thru the selected region */
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for (word = 0; word < *words; word++) {
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index = offset + word;
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ret_code = i40e_read_nvm_word(hw, index, &data[word]);
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if (ret_code != I40E_SUCCESS)
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break;
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}
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/* Update the number of words read from the Shadow RAM */
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*words = word;
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return ret_code;
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}
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/**
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* i40e_write_nvm_aq - Writes Shadow RAM.
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* @hw: pointer to the HW structure.
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* @module_pointer: module pointer location in words from the NVM beginning
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* @offset: offset in words from module start
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* @words: number of words to write
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* @data: buffer with words to write to the Shadow RAM
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* @last_command: tells the AdminQ that this is the last command
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*
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* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
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**/
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enum i40e_status_code i40e_write_nvm_aq(struct i40e_hw *hw, u8 module_pointer,
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u32 offset, u16 words, void *data,
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bool last_command)
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{
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enum i40e_status_code ret_code = I40E_ERR_NVM;
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DEBUGFUNC("i40e_write_nvm_aq");
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/* Here we are checking the SR limit only for the flat memory model.
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* We cannot do it for the module-based model, as we did not acquire
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* the NVM resource yet (we cannot get the module pointer value).
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* Firmware will check the module-based model.
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*/
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if ((offset + words) > hw->nvm.sr_size)
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DEBUGOUT("NVM write error: offset beyond Shadow RAM limit.\n");
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else if (words > I40E_SR_SECTOR_SIZE_IN_WORDS)
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/* We can write only up to 4KB (one sector), in one AQ write */
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DEBUGOUT("NVM write fail error: cannot write more than 4KB in a single write.\n");
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else if (((offset + (words - 1)) / I40E_SR_SECTOR_SIZE_IN_WORDS)
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!= (offset / I40E_SR_SECTOR_SIZE_IN_WORDS))
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/* A single write cannot spread over two sectors */
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DEBUGOUT("NVM write error: cannot spread over two sectors in a single write.\n");
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else
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ret_code = i40e_aq_update_nvm(hw, module_pointer,
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2 * offset, /*bytes*/
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2 * words, /*bytes*/
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data, last_command, NULL);
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return ret_code;
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}
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/**
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* i40e_write_nvm_word - Writes Shadow RAM word
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* @hw: pointer to the HW structure
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* @offset: offset of the Shadow RAM word to write
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* @data: word to write to the Shadow RAM
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*
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* Writes a 16 bit word to the SR using the i40e_write_nvm_aq() method.
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* NVM ownership have to be acquired and released (on ARQ completion event
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* reception) by caller. To commit SR to NVM update checksum function
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* should be called.
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**/
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enum i40e_status_code i40e_write_nvm_word(struct i40e_hw *hw, u32 offset,
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void *data)
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{
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DEBUGFUNC("i40e_write_nvm_word");
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/* Value 0x00 below means that we treat SR as a flat mem */
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return i40e_write_nvm_aq(hw, 0x00, offset, 1, data, FALSE);
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}
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/**
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* i40e_write_nvm_buffer - Writes Shadow RAM buffer
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* @hw: pointer to the HW structure
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* @module_pointer: module pointer location in words from the NVM beginning
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* @offset: offset of the Shadow RAM buffer to write
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* @words: number of words to write
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* @data: words to write to the Shadow RAM
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*
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* Writes a 16 bit words buffer to the Shadow RAM using the admin command.
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* NVM ownership must be acquired before calling this function and released
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* on ARQ completion event reception by caller. To commit SR to NVM update
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* checksum function should be called.
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**/
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enum i40e_status_code i40e_write_nvm_buffer(struct i40e_hw *hw,
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u8 module_pointer, u32 offset,
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u16 words, void *data)
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{
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DEBUGFUNC("i40e_write_nvm_buffer");
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/* Here we will only write one buffer as the size of the modules
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* mirrored in the Shadow RAM is always less than 4K.
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*/
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return i40e_write_nvm_aq(hw, module_pointer, offset, words,
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data, FALSE);
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}
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/**
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* i40e_calc_nvm_checksum - Calculates and returns the checksum
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* @hw: pointer to hardware structure
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* @checksum: pointer to the checksum
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*
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* This function calculates SW Checksum that covers the whole 64kB shadow RAM
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* except the VPD and PCIe ALT Auto-load modules. The structure and size of VPD
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* is customer specific and unknown. Therefore, this function skips all maximum
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* possible size of VPD (1kB).
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**/
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enum i40e_status_code i40e_calc_nvm_checksum(struct i40e_hw *hw, u16 *checksum)
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{
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enum i40e_status_code ret_code = I40E_SUCCESS;
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u16 pcie_alt_module = 0;
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u16 checksum_local = 0;
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u16 vpd_module = 0;
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u16 word = 0;
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u32 i = 0;
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DEBUGFUNC("i40e_calc_nvm_checksum");
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/* read pointer to VPD area */
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ret_code = i40e_read_nvm_word(hw, I40E_SR_VPD_PTR, &vpd_module);
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if (ret_code != I40E_SUCCESS) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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/* read pointer to PCIe Alt Auto-load module */
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ret_code = i40e_read_nvm_word(hw, I40E_SR_PCIE_ALT_AUTO_LOAD_PTR,
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&pcie_alt_module);
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if (ret_code != I40E_SUCCESS) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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/* Calculate SW checksum that covers the whole 64kB shadow RAM
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* except the VPD and PCIe ALT Auto-load modules
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*/
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for (i = 0; i < hw->nvm.sr_size; i++) {
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/* Skip Checksum word */
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if (i == I40E_SR_SW_CHECKSUM_WORD)
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i++;
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/* Skip VPD module (convert byte size to word count) */
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if (i == (u32)vpd_module) {
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i += (I40E_SR_VPD_MODULE_MAX_SIZE / 2);
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if (i >= hw->nvm.sr_size)
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break;
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}
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/* Skip PCIe ALT module (convert byte size to word count) */
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if (i == (u32)pcie_alt_module) {
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i += (I40E_SR_PCIE_ALT_MODULE_MAX_SIZE / 2);
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if (i >= hw->nvm.sr_size)
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break;
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}
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ret_code = i40e_read_nvm_word(hw, (u16)i, &word);
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if (ret_code != I40E_SUCCESS) {
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ret_code = I40E_ERR_NVM_CHECKSUM;
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goto i40e_calc_nvm_checksum_exit;
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}
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checksum_local += word;
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}
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*checksum = (u16)I40E_SR_SW_CHECKSUM_BASE - checksum_local;
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i40e_calc_nvm_checksum_exit:
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return ret_code;
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}
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/**
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* i40e_update_nvm_checksum - Updates the NVM checksum
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* @hw: pointer to hardware structure
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*
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* NVM ownership must be acquired before calling this function and released
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* on ARQ completion event reception by caller.
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* This function will commit SR to NVM.
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**/
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enum i40e_status_code i40e_update_nvm_checksum(struct i40e_hw *hw)
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{
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enum i40e_status_code ret_code = I40E_SUCCESS;
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u16 checksum;
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DEBUGFUNC("i40e_update_nvm_checksum");
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ret_code = i40e_calc_nvm_checksum(hw, &checksum);
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if (ret_code == I40E_SUCCESS)
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ret_code = i40e_write_nvm_aq(hw, 0x00, I40E_SR_SW_CHECKSUM_WORD,
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1, &checksum, TRUE);
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return ret_code;
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}
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/**
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* i40e_validate_nvm_checksum - Validate EEPROM checksum
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* @hw: pointer to hardware structure
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* @checksum: calculated checksum
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|
*
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|
* Performs checksum calculation and validates the NVM SW checksum. If the
|
|
* caller does not need checksum, the value can be NULL.
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|
**/
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|
enum i40e_status_code i40e_validate_nvm_checksum(struct i40e_hw *hw,
|
|
u16 *checksum)
|
|
{
|
|
enum i40e_status_code ret_code = I40E_SUCCESS;
|
|
u16 checksum_sr = 0;
|
|
u16 checksum_local = 0;
|
|
|
|
DEBUGFUNC("i40e_validate_nvm_checksum");
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|
|
|
ret_code = i40e_calc_nvm_checksum(hw, &checksum_local);
|
|
if (ret_code != I40E_SUCCESS)
|
|
goto i40e_validate_nvm_checksum_exit;
|
|
|
|
/* Do not use i40e_read_nvm_word() because we do not want to take
|
|
* the synchronization semaphores twice here.
|
|
*/
|
|
i40e_read_nvm_word(hw, I40E_SR_SW_CHECKSUM_WORD, &checksum_sr);
|
|
|
|
/* Verify read checksum from EEPROM is the same as
|
|
* calculated checksum
|
|
*/
|
|
if (checksum_local != checksum_sr)
|
|
ret_code = I40E_ERR_NVM_CHECKSUM;
|
|
|
|
/* If the user cares, return the calculated checksum */
|
|
if (checksum)
|
|
*checksum = checksum_local;
|
|
|
|
i40e_validate_nvm_checksum_exit:
|
|
return ret_code;
|
|
}
|