851 lines
21 KiB
C
851 lines
21 KiB
C
/*-
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* Copyright (c) 1998 Doug Rabson
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $Id: cia.c,v 1.16 1999/04/16 21:21:39 peter Exp $
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*/
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/*-
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* Copyright (c) 1998 The NetBSD Foundation, Inc.
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* All rights reserved.
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*
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* This code is derived from software contributed to The NetBSD Foundation
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* by Jason R. Thorpe of the Numerical Aerospace Simulation Facility,
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* NASA Ames Research Center.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the NetBSD
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* Foundation, Inc. and its contributors.
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* 4. Neither the name of The NetBSD Foundation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Copyright (c) 1995, 1996 Carnegie-Mellon University.
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* All rights reserved.
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*
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* Author: Chris G. Demetriou
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*
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* Permission to use, copy, modify and distribute this software and
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* its documentation is hereby granted, provided that both the copyright
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* notice and this permission notice appear in all copies of the
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* software, derivative works or modified versions, and any portions
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* thereof, and that both notices appear in supporting documentation.
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*
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* CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS"
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* CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND
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* FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE.
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*
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* Carnegie Mellon requests users of this software to return to
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*
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* Software Distribution Coordinator or Software.Distribution@CS.CMU.EDU
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* School of Computer Science
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* Carnegie Mellon University
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* Pittsburgh PA 15213-3890
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*
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* any improvements or extensions that they make and grant Carnegie the
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* rights to redistribute these changes.
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*/
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#include "opt_cpu.h"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/bus.h>
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#include <machine/bus.h>
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#include <sys/rman.h>
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#include <alpha/pci/ciareg.h>
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#include <alpha/pci/ciavar.h>
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#include <alpha/pci/pcibus.h>
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#include <machine/bwx.h>
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#include <machine/swiz.h>
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#include <machine/intr.h>
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#include <machine/intrcnt.h>
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#include <machine/cpuconf.h>
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#include <machine/rpb.h>
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#include <machine/resource.h>
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#define KV(pa) ALPHA_PHYS_TO_K0SEG(pa)
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static devclass_t cia_devclass;
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static device_t cia0; /* XXX only one for now */
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static u_int32_t cia_hae_mem;
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static int cia_rev, cia_ispyxis, cia_config;
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struct cia_softc {
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int junk; /* no softc */
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};
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#define CIA_SOFTC(dev) (struct cia_softc*) device_get_softc(dev)
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static alpha_chipset_inb_t cia_bwx_inb, cia_swiz_inb;
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static alpha_chipset_inw_t cia_bwx_inw, cia_swiz_inw;
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static alpha_chipset_inl_t cia_bwx_inl, cia_swiz_inl;
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static alpha_chipset_outb_t cia_bwx_outb, cia_swiz_outb;
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static alpha_chipset_outw_t cia_bwx_outw, cia_swiz_outw;
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static alpha_chipset_outl_t cia_bwx_outl, cia_swiz_outl;
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static alpha_chipset_readb_t cia_bwx_readb, cia_swiz_readb;
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static alpha_chipset_readw_t cia_bwx_readw, cia_swiz_readw;
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static alpha_chipset_readl_t cia_bwx_readl, cia_swiz_readl;
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static alpha_chipset_writeb_t cia_bwx_writeb, cia_swiz_writeb;
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static alpha_chipset_writew_t cia_bwx_writew, cia_swiz_writew;
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static alpha_chipset_writel_t cia_bwx_writel, cia_swiz_writel;
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static alpha_chipset_maxdevs_t cia_bwx_maxdevs, cia_swiz_maxdevs;
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static alpha_chipset_cfgreadb_t cia_bwx_cfgreadb, cia_swiz_cfgreadb;
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static alpha_chipset_cfgreadw_t cia_bwx_cfgreadw, cia_swiz_cfgreadw;
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static alpha_chipset_cfgreadl_t cia_bwx_cfgreadl, cia_swiz_cfgreadl;
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static alpha_chipset_cfgwriteb_t cia_bwx_cfgwriteb, cia_swiz_cfgwriteb;
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static alpha_chipset_cfgwritew_t cia_bwx_cfgwritew, cia_swiz_cfgwritew;
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static alpha_chipset_cfgwritel_t cia_bwx_cfgwritel, cia_swiz_cfgwritel;
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static alpha_chipset_addrcvt_t cia_cvt_dense, cia_cvt_bwx;
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static alpha_chipset_read_hae_t cia_read_hae;
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static alpha_chipset_write_hae_t cia_write_hae;
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static alpha_chipset_t cia_bwx_chipset = {
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cia_bwx_inb,
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cia_bwx_inw,
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cia_bwx_inl,
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cia_bwx_outb,
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cia_bwx_outw,
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cia_bwx_outl,
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cia_bwx_readb,
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cia_bwx_readw,
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cia_bwx_readl,
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cia_bwx_writeb,
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cia_bwx_writew,
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cia_bwx_writel,
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cia_bwx_maxdevs,
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cia_bwx_cfgreadb,
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cia_bwx_cfgreadw,
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cia_bwx_cfgreadl,
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cia_bwx_cfgwriteb,
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cia_bwx_cfgwritew,
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cia_bwx_cfgwritel,
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cia_cvt_dense,
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cia_cvt_bwx,
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cia_read_hae,
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cia_write_hae,
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};
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static alpha_chipset_t cia_swiz_chipset = {
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cia_swiz_inb,
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cia_swiz_inw,
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cia_swiz_inl,
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cia_swiz_outb,
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cia_swiz_outw,
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cia_swiz_outl,
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cia_swiz_readb,
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cia_swiz_readw,
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cia_swiz_readl,
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cia_swiz_writeb,
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cia_swiz_writew,
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cia_swiz_writel,
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cia_swiz_maxdevs,
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cia_swiz_cfgreadb,
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cia_swiz_cfgreadw,
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cia_swiz_cfgreadl,
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cia_swiz_cfgwriteb,
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cia_swiz_cfgwritew,
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cia_swiz_cfgwritel,
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cia_cvt_dense,
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NULL,
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cia_read_hae,
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cia_write_hae,
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};
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static u_int8_t
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cia_bwx_inb(u_int32_t port)
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{
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alpha_mb();
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return ldbu(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port));
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}
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static u_int16_t
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cia_bwx_inw(u_int32_t port)
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{
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alpha_mb();
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return ldwu(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port));
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}
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static u_int32_t
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cia_bwx_inl(u_int32_t port)
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{
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alpha_mb();
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return ldl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port));
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}
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static void
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cia_bwx_outb(u_int32_t port, u_int8_t data)
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{
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stb(KV(CIA_EV56_BWIO+BWX_EV56_INT1 + port), data);
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alpha_wmb();
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}
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static void
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cia_bwx_outw(u_int32_t port, u_int16_t data)
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{
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stw(KV(CIA_EV56_BWIO+BWX_EV56_INT2 + port), data);
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alpha_wmb();
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}
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static void
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cia_bwx_outl(u_int32_t port, u_int32_t data)
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{
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stl(KV(CIA_EV56_BWIO+BWX_EV56_INT4 + port), data);
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alpha_wmb();
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}
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static u_int8_t
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cia_bwx_readb(u_int32_t pa)
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{
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alpha_mb();
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return ldbu(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa));
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}
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static u_int16_t
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cia_bwx_readw(u_int32_t pa)
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{
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alpha_mb();
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return ldwu(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa));
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}
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static u_int32_t
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cia_bwx_readl(u_int32_t pa)
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{
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alpha_mb();
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return ldl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa));
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}
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static void
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cia_bwx_writeb(u_int32_t pa, u_int8_t data)
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{
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stb(KV(CIA_EV56_BWMEM+BWX_EV56_INT1 + pa), data);
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alpha_wmb();
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}
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static void
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cia_bwx_writew(u_int32_t pa, u_int16_t data)
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{
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stw(KV(CIA_EV56_BWMEM+BWX_EV56_INT2 + pa), data);
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alpha_wmb();
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}
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static void
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cia_bwx_writel(u_int32_t pa, u_int32_t data)
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{
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stl(KV(CIA_EV56_BWMEM+BWX_EV56_INT4 + pa), data);
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alpha_wmb();
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}
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static int
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cia_bwx_maxdevs(u_int b)
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{
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return 12; /* XXX */
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}
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static void
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cia_clear_abort(void)
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{
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/*
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* Some (apparently-common) revisions of EB164 and AlphaStation
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* firmware do the Wrong thing with PCI master and target aborts,
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* which are caused by accesing the configuration space of devices
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* that don't exist (for example).
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*
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* To work around this, we clear the CIA error register's PCI
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* master and target abort bits before touching PCI configuration
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* space and check it afterwards. If it indicates a master or target
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* abort, the device wasn't there so we return 0xffffffff.
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*/
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REGVAL(CIA_CSR_CIA_ERR) = CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT;
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alpha_mb();
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alpha_pal_draina();
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}
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static int
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cia_check_abort(void)
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{
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u_int32_t errbits;
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int ba = 0;
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alpha_pal_draina();
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alpha_mb();
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errbits = REGVAL(CIA_CSR_CIA_ERR);
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if (errbits & (CIA_ERR_RCVD_MAS_ABT|CIA_ERR_RCVD_TAR_ABT))
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ba = 1;
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if (errbits) {
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REGVAL(CIA_CSR_CIA_ERR) = errbits;
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alpha_mb();
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alpha_pal_draina();
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}
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return ba;
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}
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#define CIA_BWX_CFGADDR(b, s, f, r) \
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KV(((b) ? CIA_EV56_BWCONF1 : CIA_EV56_BWCONF0) \
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| ((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
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static u_int8_t
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cia_bwx_cfgreadb(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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u_int8_t data;
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cia_clear_abort();
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if (badaddr((caddr_t)va, 1)) {
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cia_check_abort();
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return ~0;
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}
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data = ldbu(va+BWX_EV56_INT1);
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if (cia_check_abort())
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return ~0;
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return data;
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}
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static u_int16_t
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cia_bwx_cfgreadw(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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u_int16_t data;
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cia_clear_abort();
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if (badaddr((caddr_t)va, 2)) {
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cia_check_abort();
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return ~0;
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}
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data = ldwu(va+BWX_EV56_INT2);
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if (cia_check_abort())
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return ~0;
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return data;
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}
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static u_int32_t
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cia_bwx_cfgreadl(u_int b, u_int s, u_int f, u_int r)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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u_int32_t data;
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cia_clear_abort();
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if (badaddr((caddr_t)va, 4)) {
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cia_check_abort();
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return ~0;
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}
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data = ldl(va+BWX_EV56_INT4);
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if (cia_check_abort())
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return ~0;
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return data;
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}
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static void
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cia_bwx_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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cia_clear_abort();
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if (badaddr((caddr_t)va, 1)) return;
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stb(va+BWX_EV56_INT1, data);
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cia_check_abort();
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}
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static void
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cia_bwx_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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if (badaddr((caddr_t)va, 2)) return;
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stw(va+BWX_EV56_INT2, data);
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cia_check_abort();
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}
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static void
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cia_bwx_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
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{
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vm_offset_t va = CIA_BWX_CFGADDR(b, s, f, r);
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if (badaddr((caddr_t)va, 4)) return;
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stl(va+BWX_EV56_INT4, data);
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cia_check_abort();
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}
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static u_int8_t
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cia_swiz_inb(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_BYTE(KV(CIA_PCI_SIO1), port);
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}
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static u_int16_t
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cia_swiz_inw(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_WORD(KV(CIA_PCI_SIO1), port);
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}
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static u_int32_t
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cia_swiz_inl(u_int32_t port)
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{
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alpha_mb();
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return SPARSE_READ_LONG(KV(CIA_PCI_SIO1), port);
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}
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static void
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cia_swiz_outb(u_int32_t port, u_int8_t data)
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{
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SPARSE_WRITE_BYTE(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static void
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cia_swiz_outw(u_int32_t port, u_int16_t data)
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{
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SPARSE_WRITE_WORD(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static void
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cia_swiz_outl(u_int32_t port, u_int32_t data)
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{
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SPARSE_WRITE_LONG(KV(CIA_PCI_SIO1), port, data);
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alpha_wmb();
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}
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static __inline void
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cia_swiz_set_hae_mem(u_int32_t *pa)
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{
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/* Only bother with region 1 */
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#define REG1 (7 << 29)
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if ((cia_hae_mem & REG1) != (*pa & REG1)) {
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/*
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* Seems fairly paranoid but this is what Linux does...
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*/
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u_int32_t msb = *pa & REG1;
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int s = splhigh();
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cia_hae_mem = (cia_hae_mem & ~REG1) | msb;
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REGVAL(CIA_CSR_HAE_MEM) = cia_hae_mem;
|
|
alpha_mb();
|
|
cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
|
|
splx(s);
|
|
*pa -= msb;
|
|
}
|
|
}
|
|
|
|
static u_int8_t
|
|
cia_swiz_readb(u_int32_t pa)
|
|
{
|
|
alpha_mb();
|
|
cia_swiz_set_hae_mem(&pa);
|
|
return SPARSE_READ_BYTE(KV(CIA_PCI_SMEM1), pa);
|
|
}
|
|
|
|
static u_int16_t
|
|
cia_swiz_readw(u_int32_t pa)
|
|
{
|
|
alpha_mb();
|
|
cia_swiz_set_hae_mem(&pa);
|
|
return SPARSE_READ_WORD(KV(CIA_PCI_SMEM1), pa);
|
|
}
|
|
|
|
static u_int32_t
|
|
cia_swiz_readl(u_int32_t pa)
|
|
{
|
|
alpha_mb();
|
|
cia_swiz_set_hae_mem(&pa);
|
|
return SPARSE_READ_LONG(KV(CIA_PCI_SMEM1), pa);
|
|
}
|
|
|
|
static void
|
|
cia_swiz_writeb(u_int32_t pa, u_int8_t data)
|
|
{
|
|
cia_swiz_set_hae_mem(&pa);
|
|
SPARSE_WRITE_BYTE(KV(CIA_PCI_SMEM1), pa, data);
|
|
alpha_wmb();
|
|
}
|
|
|
|
static void
|
|
cia_swiz_writew(u_int32_t pa, u_int16_t data)
|
|
{
|
|
cia_swiz_set_hae_mem(&pa);
|
|
SPARSE_WRITE_WORD(KV(CIA_PCI_SMEM1), pa, data);
|
|
alpha_wmb();
|
|
}
|
|
|
|
static void
|
|
cia_swiz_writel(u_int32_t pa, u_int32_t data)
|
|
{
|
|
cia_swiz_set_hae_mem(&pa);
|
|
SPARSE_WRITE_LONG(KV(CIA_PCI_SMEM1), pa, data);
|
|
alpha_wmb();
|
|
}
|
|
|
|
static int
|
|
cia_swiz_maxdevs(u_int b)
|
|
{
|
|
return 12; /* XXX */
|
|
}
|
|
|
|
#define CIA_SWIZ_CFGOFF(b, s, f, r) \
|
|
(((b) << 16) | ((s) << 11) | ((f) << 8) | (r))
|
|
|
|
/* when doing a type 1 pci configuration space access, we
|
|
* must set a bit in the CIA_CSR_CFG register & clear it
|
|
* when we're done
|
|
*/
|
|
|
|
#define CIA_TYPE1_SETUP(b,s,old_cfg) if((b)) { \
|
|
do { \
|
|
(s) = splhigh(); \
|
|
(old_cfg) = REGVAL(CIA_CSR_CFG); \
|
|
alpha_mb(); \
|
|
REGVAL(CIA_CSR_CFG) = (old_cfg) | 0x1; \
|
|
alpha_mb(); \
|
|
} while(0); \
|
|
}
|
|
|
|
#define CIA_TYPE1_TEARDOWN(b,s,old_cfg) if((b)) { \
|
|
do { \
|
|
alpha_mb(); \
|
|
REGVAL(CIA_CSR_CFG) = (old_cfg); \
|
|
alpha_mb(); \
|
|
splx((s)); \
|
|
} while(0); \
|
|
}
|
|
|
|
#define SWIZ_CFGREAD(b, s, f, r, width, type) \
|
|
type val = ~0; \
|
|
int ipl = 0; \
|
|
u_int32_t old_cfg = 0; \
|
|
vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
|
|
vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(CIA_PCI_CONF), off); \
|
|
alpha_mb(); \
|
|
CIA_TYPE1_SETUP(b,ipl,old_cfg); \
|
|
if (!badaddr((caddr_t)kv, sizeof(type))) { \
|
|
val = SPARSE_##width##_EXTRACT(off, SPARSE_READ(kv)); \
|
|
} \
|
|
CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
|
|
return val;
|
|
|
|
#define SWIZ_CFGWRITE(b, s, f, r, data, width, type) \
|
|
int ipl = 0; \
|
|
u_int32_t old_cfg = 0; \
|
|
vm_offset_t off = CIA_SWIZ_CFGOFF(b, s, f, r); \
|
|
vm_offset_t kv = SPARSE_##width##_ADDRESS(KV(CIA_PCI_CONF), off); \
|
|
alpha_mb(); \
|
|
CIA_TYPE1_SETUP(b,ipl,old_cfg); \
|
|
if (!badaddr((caddr_t)kv, sizeof(type))) { \
|
|
SPARSE_WRITE(kv, SPARSE_##width##_INSERT(off, data)); \
|
|
alpha_wmb(); \
|
|
} \
|
|
CIA_TYPE1_TEARDOWN(b,ipl,old_cfg); \
|
|
return;
|
|
|
|
static u_int8_t
|
|
cia_swiz_cfgreadb(u_int b, u_int s, u_int f, u_int r)
|
|
{
|
|
SWIZ_CFGREAD(b, s, f, r, BYTE, u_int8_t);
|
|
}
|
|
|
|
static u_int16_t
|
|
cia_swiz_cfgreadw(u_int b, u_int s, u_int f, u_int r)
|
|
{
|
|
SWIZ_CFGREAD(b, s, f, r, WORD, u_int16_t);
|
|
}
|
|
|
|
static u_int32_t
|
|
cia_swiz_cfgreadl(u_int b, u_int s, u_int f, u_int r)
|
|
{
|
|
SWIZ_CFGREAD(b, s, f, r, LONG, u_int32_t);
|
|
}
|
|
|
|
static void
|
|
cia_swiz_cfgwriteb(u_int b, u_int s, u_int f, u_int r, u_int8_t data)
|
|
{
|
|
SWIZ_CFGWRITE(b, s, f, r, data, BYTE, u_int8_t);
|
|
}
|
|
|
|
static void
|
|
cia_swiz_cfgwritew(u_int b, u_int s, u_int f, u_int r, u_int16_t data)
|
|
{
|
|
SWIZ_CFGWRITE(b, s, f, r, data, WORD, u_int16_t);
|
|
}
|
|
|
|
static void
|
|
cia_swiz_cfgwritel(u_int b, u_int s, u_int f, u_int r, u_int32_t data)
|
|
{
|
|
SWIZ_CFGWRITE(b, s, f, r, data, LONG, u_int32_t);
|
|
}
|
|
|
|
vm_offset_t
|
|
cia_cvt_dense(vm_offset_t addr)
|
|
{
|
|
addr &= 0xffffffffUL;
|
|
return (addr | CIA_PCI_DENSE);
|
|
|
|
}
|
|
|
|
vm_offset_t
|
|
cia_cvt_bwx(vm_offset_t addr)
|
|
{
|
|
addr &= 0xffffffffUL;
|
|
return (addr |= CIA_EV56_BWMEM);
|
|
}
|
|
|
|
static u_int64_t
|
|
cia_read_hae(void)
|
|
{
|
|
return cia_hae_mem & REG1;
|
|
}
|
|
|
|
static void
|
|
cia_write_hae(u_int64_t hae)
|
|
{
|
|
u_int32_t pa = hae;
|
|
cia_swiz_set_hae_mem(&pa);
|
|
}
|
|
|
|
static int cia_probe(device_t dev);
|
|
static int cia_attach(device_t dev);
|
|
static int cia_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags,
|
|
driver_intr_t *intr, void *arg, void **cookiep);
|
|
static int cia_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie);
|
|
|
|
static device_method_t cia_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, cia_probe),
|
|
DEVMETHOD(device_attach, cia_attach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_print_child, bus_generic_print_child),
|
|
DEVMETHOD(bus_alloc_resource, pci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, pci_release_resource),
|
|
DEVMETHOD(bus_activate_resource, pci_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, pci_deactivate_resource),
|
|
DEVMETHOD(bus_setup_intr, cia_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, cia_teardown_intr),
|
|
|
|
{ 0, 0 }
|
|
};
|
|
|
|
static driver_t cia_driver = {
|
|
"cia",
|
|
cia_methods,
|
|
sizeof(struct cia_softc),
|
|
};
|
|
|
|
void
|
|
cia_init()
|
|
{
|
|
static int initted = 0;
|
|
|
|
if (initted) return;
|
|
initted = 1;
|
|
|
|
cia_rev = REGVAL(CIA_CSR_REV) & REV_MASK;
|
|
|
|
/*
|
|
* Determine if we have a Pyxis. Only two systypes can
|
|
* have this: the EB164 systype (AlphaPC164LX and AlphaPC164SX)
|
|
* and the DEC_ST550 systype (Miata).
|
|
*/
|
|
if ((hwrpb->rpb_type == ST_EB164 &&
|
|
(hwrpb->rpb_variation & SV_ST_MASK) >= SV_ST_ALPHAPC164LX_400) ||
|
|
hwrpb->rpb_type == ST_DEC_550)
|
|
cia_ispyxis = TRUE;
|
|
else
|
|
cia_ispyxis = FALSE;
|
|
|
|
/*
|
|
* ALCOR/ALCOR2 Revisions >= 2 and Pyxis have the CNFG register.
|
|
*/
|
|
if (cia_rev >= 2 || cia_ispyxis)
|
|
cia_config = REGVAL(CIA_CSR_CNFG);
|
|
else
|
|
cia_config = 0;
|
|
|
|
if (alpha_implver() != ALPHA_IMPLVER_EV5
|
|
|| alpha_amask(ALPHA_AMASK_BWX)
|
|
|| !(cia_config & CNFG_BWEN))
|
|
chipset = cia_swiz_chipset;
|
|
else
|
|
chipset = cia_bwx_chipset;
|
|
cia_hae_mem = REGVAL(CIA_CSR_HAE_MEM);
|
|
|
|
#if 0
|
|
chipset = cia_swiz_chipset; /* XXX */
|
|
cia_ispyxis = 0;
|
|
#endif
|
|
|
|
if (platform.pci_intr_init)
|
|
platform.pci_intr_init();
|
|
}
|
|
|
|
static int
|
|
cia_probe(device_t dev)
|
|
{
|
|
if (cia0)
|
|
return ENXIO;
|
|
cia0 = dev;
|
|
device_set_desc(dev, "2117x Core Logic chipset"); /* XXX */
|
|
|
|
pci_init_resources();
|
|
isa_init_intr();
|
|
|
|
device_add_child(dev, "pcib", 0, 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
cia_attach(device_t dev)
|
|
{
|
|
char* name;
|
|
int pass;
|
|
|
|
cia_init();
|
|
|
|
name = cia_ispyxis ? "Pyxis" : "ALCOR/ALCOR2";
|
|
if (cia_ispyxis) {
|
|
name = "Pyxis";
|
|
pass = cia_rev;
|
|
} else {
|
|
name = "ALCOR/ALCOR2";
|
|
pass = cia_rev+1;
|
|
}
|
|
printf("cia0: %s, pass %d\n", name, pass);
|
|
if (cia_config)
|
|
printf("cia0: extended capabilities: %b\n",
|
|
cia_config, CIA_CSR_CNFG_BITS);
|
|
|
|
#ifdef DEC_ST550
|
|
if (hwrpb->rpb_type == ST_DEC_550 &&
|
|
(hwrpb->rpb_variation & SV_ST_MASK) < SV_ST_MIATA_1_5) {
|
|
/*
|
|
* Miata 1 systems have a bug: DMA cannot cross
|
|
* an 8k boundary! Make sure PCI read prefetching
|
|
* is disabled on these chips. Note that secondary
|
|
* PCI busses don't have this problem, because of
|
|
* the way PPBs handle PCI read requests.
|
|
*
|
|
* In the 21174 Technical Reference Manual, this is
|
|
* actually documented as "Pyxis Pass 1", but apparently
|
|
* there are chips that report themselves as "Pass 1"
|
|
* which do not have the bug! Miatas with the Cypress
|
|
* PCI-ISA bridge (i.e. Miata 1.5 and Miata 2) do not
|
|
* have the bug, so we use this check.
|
|
*
|
|
* XXX We also need to deal with this boundary constraint
|
|
* XXX in the PCI bus 0 (and ISA) DMA tags, but some
|
|
* XXX drivers are going to need to be changed first.
|
|
*/
|
|
u_int32_t ctrl;
|
|
|
|
/* XXX no bets... */
|
|
printf("cia0: WARNING: Pyxis pass 1 DMA bug; no bets...\n");
|
|
|
|
alpha_mb();
|
|
ctrl = REGVAL(CIA_CSR_CTRL);
|
|
ctrl &= ~(CTRL_RD_TYPE|CTRL_RL_TYPE|CTRL_RM_TYPE);
|
|
REGVAL(CIA_CSR_CTRL) = ctrl;
|
|
alpha_mb();
|
|
}
|
|
#endif
|
|
|
|
if (!platform.iointr) /* XXX */
|
|
set_iointr(alpha_dispatch_intr);
|
|
|
|
if (cia_ispyxis) {
|
|
snprintf(chipset_type, sizeof(chipset_type), "pyxis");
|
|
chipset_bwx = 1;
|
|
chipset_ports = CIA_EV56_BWIO;
|
|
chipset_memory = CIA_EV56_BWMEM;
|
|
chipset_dense = CIA_PCI_DENSE;
|
|
} else {
|
|
snprintf(chipset_type, sizeof(chipset_type), "cia");
|
|
chipset_bwx = 0;
|
|
chipset_ports = CIA_PCI_SIO1;
|
|
chipset_memory = CIA_PCI_SMEM1;
|
|
chipset_dense = CIA_PCI_DENSE;
|
|
chipset_hae_mask = 7L << 29;
|
|
}
|
|
|
|
bus_generic_attach(dev);
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
cia_setup_intr(device_t dev, device_t child,
|
|
struct resource *irq, int flags,
|
|
driver_intr_t *intr, void *arg, void **cookiep)
|
|
{
|
|
int error;
|
|
|
|
error = rman_activate_resource(irq);
|
|
if (error)
|
|
return error;
|
|
|
|
error = alpha_setup_intr(0x900 + (irq->r_start << 4),
|
|
intr, arg, cookiep,
|
|
&intrcnt[INTRCNT_EB164_IRQ + irq->r_start]);
|
|
if (error)
|
|
return error;
|
|
|
|
/* Enable PCI interrupt */
|
|
platform.pci_intr_enable(irq->r_start);
|
|
|
|
device_printf(child, "interrupting at CIA irq %d\n",
|
|
(int) irq->r_start);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int
|
|
cia_teardown_intr(device_t dev, device_t child,
|
|
struct resource *irq, void *cookie)
|
|
{
|
|
alpha_teardown_intr(cookie);
|
|
return rman_deactivate_resource(irq);
|
|
}
|
|
|
|
DRIVER_MODULE(cia, root, cia_driver, cia_devclass, 0, 0);
|