2d14418625
there is a PCI bus at all) ... - Do not expect the chip sets to follow even very clearly expressed requirements of the PCI 2.0 spec. - Do not read back the value just written to an I/O port without making sure that some other data have crossed the bus in between ...
440 lines
9.9 KiB
C
440 lines
9.9 KiB
C
/**************************************************************************
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**
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** $Id: pcibus.c,v 1.12 1995/09/14 20:27:31 se Exp $
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**
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** pci bus subroutines for i386 architecture.
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**
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** FreeBSD
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**
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**-------------------------------------------------------------------------
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**
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** Copyright (c) 1994 Wolfgang Stanglmeier. All rights reserved.
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**
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** Redistribution and use in source and binary forms, with or without
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** modification, are permitted provided that the following conditions
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** are met:
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** 1. Redistributions of source code must retain the above copyright
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** notice, this list of conditions and the following disclaimer.
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** 2. Redistributions in binary form must reproduce the above copyright
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** notice, this list of conditions and the following disclaimer in the
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** documentation and/or other materials provided with the distribution.
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** 3. The name of the author may not be used to endorse or promote products
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** derived from this software without specific prior written permission.
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**
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** THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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** IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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** OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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** IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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** INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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** NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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** DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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** THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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** THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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**
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***************************************************************************
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*/
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#define __PCIBUS_C___ "pl4 95/03/21"
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/kernel.h>
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#include <machine/cpu.h> /* bootverbose */
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#include <i386/isa/icu.h>
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#include <i386/isa/isa.h>
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#include <i386/isa/isa_device.h>
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#include <pci/pcivar.h>
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#include <pci/pcireg.h>
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#include <pci/pcibus.h>
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/*-----------------------------------------------------------------
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**
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** The following functions are provided by the pci bios.
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** They are used only by the pci configuration.
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**
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** pcibus_setup():
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** Probes for a pci system.
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** Sets pci_maxdevice and pci_mechanism.
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**
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** pcibus_tag():
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** Creates a handle for pci configuration space access.
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** This handle is given to the read/write functions.
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**
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** pcibus_ftag():
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** Creates a modified handle.
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**
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** pcibus_read():
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** Read a long word from the pci configuration space.
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** Requires a tag (from pcitag) and the register
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** number (should be a long word alligned one).
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**
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** pcibus_write():
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** Writes a long word to the pci configuration space.
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** Requires a tag (from pcitag), the register number
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** (should be a long word alligned one), and a value.
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**
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** pcibus_regirq():
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** Register an interupt handler for a pci device.
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** Requires a tag (from pcitag), the register number
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** (should be a long word alligned one), and a value.
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**
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**-----------------------------------------------------------------
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*/
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static void
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pcibus_setup (void);
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static pcici_t
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pcibus_tag (u_char bus, u_char device, u_char func);
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static pcici_t
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pcibus_ftag (pcici_t tag, u_char func);
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static u_long
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pcibus_read (pcici_t tag, u_long reg);
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static void
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pcibus_write (pcici_t tag, u_long reg, u_long data);
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static int
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pcibus_ihandler_attach (int irq, void(*ihandler)(), int arg, unsigned* maskp);
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static int
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pcibus_ihandler_detach (int irq, void(*handler)());
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static int
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pcibus_imask_include (int irq, unsigned* maskptr);
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static int
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pcibus_imask_exclude (int irq, unsigned* maskptr);
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struct pcibus i386pci = {
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"pci",
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pcibus_setup,
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pcibus_tag,
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pcibus_ftag,
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pcibus_read,
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pcibus_write,
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ICU_LEN,
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pcibus_ihandler_attach,
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pcibus_ihandler_detach,
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pcibus_imask_include,
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pcibus_imask_exclude,
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};
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/*
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** Announce structure to generic driver
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*/
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DATA_SET (pcibus_set, i386pci);
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/*--------------------------------------------------------------------
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**
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** Determine configuration mode
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**
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**--------------------------------------------------------------------
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*/
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#define CONF1_ADDR_PORT 0x0cf8
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#define CONF1_DATA_PORT 0x0cfc
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#define CONF1_ENABLE 0x80000000ul
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#define CONF1_ENABLE_CHK 0x80000001ul
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#define CONF1_ENABLE_MSK 0x80000001ul
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#define CONF1_ENABLE_RES 0x80000000ul
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#define CONF2_ENABLE_PORT 0x0cf8
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#define CONF2_FORWARD_PORT 0x0cfa
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#define CONF2_ENABLE_CHK 0x0e
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#define CONF2_ENABLE_RES 0x0e
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static void
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pcibus_setup (void)
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{
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u_long result, oldval;
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/*---------------------------------------
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** Configuration mode 1 ?
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**---------------------------------------
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*/
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oldval = inl (CONF1_ADDR_PORT);
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outl (CONF1_ADDR_PORT, CONF1_ENABLE_CHK);
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outl (CONF1_DATA_PORT, 0);
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result = inl (CONF1_ADDR_PORT);
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outl (CONF1_ADDR_PORT, oldval);
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if (bootverbose && (result != 0xfffffffful))
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printf ("pcibus_setup: "
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"wrote 0x%08x, read back 0x%08x, expected 0x%08x\n",
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CONF1_ENABLE_CHK, result, CONF1_ENABLE_RES);
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if ((result & CONF1_ENABLE_MSK) == CONF1_ENABLE_RES) {
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pci_mechanism = 1;
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pci_maxdevice = 32;
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return;
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};
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/*---------------------------------------
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** Configuration mode 2 ?
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**---------------------------------------
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*/
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outb (CONF2_ENABLE_PORT, CONF2_ENABLE_CHK);
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outb (CONF2_FORWARD_PORT, 0);
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result = inb (CONF2_ENABLE_PORT);
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outb (CONF2_ENABLE_PORT, 0);
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if ((result == CONF2_ENABLE_RES)
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&& !inb (CONF2_ENABLE_PORT)
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&& !inb (CONF2_FORWARD_PORT)) {
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pci_mechanism = 2;
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pci_maxdevice = 16;
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return;
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};
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/*---------------------------------------
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** No PCI bus host bridge found
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**---------------------------------------
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*/
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pci_mechanism = 0;
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pci_maxdevice = 0;
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}
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/*--------------------------------------------------------------------
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**
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** Build a pcitag from bus, device and function number
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**
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**--------------------------------------------------------------------
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*/
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static pcici_t
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pcibus_tag (unsigned char bus, unsigned char device, unsigned char func)
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{
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pcici_t tag;
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tag.cfg1 = 0;
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if (func >= 8) return tag;
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switch (pci_mechanism) {
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case 1:
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if (device < 32) {
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tag.cfg1 = CONF1_ENABLE
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| (((u_long) bus ) << 16ul)
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| (((u_long) device) << 11ul)
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| (((u_long) func ) << 8ul);
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}
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break;
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case 2:
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if (device < 16) {
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tag.cfg2.port = 0xc000 | (device << 8ul);
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tag.cfg2.enable = 0xf0 | (func << 1ul);
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tag.cfg2.forward = bus;
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}
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break;
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};
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return tag;
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}
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static pcici_t
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pcibus_ftag (pcici_t tag, u_char func)
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{
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switch (pci_mechanism) {
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case 1:
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tag.cfg1 &= ~0x700ul;
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tag.cfg1 |= (((u_long) func) << 8ul);
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break;
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case 2:
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tag.cfg2.enable = 0xf0 | (func << 1ul);
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break;
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};
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return tag;
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}
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/*--------------------------------------------------------------------
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**
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** Read register from configuration space.
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**
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**--------------------------------------------------------------------
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*/
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static u_long
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pcibus_read (pcici_t tag, u_long reg)
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{
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u_long addr, data = 0;
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if (!tag.cfg1) return (0xfffffffful);
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switch (pci_mechanism) {
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case 1:
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addr = tag.cfg1 | (reg & 0xfc);
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#ifdef PCI_DEBUG
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printf ("pci_conf_read(1): addr=%x ", addr);
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#endif
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outl (CONF1_ADDR_PORT, addr);
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data = inl (CONF1_DATA_PORT);
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outl (CONF1_ADDR_PORT, 0 );
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break;
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case 2:
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addr = tag.cfg2.port | (reg & 0xfc);
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#ifdef PCI_DEBUG
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printf ("pci_conf_read(2): addr=%x ", addr);
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#endif
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outb (CONF2_ENABLE_PORT , tag.cfg2.enable );
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outb (CONF2_FORWARD_PORT, tag.cfg2.forward);
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data = inl ((u_short) addr);
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outb (CONF2_ENABLE_PORT, 0);
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outb (CONF2_FORWARD_PORT, 0);
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break;
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};
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#ifdef PCI_DEBUG
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printf ("data=%x\n", data);
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#endif
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return (data);
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}
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/*--------------------------------------------------------------------
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**
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** Write register into configuration space.
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**
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**--------------------------------------------------------------------
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*/
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static void
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pcibus_write (pcici_t tag, u_long reg, u_long data)
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{
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u_long addr;
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if (!tag.cfg1) return;
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switch (pci_mechanism) {
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case 1:
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addr = tag.cfg1 | (reg & 0xfc);
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#ifdef PCI_DEBUG
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printf ("pci_conf_write(1): addr=%x data=%x\n",
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addr, data);
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#endif
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outl (CONF1_ADDR_PORT, addr);
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outl (CONF1_DATA_PORT, data);
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outl (CONF1_ADDR_PORT, 0 );
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break;
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case 2:
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addr = tag.cfg2.port | (reg & 0xfc);
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#ifdef PCI_DEBUG
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printf ("pci_conf_write(2): addr=%x data=%x\n",
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addr, data);
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#endif
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outb (CONF2_ENABLE_PORT, tag.cfg2.enable);
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outb (CONF2_FORWARD_PORT, tag.cfg2.forward);
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outl ((u_short) addr, data);
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outb (CONF2_ENABLE_PORT, 0);
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outb (CONF2_FORWARD_PORT, 0);
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break;
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};
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}
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/*-----------------------------------------------------------------------
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**
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** Register an interupt handler for a pci device.
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**
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**-----------------------------------------------------------------------
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*/
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static int
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pcibus_ihandler_attach (int irq, void(*func)(), int arg, unsigned * maskptr)
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{
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int result;
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result = register_intr(
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irq, /* isa irq */
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0, /* deviced?? */
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0, /* flags? */
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(inthand2_t*) func, /* handler */
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maskptr, /* mask pointer */
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arg); /* handler arg */
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if (result) {
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printf ("@@@ pcibus_ihandler_attach: result=%d\n", result);
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return (result);
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};
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update_intr_masks();
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INTREN ((1ul<<irq));
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return (0);
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}
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static int
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pcibus_ihandler_detach (int irq, void(*func)())
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{
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int result;
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INTRDIS ((1ul<<irq));
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result = unregister_intr (irq, (inthand2_t*) func);
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if (result)
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printf ("@@@ pcibus_ihandler_detach: result=%d\n", result);
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update_intr_masks();
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return (result);
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}
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static int
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pcibus_imask_include (int irq, unsigned* maskptr)
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{
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unsigned mask;
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if (!maskptr) return (0);
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mask = 1ul << irq;
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if (*maskptr & mask)
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return (-1);
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INTRMASK (*maskptr, mask);
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update_intr_masks();
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return (0);
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}
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static int
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pcibus_imask_exclude (int irq, unsigned* maskptr)
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{
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unsigned mask;
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if (!maskptr) return (0);
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mask = 1ul << irq;
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if (! (*maskptr & mask))
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return (-1);
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*maskptr &= ~mask;
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update_intr_masks();
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return (0);
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}
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