105 lines
3.2 KiB
C
105 lines
3.2 KiB
C
/*
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* Copyright (c) 1999 Cameron Grant <gandalf@vilnya.demon.co.uk>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* $FreeBSD$
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*/
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#ifndef _T4DWAVE_REG_H
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#define _T4DWAVE_REG_H
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#define TR_REG_CIR 0xa0
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#define TR_CIR_MASK 0x0000003f
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#define TR_CIR_ADDRENA 0x00001000
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#define TR_CIR_MIDENA 0x00002000
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#define TR_REG_MISCINT 0xb0
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#define TR_INT_ADDR 0x00000020
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#define TR_INT_SB 0x00000004
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#define TR_REG_DMAR0 0x00
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#define TR_REG_DMAR4 0x04
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#define TR_REG_DMAR11 0x0b
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#define TR_REG_DMAR15 0x0f
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#define TR_REG_SBR4 0x14
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#define TR_REG_SBR5 0x15
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#define TR_SB_INTSTATUS 0x82
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#define TR_REG_SBR9 0x1e
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#define TR_REG_SBR10 0x1f
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#define TR_REG_SBBL 0xc0
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#define TR_REG_SBCTRL 0xc4
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#define TR_REG_SBDELTA 0xac
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#define TR_CDC_DATA 16
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#define TDX_REG_CODECWR 0x40
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#define TDX_REG_CODECRD 0x44
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#define TDX_CDC_RWSTAT 0x00008000
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#define TDX_REG_CODECST 0x48
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#define TDX_CDC_SBCTRL 0x40
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#define TDX_CDC_ACTIVE 0x20
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#define TDX_CDC_READY 0x10
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#define TDX_CDC_ADCON 0x08
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#define TDX_CDC_DACON 0x02
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#define TDX_CDC_RESET 0x01
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#define TDX_CDC_ON (TDX_CDC_ADCON|TDX_CDC_DACON)
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#define SPA_REG_CODECRD 0x44
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#define SPA_REG_CODECWR 0x40
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#define SPA_REG_CODECST 0x48
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#define SPA_RST_OFF 0x0f0000
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#define SPA_REG_GPIO 0x48
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#define SPA_CDC_RWSTAT 0x00008000
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#define TNX_REG_CODECWR 0x44
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#define TNX_REG_CODEC1RD 0x48
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#define TNX_REG_CODEC2RD 0x4c
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#define TNX_CDC_RWSTAT 0x00000c00
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#define TNX_CDC_SEC 0x00000100
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#define TNX_REG_CODECST 0x40
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#define TNX_CDC_READY2 0x40
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#define TNX_CDC_ADC2ON 0x20
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#define TNX_CDC_DAC2ON 0x10
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#define TNX_CDC_READY1 0x08
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#define TNX_CDC_ADC1ON 0x04
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#define TNX_CDC_DAC1ON 0x02
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#define TNX_CDC_RESET 0x01
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#define TNX_CDC_ON (TNX_CDC_ADC1ON|TNX_CDC_DAC1ON)
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#define TR_REG_STARTA 0x80
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#define TR_REG_STOPA 0x84
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#define TR_REG_CSPF_A 0x90
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#define TR_REG_ADDRINTA 0x98
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#define TR_REG_INTENA 0xa4
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#define TR_REG_STARTB 0xb4
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#define TR_REG_STOPB 0xb8
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#define TR_REG_CSPF_B 0xbc
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#define TR_REG_ADDRINTB 0xd8
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#define TR_REG_INTENB 0xdc
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#define TR_REG_CHNBASE 0xe0
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#define TR_CHN_REGS 5
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#endif
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