524 lines
17 KiB
C++
524 lines
17 KiB
C++
//===- ExecutionDepsFix.cpp - Fix execution dependecy issues ----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the execution dependency fix pass.
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//
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// Some X86 SSE instructions like mov, and, or, xor are available in different
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// variants for different operand types. These variant instructions are
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// equivalent, but on Nehalem and newer cpus there is extra latency
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// transferring data between integer and floating point domains. ARM cores
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// have similar issues when they are configured with both VFP and NEON
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// pipelines.
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//
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// This pass changes the variant instructions to minimize domain crossings.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "execution-fix"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/Target/TargetInstrInfo.h"
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#include "llvm/Target/TargetMachine.h"
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#include "llvm/ADT/DepthFirstIterator.h"
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#include "llvm/Support/Allocator.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it also keeps track
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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/// keep track of the fact the the register is now available in multiple
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/// domains.
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namespace {
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struct DomainValue {
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// Basic reference counting.
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unsigned Refs;
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// Bitmask of available domains. For an open DomainValue, it is the still
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// possible domains for collapsing. For a collapsed DomainValue it is the
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// domains where the register is available for free.
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unsigned AvailableDomains;
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// Position of the last defining instruction.
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unsigned Dist;
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// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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// A collapsed DomainValue has no instructions to twiddle - it simply keeps
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// track of the domains where the registers are already available.
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bool isCollapsed() const { return Instrs.empty(); }
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// Is domain available?
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bool hasDomain(unsigned domain) const {
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return AvailableDomains & (1u << domain);
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}
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// Mark domain as available.
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void addDomain(unsigned domain) {
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AvailableDomains |= 1u << domain;
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}
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// Restrict to a single domain available.
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void setSingleDomain(unsigned domain) {
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AvailableDomains = 1u << domain;
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}
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// Return bitmask of domains that are available and in mask.
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unsigned getCommonDomains(unsigned mask) const {
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return AvailableDomains & mask;
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}
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// First domain available.
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unsigned getFirstDomain() const {
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return CountTrailingZeros_32(AvailableDomains);
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}
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DomainValue() { clear(); }
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void clear() {
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Refs = AvailableDomains = Dist = 0;
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Instrs.clear();
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}
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};
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}
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namespace {
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class ExeDepsFix : public MachineFunctionPass {
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static char ID;
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SpecificBumpPtrAllocator<DomainValue> Allocator;
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SmallVector<DomainValue*,16> Avail;
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const TargetRegisterClass *const RC;
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MachineFunction *MF;
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const TargetInstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineBasicBlock *MBB;
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std::vector<int> AliasMap;
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const unsigned NumRegs;
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DomainValue **LiveRegs;
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typedef DenseMap<MachineBasicBlock*,DomainValue**> LiveOutMap;
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LiveOutMap LiveOuts;
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unsigned Distance;
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public:
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ExeDepsFix(const TargetRegisterClass *rc)
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: MachineFunctionPass(ID), RC(rc), NumRegs(RC->getNumRegs()) {}
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virtual void getAnalysisUsage(AnalysisUsage &AU) const {
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AU.setPreservesAll();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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virtual bool runOnMachineFunction(MachineFunction &MF);
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virtual const char *getPassName() const {
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return "SSE execution domain fixup";
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}
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private:
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// Register mapping.
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int RegIndex(unsigned Reg);
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// DomainValue allocation.
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DomainValue *Alloc(int domain = -1);
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void Recycle(DomainValue*);
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// LiveRegs manipulations.
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void SetLiveReg(int rx, DomainValue *DV);
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void Kill(int rx);
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void Force(int rx, unsigned domain);
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void Collapse(DomainValue *dv, unsigned domain);
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bool Merge(DomainValue *A, DomainValue *B);
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void enterBasicBlock();
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void visitGenericInstr(MachineInstr*);
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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};
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}
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char ExeDepsFix::ID = 0;
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/// Translate TRI register number to an index into our smaller tables of
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/// interesting registers. Return -1 for boring registers.
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int ExeDepsFix::RegIndex(unsigned Reg) {
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assert(Reg < AliasMap.size() && "Invalid register");
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return AliasMap[Reg];
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}
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DomainValue *ExeDepsFix::Alloc(int domain) {
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DomainValue *dv = Avail.empty() ?
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new(Allocator.Allocate()) DomainValue :
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Avail.pop_back_val();
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dv->Dist = Distance;
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if (domain >= 0)
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dv->addDomain(domain);
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return dv;
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}
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void ExeDepsFix::Recycle(DomainValue *dv) {
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assert(dv && "Cannot recycle NULL");
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dv->clear();
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Avail.push_back(dv);
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}
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void ExeDepsFix::SetLiveReg(int rx, DomainValue *dv) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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if (!LiveRegs) {
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LiveRegs = new DomainValue*[NumRegs];
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std::fill(LiveRegs, LiveRegs+NumRegs, (DomainValue*)0);
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}
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if (LiveRegs[rx] == dv)
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return;
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if (LiveRegs[rx]) {
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assert(LiveRegs[rx]->Refs && "Bad refcount");
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if (--LiveRegs[rx]->Refs == 0) Recycle(LiveRegs[rx]);
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}
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LiveRegs[rx] = dv;
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if (dv) ++dv->Refs;
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}
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// Kill register rx, recycle or collapse any DomainValue.
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void ExeDepsFix::Kill(int rx) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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if (!LiveRegs || !LiveRegs[rx]) return;
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// Before killing the last reference to an open DomainValue, collapse it to
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// the first available domain.
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if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->isCollapsed())
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Collapse(LiveRegs[rx], LiveRegs[rx]->getFirstDomain());
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else
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SetLiveReg(rx, 0);
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}
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/// Force register rx into domain.
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void ExeDepsFix::Force(int rx, unsigned domain) {
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assert(unsigned(rx) < NumRegs && "Invalid index");
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DomainValue *dv;
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if (LiveRegs && (dv = LiveRegs[rx])) {
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if (dv->isCollapsed())
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dv->addDomain(domain);
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else if (dv->hasDomain(domain))
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Collapse(dv, domain);
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else {
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// This is an incompatible open DomainValue. Collapse it to whatever and
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// force the new value into domain. This costs a domain crossing.
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Collapse(dv, dv->getFirstDomain());
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assert(LiveRegs[rx] && "Not live after collapse?");
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LiveRegs[rx]->addDomain(domain);
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}
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} else {
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// Set up basic collapsed DomainValue.
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SetLiveReg(rx, Alloc(domain));
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}
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}
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void ExeDepsFix::Collapse(DomainValue *dv, unsigned domain) {
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assert(dv->hasDomain(domain) && "Cannot collapse");
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// Collapse all the instructions.
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while (!dv->Instrs.empty())
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TII->setExecutionDomain(dv->Instrs.pop_back_val(), domain);
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dv->setSingleDomain(domain);
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// If there are multiple users, give them new, unique DomainValues.
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if (LiveRegs && dv->Refs > 1)
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for (unsigned rx = 0; rx != NumRegs; ++rx)
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if (LiveRegs[rx] == dv)
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SetLiveReg(rx, Alloc(domain));
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}
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/// Merge - All instructions and registers in B are moved to A, and B is
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/// released.
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bool ExeDepsFix::Merge(DomainValue *A, DomainValue *B) {
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assert(!A->isCollapsed() && "Cannot merge into collapsed");
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assert(!B->isCollapsed() && "Cannot merge from collapsed");
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if (A == B)
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return true;
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// Restrict to the domains that A and B have in common.
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unsigned common = A->getCommonDomains(B->AvailableDomains);
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if (!common)
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return false;
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A->AvailableDomains = common;
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A->Dist = std::max(A->Dist, B->Dist);
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A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
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for (unsigned rx = 0; rx != NumRegs; ++rx)
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if (LiveRegs[rx] == B)
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SetLiveReg(rx, A);
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return true;
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}
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void ExeDepsFix::enterBasicBlock() {
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// Try to coalesce live-out registers from predecessors.
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for (MachineBasicBlock::livein_iterator i = MBB->livein_begin(),
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e = MBB->livein_end(); i != e; ++i) {
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int rx = RegIndex(*i);
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if (rx < 0) continue;
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for (MachineBasicBlock::const_pred_iterator pi = MBB->pred_begin(),
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pe = MBB->pred_end(); pi != pe; ++pi) {
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LiveOutMap::const_iterator fi = LiveOuts.find(*pi);
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if (fi == LiveOuts.end()) continue;
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DomainValue *pdv = fi->second[rx];
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if (!pdv) continue;
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if (!LiveRegs || !LiveRegs[rx]) {
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SetLiveReg(rx, pdv);
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continue;
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}
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// We have a live DomainValue from more than one predecessor.
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if (LiveRegs[rx]->isCollapsed()) {
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// We are already collapsed, but predecessor is not. Force him.
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unsigned domain = LiveRegs[rx]->getFirstDomain();
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if (!pdv->isCollapsed() && pdv->hasDomain(domain))
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Collapse(pdv, domain);
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continue;
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}
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// Currently open, merge in predecessor.
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if (!pdv->isCollapsed())
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Merge(LiveRegs[rx], pdv);
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else
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Force(rx, pdv->getFirstDomain());
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}
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}
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}
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// A hard instruction only works in one domain. All input registers will be
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// forced into that domain.
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void ExeDepsFix::visitHardInstr(MachineInstr *mi, unsigned domain) {
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// Collapse all uses.
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Force(rx, domain);
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}
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// Kill all defs and force them.
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Kill(rx);
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Force(rx, domain);
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}
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}
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// A soft instruction can be changed to work in other domains given by mask.
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void ExeDepsFix::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// Bitmask of available domains for this instruction after taking collapsed
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// operands into account.
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unsigned available = mask;
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// Scan the explicit use operands for incoming domains.
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SmallVector<int, 4> used;
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if (LiveRegs)
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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if (DomainValue *dv = LiveRegs[rx]) {
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// Bitmask of domains that dv and available have in common.
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unsigned common = dv->getCommonDomains(available);
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// Is it possible to use this collapsed register for free?
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if (dv->isCollapsed()) {
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// Restrict available domains to the ones in common with the operand.
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// If there are no common domains, we must pay the cross-domain
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// penalty for this operand.
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if (common) available = common;
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} else if (common)
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// Open DomainValue is compatible, save it for merging.
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used.push_back(rx);
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else
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// Open DomainValue is not compatible with instruction. It is useless
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// now.
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Kill(rx);
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}
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}
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// If the collapsed operands force a single domain, propagate the collapse.
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if (isPowerOf2_32(available)) {
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unsigned domain = CountTrailingZeros_32(available);
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TII->setExecutionDomain(mi, domain);
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visitHardInstr(mi, domain);
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return;
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}
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// Kill off any remaining uses that don't match available, and build a list of
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// incoming DomainValues that we want to merge.
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SmallVector<DomainValue*,4> doms;
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for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
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int rx = *i;
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DomainValue *dv = LiveRegs[rx];
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// This useless DomainValue could have been missed above.
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if (!dv->getCommonDomains(available)) {
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Kill(*i);
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continue;
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}
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// sorted, uniqued insert.
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bool inserted = false;
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for (SmallVector<DomainValue*,4>::iterator i = doms.begin(), e = doms.end();
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i != e && !inserted; ++i) {
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if (dv == *i)
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inserted = true;
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else if (dv->Dist < (*i)->Dist) {
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inserted = true;
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doms.insert(i, dv);
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}
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}
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if (!inserted)
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doms.push_back(dv);
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}
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// doms are now sorted in order of appearance. Try to merge them all, giving
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// priority to the latest ones.
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DomainValue *dv = 0;
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while (!doms.empty()) {
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if (!dv) {
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dv = doms.pop_back_val();
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continue;
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}
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DomainValue *latest = doms.pop_back_val();
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if (Merge(dv, latest)) continue;
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// If latest didn't merge, it is useless now. Kill all registers using it.
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for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i != e; ++i)
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if (LiveRegs[*i] == latest)
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Kill(*i);
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}
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// dv is the DomainValue we are going to use for this instruction.
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if (!dv)
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dv = Alloc();
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dv->Dist = Distance;
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dv->AvailableDomains = available;
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dv->Instrs.push_back(mi);
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// Finally set all defs and non-collapsed uses to dv.
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for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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if (!LiveRegs || !LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) {
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Kill(rx);
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SetLiveReg(rx, dv);
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}
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}
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}
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void ExeDepsFix::visitGenericInstr(MachineInstr *mi) {
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// Process explicit defs, kill any relevant registers redefined.
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Kill(rx);
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}
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}
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bool ExeDepsFix::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TII = MF->getTarget().getInstrInfo();
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TRI = MF->getTarget().getRegisterInfo();
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MBB = 0;
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LiveRegs = 0;
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Distance = 0;
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assert(NumRegs == RC->getNumRegs() && "Bad regclass");
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// If no relevant registers are used in the function, we can skip it
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// completely.
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bool anyregs = false;
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for (TargetRegisterClass::const_iterator I = RC->begin(), E = RC->end();
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I != E; ++I)
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if (MF->getRegInfo().isPhysRegUsed(*I)) {
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anyregs = true;
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break;
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}
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if (!anyregs) return false;
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// Initialize the AliasMap on the first use.
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if (AliasMap.empty()) {
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// Given a PhysReg, AliasMap[PhysReg] is either the relevant index into RC,
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// or -1.
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AliasMap.resize(TRI->getNumRegs(), -1);
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for (unsigned i = 0, e = RC->getNumRegs(); i != e; ++i)
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for (const unsigned *AI = TRI->getOverlaps(RC->getRegister(i)); *AI; ++AI)
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AliasMap[*AI] = i;
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}
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MachineBasicBlock *Entry = MF->begin();
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SmallPtrSet<MachineBasicBlock*, 16> Visited;
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for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 16> >
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DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
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DFI != DFE; ++DFI) {
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MBB = *DFI;
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enterBasicBlock();
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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MachineInstr *mi = I;
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if (mi->isDebugValue()) continue;
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++Distance;
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std::pair<uint16_t, uint16_t> domp = TII->getExecutionDomain(mi);
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if (domp.first)
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if (domp.second)
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visitSoftInstr(mi, domp.second);
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else
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visitHardInstr(mi, domp.first);
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else if (LiveRegs)
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visitGenericInstr(mi);
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}
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// Save live registers at end of MBB - used by enterBasicBlock().
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if (LiveRegs)
|
|
LiveOuts.insert(std::make_pair(MBB, LiveRegs));
|
|
LiveRegs = 0;
|
|
}
|
|
|
|
// Clear the LiveOuts vectors. Should we also collapse any remaining
|
|
// DomainValues?
|
|
for (LiveOutMap::const_iterator i = LiveOuts.begin(), e = LiveOuts.end();
|
|
i != e; ++i)
|
|
delete[] i->second;
|
|
LiveOuts.clear();
|
|
Avail.clear();
|
|
Allocator.DestroyAll();
|
|
|
|
return false;
|
|
}
|
|
|
|
FunctionPass *
|
|
llvm::createExecutionDependencyFixPass(const TargetRegisterClass *RC) {
|
|
return new ExeDepsFix(RC);
|
|
}
|