ac1e0174a6
On the KB9202 go ahead and enable the flash controller so the boot loader can access the parallel flash.
199 lines
6.2 KiB
C
199 lines
6.2 KiB
C
/*-
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* Copyright (c) 2006 M. Warner Losh. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This software is derived from software provide by Kwikbyte who specifically
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* disclaimed copyright on the code.
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*
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* $FreeBSD$
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*/
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#include "at91rm9200.h"
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#include "at91rm9200_lowlevel.h"
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#define BAUD 115200
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#define AT91C_US_ASYNC_MODE (AT91C_US_USMODE_NORMAL | AT91C_US_NBSTOP_1_BIT | \
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AT91C_US_PAR_NONE | AT91C_US_CHRL_8_BITS | AT91C_US_CLKS_CLOCK)
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/*
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* void DefaultSystemInit(void)
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* Load the system with sane values based on how the system is configured.
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* at91rm9200_lowlevel.h is expected to define the necessary parameters.
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*/
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void
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_init(void)
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{
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AT91PS_USART pUSART = (AT91PS_USART)AT91C_BASE_DBGU;
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AT91PS_PDC pPDC = (AT91PS_PDC)&(pUSART->US_RPR);
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register unsigned value;
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volatile sdram_size_t *p = (sdram_size_t *)SDRAM_BASE;
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#ifdef BOOT_TSC
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// For the TSC board, we turn ON the one LED we have while
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// early in boot.
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AT91C_BASE_PIOC->PIO_PER = AT91C_PIO_PC10;
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AT91C_BASE_PIOC->PIO_OER = AT91C_PIO_PC10;
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AT91C_BASE_PIOC->PIO_CODR = AT91C_PIO_PC10;
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#endif
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// configure clocks
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// assume:
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// main osc = 10Mhz
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// PLLB configured for 96MHz (48MHz after div)
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// CSS = PLLB
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// set PLLA = 180MHz
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// assume main osc = 10Mhz
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// div = 5 , out = 2 (150MHz = 240MHz)
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value = AT91C_BASE_CKGR->CKGR_PLLAR;
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value &= ~(AT91C_CKGR_DIVA | AT91C_CKGR_OUTA | AT91C_CKGR_MULA);
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value |= OSC_MAIN_FREQ_DIV | AT91C_CKGR_OUTA_2 | AT91C_CKGR_SRCA |
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((OSC_MAIN_MULT - 1) << 16);
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AT91C_BASE_CKGR->CKGR_PLLAR = value;
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// wait for lock
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_LOCKA))
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continue;
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// change divider = 3, pres = 1
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value = AT91C_BASE_PMC->PMC_MCKR;
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value &= ~(AT91C_PMC_MDIV | AT91C_PMC_PRES);
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value |= AT91C_PMC_MDIV_3 | AT91C_PMC_PRES_CLK;
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AT91C_BASE_PMC->PMC_MCKR = value;
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// wait for update
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
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continue;
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// change CSS = PLLA
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value &= ~AT91C_PMC_CSS;
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value |= AT91C_PMC_CSS_PLLA_CLK;
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AT91C_BASE_PMC->PMC_MCKR = value;
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// wait for update
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while (!(AT91C_BASE_PMC->PMC_SR & AT91C_PMC_MCKRDY))
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continue;
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#ifdef BOOT_KB9202
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// setup flash access (allow ample margin)
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// 9 wait states, 1 setup, 1 hold, 1 float for 8-bit device
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((AT91PS_SMC2)AT91C_BASE_SMC2)->SMC2_CSR[0] =
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AT91C_SMC2_WSEN |
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(9 & AT91C_SMC2_NWS) |
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((1 << 8) & AT91C_SMC2_TDF) |
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AT91C_SMC2_DBW_8 |
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((1 << 24) & AT91C_SMC2_RWSETUP) |
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((1 << 29) & AT91C_SMC2_RWHOLD);
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#endif
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// setup SDRAM access
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// EBI chip-select register (CS1 = SDRAM controller)
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// 9 col, 13row, 4 bank, CAS2
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// write recovery = 2 (Twr)
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// row cycle = 5 (Trc)
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// precharge delay = 2 (Trp)
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// row to col delay 2 (Trcd)
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// active to precharge = 4 (Tras)
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// exit self refresh to active = 6 (Txsr)
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value = ((AT91PS_EBI)AT91C_BASE_EBI)->EBI_CSA;
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value &= ~AT91C_EBI_CS1A;
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value |= AT91C_EBI_CS1A_SDRAMC;
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AT91C_BASE_EBI->EBI_CSA = value;
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AT91C_BASE_SDRC->SDRC_CR =
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AT91C_SDRC_NC_9 |
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AT91C_SDRC_NR_13 |
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AT91C_SDRC_NB_4_BANKS |
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AT91C_SDRC_CAS_2 |
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((2 << 7) & AT91C_SDRC_TWR) |
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((5 << 11) & AT91C_SDRC_TRC) |
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((2 << 15) & AT91C_SDRC_TRP) |
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((2 << 19) & AT91C_SDRC_TRCD) |
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((4 << 23) & AT91C_SDRC_TRAS) |
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((6 << 27) & AT91C_SDRC_TXSR);
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// Step 1: We assume 200us of idle time.
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// Step 2: Issue an all banks precharge command
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AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_PRCGALL_CMD;
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*p = 0;
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// Step 3: Issue 8 Auto-refresh (CBR) cycles
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AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_RFSH_CMD;
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*p = 0;
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*p = 0;
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*p = 0;
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*p = 0;
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*p = 0;
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*p = 0;
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*p = 0;
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*p = 0;
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// Step 4: Issue an Mode Set Register (MRS) cycle to program in
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// the parameters that we setup in the SDRC_CR register above.
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AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_LMR_CMD;
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*p = 0;
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// Step 5: set the refresh timer and access memory to start it
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// running. We have to wait 3 clocks after the LMR_CMD above,
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// and this fits the bill nicely.
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AT91C_BASE_SDRC->SDRC_TR = 7 * AT91C_MASTER_CLOCK / 1000000;
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*p = 0;
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// Step 6: Set normal mode.
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AT91C_BASE_SDRC->SDRC_MR = SDRAM_WIDTH | AT91C_SDRC_MODE_NORMAL_CMD;
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*p = 0;
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#if SDRAM_WIDTH == AT91C_SDRC_DBW_32_BITS
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// Turn on the upper 16 bits on the SDRAM bus.
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AT91C_BASE_PIOC->PIO_ASR = 0xffff0000;
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AT91C_BASE_PIOC->PIO_PDR = 0xffff0000;
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#endif
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// Configure DBGU -use local routine optimized for space
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AT91C_BASE_PIOA->PIO_ASR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
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AT91C_BASE_PIOA->PIO_PDR = AT91C_PA31_DTXD | AT91C_PA30_DRXD;
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pUSART->US_IDR = (unsigned int) -1;
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pUSART->US_CR =
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AT91C_US_RSTRX | AT91C_US_RSTTX | AT91C_US_RXDIS | AT91C_US_TXDIS;
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pUSART->US_BRGR = ((((AT91C_MASTER_CLOCK*10)/(BAUD*16))+5)/10);
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pUSART->US_TTGR = 0;
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pPDC->PDC_PTCR = AT91C_PDC_RXTDIS;
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pPDC->PDC_PTCR = AT91C_PDC_TXTDIS;
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pPDC->PDC_TNPR = 0;
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pPDC->PDC_TNCR = 0;
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pPDC->PDC_RNPR = 0;
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pPDC->PDC_RNCR = 0;
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pPDC->PDC_TPR = 0;
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pPDC->PDC_TCR = 0;
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pPDC->PDC_RPR = 0;
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pPDC->PDC_RCR = 0;
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pPDC->PDC_PTCR = AT91C_PDC_RXTEN;
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pPDC->PDC_PTCR = AT91C_PDC_TXTEN;
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pUSART->US_MR = AT91C_US_ASYNC_MODE;
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pUSART->US_CR = AT91C_US_TXEN;
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pUSART->US_CR = AT91C_US_RXEN;
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}
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