560 lines
14 KiB
C
560 lines
14 KiB
C
/*-
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* Copyright (c) 2016 Ganbold Tsagaankhuu <ganbold@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Allwinner Consumer IR controller
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/evdev/input.h>
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#include <dev/evdev/evdev.h>
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#define READ(_sc, _r) bus_read_4((_sc)->res[0], (_r))
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#define WRITE(_sc, _r, _v) bus_write_4((_sc)->res[0], (_r), (_v))
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/* IR Control */
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#define AW_IR_CTL 0x00
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/* Global Enable */
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#define AW_IR_CTL_GEN (1 << 0)
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/* RX enable */
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#define AW_IR_CTL_RXEN (1 << 1)
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/* CIR mode enable */
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#define AW_IR_CTL_MD (1 << 4) | (1 << 5)
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/* RX Config Reg */
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#define AW_IR_RXCTL 0x10
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/* Pulse Polarity Invert flag */
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#define AW_IR_RXCTL_RPPI (1 << 2)
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/* RX Data */
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#define AW_IR_RXFIFO 0x20
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/* RX Interrupt Control */
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#define AW_IR_RXINT 0x2C
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/* RX FIFO Overflow */
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#define AW_IR_RXINT_ROI_EN (1 << 0)
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/* RX Packet End */
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#define AW_IR_RXINT_RPEI_EN (1 << 1)
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/* RX FIFO Data Available */
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#define AW_IR_RXINT_RAI_EN (1 << 4)
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/* RX FIFO available byte level */
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#define AW_IR_RXINT_RAL(val) ((val) << 8)
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/* RX Interrupt Status Reg */
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#define AW_IR_RXSTA 0x30
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/* RX FIFO Get Available Counter */
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#define AW_IR_RXSTA_COUNTER(val) (((val) >> 8) & (sc->fifo_size * 2 - 1))
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/* Clear all interrupt status */
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#define AW_IR_RXSTA_CLEARALL 0xff
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/* IR Sample Configure Reg */
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#define AW_IR_CIR 0x34
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/*
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* Frequency sample: 23437.5Hz (Cycle: 42.7us)
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* Pulse of NEC Remote > 560us
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*/
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/* Filter Threshold = 8 * 42.7 = ~341us < 500us */
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#define AW_IR_RXFILT_VAL (((8) & 0x3f) << 2)
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/* Idle Threshold = (2 + 1) * 128 * 42.7 = ~16.4ms > 9ms */
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#define AW_IR_RXIDLE_VAL (((2) & 0xff) << 8)
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/* Bit 15 - value (pulse/space) */
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#define VAL_MASK 0x80
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/* Bits 0:14 - sample duration */
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#define PERIOD_MASK 0x7f
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/* Clock rate for IR0 or IR1 clock in CIR mode */
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#define AW_IR_BASE_CLK 3000000
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/* Frequency sample 3MHz/64 = 46875Hz (21.3us) */
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#define AW_IR_SAMPLE_64 (0 << 0)
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/* Frequency sample 3MHz/128 = 23437.5Hz (42.7us) */
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#define AW_IR_SAMPLE_128 (1 << 0)
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#define AW_IR_ERROR_CODE 0xffffffff
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#define AW_IR_REPEAT_CODE 0x0
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/* 80 * 42.7 = ~3.4ms, Lead1(4.5ms) > AW_IR_L1_MIN */
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#define AW_IR_L1_MIN 80
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/* 40 * 42.7 = ~1.7ms, Lead0(4.5ms) Lead0R(2.25ms) > AW_IR_L0_MIN */
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#define AW_IR_L0_MIN 40
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/* 26 * 42.7 = ~1109us ~= 561 * 2, Pulse < AW_IR_PMAX */
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#define AW_IR_PMAX 26
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/* 26 * 42.7 = ~1109us ~= 561 * 2, D1 > AW_IR_DMID, D0 <= AW_IR_DMID */
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#define AW_IR_DMID 26
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/* 53 * 42.7 = ~2263us ~= 561 * 4, D < AW_IR_DMAX */
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#define AW_IR_DMAX 53
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/* Active Thresholds */
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#define AW_IR_ACTIVE_T_VAL AW_IR_L1_MIN
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#define AW_IR_ACTIVE_T (((AW_IR_ACTIVE_T_VAL - 1) & 0xff) << 16)
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#define AW_IR_ACTIVE_T_C_VAL 0
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#define AW_IR_ACTIVE_T_C ((AW_IR_ACTIVE_T_C_VAL & 0xff) << 23)
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/* Code masks */
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#define CODE_MASK 0x00ff00ff
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#define INV_CODE_MASK 0xff00ff00
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#define VALID_CODE_MASK 0x00ff0000
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enum {
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A10_IR = 1,
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A13_IR,
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A31_IR,
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};
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#define AW_IR_RAW_BUF_SIZE 128
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SYSCTL_NODE(_hw, OID_AUTO, aw_cir, CTLFLAG_RD | CTLFLAG_MPSAFE, 0,
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"aw_cir driver");
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static int aw_cir_debug = 0;
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SYSCTL_INT(_hw_aw_cir, OID_AUTO, debug, CTLFLAG_RWTUN, &aw_cir_debug, 0,
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"Debug 1=on 0=off");
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struct aw_ir_softc {
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device_t dev;
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struct resource *res[2];
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void * intrhand;
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int fifo_size;
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int dcnt; /* Packet Count */
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unsigned char buf[AW_IR_RAW_BUF_SIZE];
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struct evdev_dev *sc_evdev;
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};
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static struct resource_spec aw_ir_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0 }
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun4i-a10-ir", A10_IR },
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{ "allwinner,sun5i-a13-ir", A13_IR },
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{ "allwinner,sun6i-a31-ir", A31_IR },
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{ NULL, 0 }
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};
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static void
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aw_ir_buf_reset(struct aw_ir_softc *sc)
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{
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sc->dcnt = 0;
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}
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static void
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aw_ir_buf_write(struct aw_ir_softc *sc, unsigned char data)
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{
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if (sc->dcnt < AW_IR_RAW_BUF_SIZE)
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sc->buf[sc->dcnt++] = data;
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else
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if (bootverbose)
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device_printf(sc->dev, "IR RX Buffer Full!\n");
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}
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static int
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aw_ir_buf_full(struct aw_ir_softc *sc)
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{
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return (sc->dcnt >= AW_IR_RAW_BUF_SIZE);
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}
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static unsigned char
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aw_ir_read_data(struct aw_ir_softc *sc)
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{
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return (unsigned char)(READ(sc, AW_IR_RXFIFO) & 0xff);
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}
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static unsigned long
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aw_ir_decode_packets(struct aw_ir_softc *sc)
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{
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unsigned int len, code;
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unsigned int active_delay;
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unsigned char val, last;
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int i, bitcount;
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "sc->dcnt = %d\n", sc->dcnt);
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/* Find Lead 1 (bit separator) */
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active_delay = AW_IR_ACTIVE_T_VAL *
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(AW_IR_ACTIVE_T_C_VAL != 0 ? 128 : 1);
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len = active_delay;
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "Initial len: %d\n", len);
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for (i = 0; i < sc->dcnt; i++) {
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val = sc->buf[i];
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if (val & VAL_MASK)
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len += (val & PERIOD_MASK) + 1;
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else {
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if (len > AW_IR_L1_MIN)
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break;
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len = 0;
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}
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}
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "len = %d\n", len);
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if ((val & VAL_MASK) || (len <= AW_IR_L1_MIN)) {
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "Bit separator error\n");
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goto error_code;
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}
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/* Find Lead 0 (bit length) */
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len = 0;
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for (; i < sc->dcnt; i++) {
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val = sc->buf[i];
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if (val & VAL_MASK) {
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if(len > AW_IR_L0_MIN)
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break;
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len = 0;
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} else
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len += (val & PERIOD_MASK) + 1;
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}
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if ((!(val & VAL_MASK)) || (len <= AW_IR_L0_MIN)) {
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "Bit length error\n");
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goto error_code;
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}
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/* Start decoding */
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code = 0;
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bitcount = 0;
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last = 1;
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len = 0;
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for (; i < sc->dcnt; i++) {
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val = sc->buf[i];
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if (last) {
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if (val & VAL_MASK)
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len += (val & PERIOD_MASK) + 1;
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else {
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if (len > AW_IR_PMAX) {
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if (bootverbose)
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device_printf(sc->dev,
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"Pulse error, len=%d\n",
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len);
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goto error_code;
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}
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last = 0;
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len = (val & PERIOD_MASK) + 1;
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}
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} else {
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if (val & VAL_MASK) {
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if (len > AW_IR_DMAX) {
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if (bootverbose)
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device_printf(sc->dev,
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"Distance error, len=%d\n",
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len);
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goto error_code;
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} else {
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if (len > AW_IR_DMID) {
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/* Decode */
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code |= 1 << bitcount;
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}
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bitcount++;
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if (bitcount == 32)
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break; /* Finish decoding */
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}
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last = 1;
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len = (val & PERIOD_MASK) + 1;
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} else
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len += (val & PERIOD_MASK) + 1;
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}
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}
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return (code);
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error_code:
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return (AW_IR_ERROR_CODE);
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}
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static int
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aw_ir_validate_code(unsigned long code)
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{
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unsigned long v1, v2;
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/* Don't check address */
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v1 = code & CODE_MASK;
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v2 = (code & INV_CODE_MASK) >> 8;
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if (((v1 ^ v2) & VALID_CODE_MASK) == VALID_CODE_MASK)
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return (0); /* valid */
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else
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return (1); /* invalid */
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}
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static void
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aw_ir_intr(void *arg)
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{
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struct aw_ir_softc *sc;
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uint32_t val;
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int i, dcnt;
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unsigned long ir_code;
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int stat;
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sc = (struct aw_ir_softc *)arg;
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/* Read RX interrupt status */
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val = READ(sc, AW_IR_RXSTA);
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "RX interrupt status: %x\n", val);
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/* Clean all pending interrupt statuses */
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WRITE(sc, AW_IR_RXSTA, val | AW_IR_RXSTA_CLEARALL);
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/* When Rx FIFO Data available or Packet end */
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if (val & (AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RPEI_EN)) {
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev,
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"RX FIFO Data available or Packet end\n");
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/* Get available message count in RX FIFO */
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dcnt = AW_IR_RXSTA_COUNTER(val);
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/* Read FIFO */
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for (i = 0; i < dcnt; i++) {
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if (aw_ir_buf_full(sc)) {
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if (bootverbose)
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device_printf(sc->dev,
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"raw buffer full\n");
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break;
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} else
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aw_ir_buf_write(sc, aw_ir_read_data(sc));
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}
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}
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if (val & AW_IR_RXINT_RPEI_EN) {
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/* RX Packet end */
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if (bootverbose && __predict_false(aw_cir_debug) != 0)
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device_printf(sc->dev, "RX Packet end\n");
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ir_code = aw_ir_decode_packets(sc);
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stat = aw_ir_validate_code(ir_code);
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if (stat == 0) {
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evdev_push_event(sc->sc_evdev,
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EV_MSC, MSC_SCAN, ir_code);
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evdev_sync(sc->sc_evdev);
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}
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if (bootverbose && __predict_false(aw_cir_debug) != 0) {
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device_printf(sc->dev, "Final IR code: %lx\n",
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ir_code);
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device_printf(sc->dev, "IR code status: %d\n",
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stat);
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}
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aw_ir_buf_reset(sc);
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}
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if (val & AW_IR_RXINT_ROI_EN) {
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/* RX FIFO overflow */
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if (bootverbose)
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device_printf(sc->dev, "RX FIFO overflow\n");
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/* Flush raw buffer */
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aw_ir_buf_reset(sc);
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}
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}
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static int
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aw_ir_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner CIR controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_ir_attach(device_t dev)
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{
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struct aw_ir_softc *sc;
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hwreset_t rst_apb;
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clk_t clk_ir, clk_gate;
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int err;
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uint32_t val = 0;
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clk_ir = clk_gate = NULL;
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rst_apb = NULL;
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sc = device_get_softc(dev);
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sc->dev = dev;
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if (bus_alloc_resources(dev, aw_ir_spec, sc->res) != 0) {
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device_printf(dev, "could not allocate memory resource\n");
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return (ENXIO);
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}
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switch (ofw_bus_search_compatible(dev, compat_data)->ocd_data) {
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case A10_IR:
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sc->fifo_size = 16;
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break;
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case A13_IR:
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case A31_IR:
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sc->fifo_size = 64;
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break;
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}
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/* De-assert reset */
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if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst_apb) == 0) {
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err = hwreset_deassert(rst_apb);
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if (err != 0) {
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device_printf(dev, "cannot de-assert reset\n");
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goto error;
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}
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}
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/* Reset buffer */
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aw_ir_buf_reset(sc);
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/* Get clocks and enable them */
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err = clk_get_by_ofw_name(dev, 0, "apb", &clk_gate);
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if (err != 0) {
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device_printf(dev, "Cannot get gate clock\n");
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goto error;
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}
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err = clk_get_by_ofw_name(dev, 0, "ir", &clk_ir);
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if (err != 0) {
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device_printf(dev, "Cannot get IR clock\n");
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goto error;
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}
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/* Set clock rate */
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err = clk_set_freq(clk_ir, AW_IR_BASE_CLK, 0);
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if (err != 0) {
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device_printf(dev, "cannot set IR clock rate\n");
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goto error;
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}
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/* Enable clocks */
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err = clk_enable(clk_gate);
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if (err != 0) {
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device_printf(dev, "Cannot enable clk gate\n");
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goto error;
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}
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err = clk_enable(clk_ir);
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if (err != 0) {
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device_printf(dev, "Cannot enable IR clock\n");
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goto error;
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}
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if (bus_setup_intr(dev, sc->res[1],
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INTR_TYPE_MISC | INTR_MPSAFE, NULL, aw_ir_intr, sc,
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&sc->intrhand)) {
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bus_release_resources(dev, aw_ir_spec, sc->res);
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device_printf(dev, "cannot setup interrupt handler\n");
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err = ENXIO;
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goto error;
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}
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/* Enable CIR Mode */
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WRITE(sc, AW_IR_CTL, AW_IR_CTL_MD);
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/*
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* Set clock sample, filter, idle thresholds.
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* Frequency sample = 3MHz/128 = 23437.5Hz (42.7us)
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*/
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val = AW_IR_SAMPLE_128;
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val |= (AW_IR_RXFILT_VAL | AW_IR_RXIDLE_VAL);
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val |= (AW_IR_ACTIVE_T | AW_IR_ACTIVE_T_C);
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WRITE(sc, AW_IR_CIR, val);
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|
|
/* Invert Input Signal */
|
|
WRITE(sc, AW_IR_RXCTL, AW_IR_RXCTL_RPPI);
|
|
|
|
/* Clear All RX Interrupt Status */
|
|
WRITE(sc, AW_IR_RXSTA, AW_IR_RXSTA_CLEARALL);
|
|
|
|
/*
|
|
* Enable RX interrupt in case of overflow, packet end
|
|
* and FIFO available.
|
|
* RX FIFO Threshold = FIFO size / 2
|
|
*/
|
|
WRITE(sc, AW_IR_RXINT, AW_IR_RXINT_ROI_EN | AW_IR_RXINT_RPEI_EN |
|
|
AW_IR_RXINT_RAI_EN | AW_IR_RXINT_RAL((sc->fifo_size >> 1) - 1));
|
|
|
|
/* Enable IR Module */
|
|
val = READ(sc, AW_IR_CTL);
|
|
WRITE(sc, AW_IR_CTL, val | AW_IR_CTL_GEN | AW_IR_CTL_RXEN);
|
|
|
|
sc->sc_evdev = evdev_alloc();
|
|
evdev_set_name(sc->sc_evdev, device_get_desc(sc->dev));
|
|
evdev_set_phys(sc->sc_evdev, device_get_nameunit(sc->dev));
|
|
evdev_set_id(sc->sc_evdev, BUS_HOST, 0, 0, 0);
|
|
evdev_support_event(sc->sc_evdev, EV_SYN);
|
|
evdev_support_event(sc->sc_evdev, EV_MSC);
|
|
evdev_support_msc(sc->sc_evdev, MSC_SCAN);
|
|
|
|
err = evdev_register(sc->sc_evdev);
|
|
if (err) {
|
|
device_printf(dev,
|
|
"failed to register evdev: error=%d\n", err);
|
|
goto error;
|
|
}
|
|
|
|
return (0);
|
|
error:
|
|
if (clk_gate != NULL)
|
|
clk_release(clk_gate);
|
|
if (clk_ir != NULL)
|
|
clk_release(clk_ir);
|
|
if (rst_apb != NULL)
|
|
hwreset_release(rst_apb);
|
|
evdev_free(sc->sc_evdev);
|
|
sc->sc_evdev = NULL; /* Avoid double free */
|
|
|
|
bus_release_resources(dev, aw_ir_spec, sc->res);
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_method_t aw_ir_methods[] = {
|
|
DEVMETHOD(device_probe, aw_ir_probe),
|
|
DEVMETHOD(device_attach, aw_ir_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t aw_ir_driver = {
|
|
"aw_ir",
|
|
aw_ir_methods,
|
|
sizeof(struct aw_ir_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(aw_ir, simplebus, aw_ir_driver, 0, 0);
|
|
MODULE_DEPEND(aw_ir, evdev, 1, 1, 1);
|