807 lines
19 KiB
C
807 lines
19 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2020 Oleksandr Tymoshenko <gonzo@FreeBSD.org>
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* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/resource.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include "syscon_if.h"
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#include "opt_snd.h"
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#include <dev/sound/pcm/sound.h>
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#include <dev/sound/fdt/audio_dai.h>
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#include "audio_dai_if.h"
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#define FIFO_LEVEL 0x40
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#define DA_CTL 0x00
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#define DA_CTL_BCLK_OUT (1 << 18) /* sun8i */
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#define DA_CLK_LRCK_OUT (1 << 17) /* sun8i */
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#define DA_CTL_SDO_EN (1 << 8)
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#define DA_CTL_MS (1 << 5) /* sun4i */
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#define DA_CTL_PCM (1 << 4) /* sun4i */
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#define DA_CTL_MODE_SEL_MASK (3 << 4) /* sun8i */
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#define DA_CTL_MODE_SEL_PCM (0 << 4) /* sun8i */
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#define DA_CTL_MODE_SEL_LJ (1 << 4) /* sun8i */
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#define DA_CTL_MODE_SEL_RJ (2 << 4) /* sun8i */
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#define DA_CTL_TXEN (1 << 2)
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#define DA_CTL_RXEN (1 << 1)
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#define DA_CTL_GEN (1 << 0)
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#define DA_FAT0 0x04
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#define DA_FAT0_LRCK_PERIOD_MASK (0x3ff << 8) /* sun8i */
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#define DA_FAT0_LRCK_PERIOD(n) (((n) & 0x3fff) << 8) /* sun8i */
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#define DA_FAT0_LRCP_MASK (1 << 7)
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#define DA_LRCP_NORMAL (0 << 7)
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#define DA_LRCP_INVERTED (1 << 7)
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#define DA_FAT0_BCP_MASK (1 << 6)
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#define DA_BCP_NORMAL (0 << 6)
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#define DA_BCP_INVERTED (1 << 6)
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#define DA_FAT0_SR __BITS(5,4)
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#define DA_FAT0_WSS __BITS(3,2)
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#define DA_FAT0_FMT_MASK (3 << 0)
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#define DA_FMT_I2S 0
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#define DA_FMT_LJ 1
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#define DA_FMT_RJ 2
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#define DA_FAT1 0x08
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#define DA_ISTA 0x0c
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#define DA_ISTA_TXUI_INT (1 << 6)
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#define DA_ISTA_TXEI_INT (1 << 4)
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#define DA_ISTA_RXAI_INT (1 << 0)
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#define DA_RXFIFO 0x10
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#define DA_FCTL 0x14
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#define DA_FCTL_HUB_EN (1 << 31)
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#define DA_FCTL_FTX (1 << 25)
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#define DA_FCTL_FRX (1 << 24)
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#define DA_FCTL_TXTL_MASK (0x7f << 12)
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#define DA_FCTL_TXTL(v) (((v) & 0x7f) << 12)
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#define DA_FCTL_TXIM (1 << 2)
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#define DA_FSTA 0x18
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#define DA_FSTA_TXE_CNT(v) (((v) >> 16) & 0xff)
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#define DA_FSTA_RXA_CNT(v) ((v) & 0x3f)
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#define DA_INT 0x1c
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#define DA_INT_TX_DRQ (1 << 7)
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#define DA_INT_TXUI_EN (1 << 6)
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#define DA_INT_TXEI_EN (1 << 4)
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#define DA_INT_RX_DRQ (1 << 3)
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#define DA_INT_RXAI_EN (1 << 0)
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#define DA_TXFIFO 0x20
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#define DA_CLKD 0x24
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#define DA_CLKD_MCLKO_EN_SUN8I (1 << 8)
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#define DA_CLKD_MCLKO_EN_SUN4I (1 << 7)
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#define DA_CLKD_BCLKDIV_SUN8I(n) (((n) & 0xf) << 4)
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#define DA_CLKD_BCLKDIV_SUN8I_MASK (0xf << 4)
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#define DA_CLKD_BCLKDIV_SUN4I(n) (((n) & 7) << 4)
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#define DA_CLKD_BCLKDIV_SUN4I_MASK (7 << 4)
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#define DA_CLKD_BCLKDIV_8 3
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#define DA_CLKD_BCLKDIV_16 5
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#define DA_CLKD_MCLKDIV(n) (((n) & 0xff) << 0)
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#define DA_CLKD_MCLKDIV_MASK (0xf << 0)
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#define DA_CLKD_MCLKDIV_1 0
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#define DA_TXCNT 0x28
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#define DA_RXCNT 0x2c
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#define DA_CHCFG 0x30 /* sun8i */
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#define DA_CHCFG_TX_SLOT_HIZ (1 << 9)
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#define DA_CHCFG_TXN_STATE (1 << 8)
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#define DA_CHCFG_RX_SLOT_NUM_MASK (7 << 4)
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#define DA_CHCFG_RX_SLOT_NUM(n) (((n) & 7) << 4)
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#define DA_CHCFG_TX_SLOT_NUM_MASK (7 << 0)
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#define DA_CHCFG_TX_SLOT_NUM(n) (((n) & 7) << 0)
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#define DA_CHSEL_OFFSET(n) (((n) & 3) << 12) /* sun8i */
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#define DA_CHSEL_OFFSET_MASK (3 << 12) /* sun8i */
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#define DA_CHSEL_EN(n) (((n) & 0xff) << 4)
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#define DA_CHSEL_EN_MASK (0xff << 4)
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#define DA_CHSEL_SEL(n) (((n) & 7) << 0)
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#define DA_CHSEL_SEL_MASK (7 << 0)
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#define AUDIO_BUFFER_SIZE 48000 * 4
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#define AW_I2S_SAMPLE_RATE 48000
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#define AW_I2S_CLK_RATE 24576000
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enum sunxi_i2s_type {
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SUNXI_I2S_SUN4I,
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SUNXI_I2S_SUN8I,
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};
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struct sunxi_i2s_config {
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const char *name;
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enum sunxi_i2s_type type;
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bus_size_t txchsel;
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bus_size_t txchmap;
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bus_size_t rxchsel;
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bus_size_t rxchmap;
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};
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static const struct sunxi_i2s_config sun50i_a64_codec_config = {
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.name = "Audio Codec (digital part)",
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.type = SUNXI_I2S_SUN4I,
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.txchsel = 0x30,
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.txchmap = 0x34,
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.rxchsel = 0x38,
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.rxchmap = 0x3c,
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};
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static const struct sunxi_i2s_config sun8i_h3_config = {
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.name = "I2S/PCM controller",
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.type = SUNXI_I2S_SUN8I,
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.txchsel = 0x34,
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.txchmap = 0x44,
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.rxchsel = 0x54,
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.rxchmap = 0x58,
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};
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static const u_int sun4i_i2s_bclk_divmap[] = {
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[0] = 2,
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[1] = 4,
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[2] = 6,
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[3] = 8,
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[4] = 12,
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[5] = 16,
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};
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static const u_int sun4i_i2s_mclk_divmap[] = {
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[0] = 1,
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[1] = 2,
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[2] = 4,
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[3] = 6,
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[4] = 8,
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[5] = 12,
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[6] = 16,
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[7] = 24,
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};
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static const u_int sun8i_i2s_divmap[] = {
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[1] = 1,
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[2] = 2,
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[3] = 4,
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[4] = 6,
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[5] = 8,
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[6] = 12,
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[7] = 16,
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[8] = 24,
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[9] = 32,
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[10] = 48,
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[11] = 64,
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[12] = 96,
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[13] = 128,
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[14] = 176,
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[15] = 192,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun50i-a64-codec-i2s", (uintptr_t)&sun50i_a64_codec_config },
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{ "allwinner,sun8i-h3-i2s", (uintptr_t)&sun8i_h3_config },
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{ NULL, 0 }
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};
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static struct resource_spec aw_i2s_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE | RF_SHAREABLE },
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{ -1, 0 }
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};
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struct aw_i2s_softc {
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device_t dev;
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struct resource *res[2];
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struct mtx mtx;
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clk_t clk;
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struct sunxi_i2s_config *cfg;
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void * intrhand;
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/* pointers to playback/capture buffers */
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uint32_t play_ptr;
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uint32_t rec_ptr;
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};
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#define I2S_LOCK(sc) mtx_lock(&(sc)->mtx)
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#define I2S_UNLOCK(sc) mtx_unlock(&(sc)->mtx)
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#define I2S_READ(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define I2S_WRITE(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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#define I2S_TYPE(sc) ((sc)->cfg->type)
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static int aw_i2s_probe(device_t dev);
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static int aw_i2s_attach(device_t dev);
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static int aw_i2s_detach(device_t dev);
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static u_int
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sunxi_i2s_div_to_regval(const u_int *divmap, u_int divmaplen, u_int div)
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{
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u_int n;
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for (n = 0; n < divmaplen; n++)
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if (divmap[n] == div)
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return n;
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return -1;
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}
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static uint32_t sc_fmt[] = {
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SND_FORMAT(AFMT_S16_LE, 2, 0),
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0
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};
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static struct pcmchan_caps aw_i2s_caps = {AW_I2S_SAMPLE_RATE, AW_I2S_SAMPLE_RATE, sc_fmt, 0};
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static int
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aw_i2s_init(struct aw_i2s_softc *sc)
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{
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uint32_t val;
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int error;
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error = clk_enable(sc->clk);
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if (error != 0) {
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device_printf(sc->dev, "cannot enable mod clock\n");
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return (ENXIO);
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}
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/* Reset */
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val = I2S_READ(sc, DA_CTL);
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val &= ~(DA_CTL_TXEN|DA_CTL_RXEN|DA_CTL_GEN);
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I2S_WRITE(sc, DA_CTL, val);
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val = I2S_READ(sc, DA_FCTL);
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val &= ~(DA_FCTL_FTX|DA_FCTL_FRX);
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val &= ~(DA_FCTL_TXTL_MASK);
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val |= DA_FCTL_TXTL(FIFO_LEVEL);
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I2S_WRITE(sc, DA_FCTL, val);
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I2S_WRITE(sc, DA_TXCNT, 0);
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I2S_WRITE(sc, DA_RXCNT, 0);
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/* Enable */
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val = I2S_READ(sc, DA_CTL);
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val |= DA_CTL_GEN;
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I2S_WRITE(sc, DA_CTL, val);
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val |= DA_CTL_SDO_EN;
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I2S_WRITE(sc, DA_CTL, val);
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/* Setup channels */
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I2S_WRITE(sc, sc->cfg->txchmap, 0x76543210);
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val = I2S_READ(sc, sc->cfg->txchsel);
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val &= ~DA_CHSEL_EN_MASK;
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val |= DA_CHSEL_EN(3);
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val &= ~DA_CHSEL_SEL_MASK;
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val |= DA_CHSEL_SEL(1);
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I2S_WRITE(sc, sc->cfg->txchsel, val);
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I2S_WRITE(sc, sc->cfg->rxchmap, 0x76543210);
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val = I2S_READ(sc, sc->cfg->rxchsel);
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val &= ~DA_CHSEL_EN_MASK;
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val |= DA_CHSEL_EN(3);
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val &= ~DA_CHSEL_SEL_MASK;
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val |= DA_CHSEL_SEL(1);
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I2S_WRITE(sc, sc->cfg->rxchsel, val);
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if (I2S_TYPE(sc) == SUNXI_I2S_SUN8I) {
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val = I2S_READ(sc, DA_CHCFG);
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val &= ~DA_CHCFG_TX_SLOT_NUM_MASK;
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val |= DA_CHCFG_TX_SLOT_NUM(1);
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val &= ~DA_CHCFG_RX_SLOT_NUM_MASK;
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val |= DA_CHCFG_RX_SLOT_NUM(1);
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I2S_WRITE(sc, DA_CHCFG, val);
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}
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return (0);
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}
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static int
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aw_i2s_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
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return (ENXIO);
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device_set_desc(dev, "Allwinner I2S");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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aw_i2s_attach(device_t dev)
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{
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struct aw_i2s_softc *sc;
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int error;
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phandle_t node;
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hwreset_t rst;
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clk_t clk;
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sc = device_get_softc(dev);
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sc->dev = dev;
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sc->cfg = (void*)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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mtx_init(&sc->mtx, device_get_nameunit(dev), NULL, MTX_DEF);
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if (bus_alloc_resources(dev, aw_i2s_spec, sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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error = ENXIO;
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goto fail;
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}
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error = clk_get_by_ofw_name(dev, 0, "mod", &sc->clk);
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if (error != 0) {
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device_printf(dev, "cannot get i2s_clk clock\n");
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goto fail;
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}
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error = clk_get_by_ofw_name(dev, 0, "apb", &clk);
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if (error != 0) {
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device_printf(dev, "cannot get APB clock\n");
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goto fail;
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}
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error = clk_enable(clk);
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if (error != 0) {
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device_printf(dev, "cannot enable APB clock\n");
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goto fail;
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}
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if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
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error = hwreset_deassert(rst);
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if (error != 0) {
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device_printf(dev, "cannot de-assert reset\n");
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goto fail;
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}
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}
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aw_i2s_init(sc);
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node = ofw_bus_get_node(dev);
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OF_device_register_xref(OF_xref_from_node(node), dev);
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return (0);
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fail:
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aw_i2s_detach(dev);
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return (error);
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}
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static int
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aw_i2s_detach(device_t dev)
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{
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struct aw_i2s_softc *i2s;
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i2s = device_get_softc(dev);
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if (i2s->clk)
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clk_release(i2s->clk);
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if (i2s->intrhand != NULL)
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bus_teardown_intr(i2s->dev, i2s->res[1], i2s->intrhand);
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bus_release_resources(dev, aw_i2s_spec, i2s->res);
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mtx_destroy(&i2s->mtx);
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return (0);
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}
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static int
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aw_i2s_dai_init(device_t dev, uint32_t format)
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{
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struct aw_i2s_softc *sc;
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int fmt, pol;
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uint32_t ctl, fat0, chsel;
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u_int offset;
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sc = device_get_softc(dev);
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fmt = AUDIO_DAI_FORMAT_FORMAT(format);
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pol = AUDIO_DAI_FORMAT_POLARITY(format);
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ctl = I2S_READ(sc, DA_CTL);
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fat0 = I2S_READ(sc, DA_FAT0);
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if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
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fat0 &= ~DA_FAT0_FMT_MASK;
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switch (fmt) {
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case AUDIO_DAI_FORMAT_I2S:
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fat0 |= DA_FMT_I2S;
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break;
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case AUDIO_DAI_FORMAT_RJ:
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fat0 |= DA_FMT_RJ;
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break;
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case AUDIO_DAI_FORMAT_LJ:
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fat0 |= DA_FMT_LJ;
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break;
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default:
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return EINVAL;
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}
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ctl &= ~DA_CTL_PCM;
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} else {
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ctl &= ~DA_CTL_MODE_SEL_MASK;
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switch (fmt) {
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case AUDIO_DAI_FORMAT_I2S:
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ctl |= DA_CTL_MODE_SEL_LJ;
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offset = 1;
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break;
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case AUDIO_DAI_FORMAT_LJ:
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ctl |= DA_CTL_MODE_SEL_LJ;
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offset = 0;
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|
break;
|
|
case AUDIO_DAI_FORMAT_RJ:
|
|
ctl |= DA_CTL_MODE_SEL_RJ;
|
|
offset = 0;
|
|
break;
|
|
case AUDIO_DAI_FORMAT_DSPA:
|
|
ctl |= DA_CTL_MODE_SEL_PCM;
|
|
offset = 1;
|
|
break;
|
|
case AUDIO_DAI_FORMAT_DSPB:
|
|
ctl |= DA_CTL_MODE_SEL_PCM;
|
|
offset = 0;
|
|
break;
|
|
default:
|
|
return EINVAL;
|
|
}
|
|
|
|
chsel = I2S_READ(sc, sc->cfg->txchsel);
|
|
chsel &= ~DA_CHSEL_OFFSET_MASK;
|
|
chsel |= DA_CHSEL_OFFSET(offset);
|
|
I2S_WRITE(sc, sc->cfg->txchsel, chsel);
|
|
|
|
chsel = I2S_READ(sc, sc->cfg->rxchsel);
|
|
chsel &= ~DA_CHSEL_OFFSET_MASK;
|
|
chsel |= DA_CHSEL_OFFSET(offset);
|
|
I2S_WRITE(sc, sc->cfg->rxchsel, chsel);
|
|
}
|
|
|
|
fat0 &= ~(DA_FAT0_LRCP_MASK|DA_FAT0_BCP_MASK);
|
|
if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
|
|
if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol))
|
|
fat0 |= DA_BCP_INVERTED;
|
|
if (AUDIO_DAI_POLARITY_INVERTED_FRAME(pol))
|
|
fat0 |= DA_LRCP_INVERTED;
|
|
} else {
|
|
if (AUDIO_DAI_POLARITY_INVERTED_BCLK(pol))
|
|
fat0 |= DA_BCP_INVERTED;
|
|
if (!AUDIO_DAI_POLARITY_INVERTED_FRAME(pol))
|
|
fat0 |= DA_LRCP_INVERTED;
|
|
|
|
fat0 &= ~DA_FAT0_LRCK_PERIOD_MASK;
|
|
fat0 |= DA_FAT0_LRCK_PERIOD(32 - 1);
|
|
}
|
|
|
|
I2S_WRITE(sc, DA_CTL, ctl);
|
|
I2S_WRITE(sc, DA_FAT0, fat0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
|
|
static int
|
|
aw_i2s_dai_intr(device_t dev, struct snd_dbuf *play_buf, struct snd_dbuf *rec_buf)
|
|
{
|
|
struct aw_i2s_softc *sc;
|
|
int ret = 0;
|
|
uint32_t val, status;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
I2S_LOCK(sc);
|
|
|
|
status = I2S_READ(sc, DA_ISTA);
|
|
/* Clear interrupts */
|
|
// device_printf(sc->dev, "status: %08x\n", status);
|
|
I2S_WRITE(sc, DA_ISTA, status);
|
|
|
|
if (status & DA_ISTA_TXEI_INT) {
|
|
uint8_t *samples;
|
|
uint32_t count, size, readyptr, written, empty;
|
|
|
|
val = I2S_READ(sc, DA_FSTA);
|
|
empty = DA_FSTA_TXE_CNT(val);
|
|
count = sndbuf_getready(play_buf);
|
|
size = sndbuf_getsize(play_buf);
|
|
readyptr = sndbuf_getreadyptr(play_buf);
|
|
|
|
samples = (uint8_t*)sndbuf_getbuf(play_buf);
|
|
written = 0;
|
|
if (empty > count / 2)
|
|
empty = count / 2;
|
|
for (; empty > 0; empty--) {
|
|
val = (samples[readyptr++ % size] << 16);
|
|
val |= (samples[readyptr++ % size] << 24);
|
|
written += 2;
|
|
I2S_WRITE(sc, DA_TXFIFO, val);
|
|
}
|
|
sc->play_ptr += written;
|
|
sc->play_ptr %= size;
|
|
ret |= AUDIO_DAI_PLAY_INTR;
|
|
}
|
|
|
|
if (status & DA_ISTA_RXAI_INT) {
|
|
uint8_t *samples;
|
|
uint32_t count, size, freeptr, recorded, available;
|
|
|
|
val = I2S_READ(sc, DA_FSTA);
|
|
available = DA_FSTA_RXA_CNT(val);
|
|
|
|
count = sndbuf_getfree(rec_buf);
|
|
size = sndbuf_getsize(rec_buf);
|
|
freeptr = sndbuf_getfreeptr(rec_buf);
|
|
samples = (uint8_t*)sndbuf_getbuf(rec_buf);
|
|
recorded = 0;
|
|
if (available > count / 2)
|
|
available = count / 2;
|
|
|
|
for (; available > 0; available--) {
|
|
val = I2S_READ(sc, DA_RXFIFO);
|
|
samples[freeptr++ % size] = (val >> 16) & 0xff;
|
|
samples[freeptr++ % size] = (val >> 24) & 0xff;
|
|
recorded += 2;
|
|
}
|
|
sc->rec_ptr += recorded;
|
|
sc->rec_ptr %= size;
|
|
ret |= AUDIO_DAI_REC_INTR;
|
|
}
|
|
|
|
I2S_UNLOCK(sc);
|
|
|
|
return (ret);
|
|
}
|
|
|
|
static struct pcmchan_caps *
|
|
aw_i2s_dai_get_caps(device_t dev)
|
|
{
|
|
return (&aw_i2s_caps);
|
|
}
|
|
|
|
static int
|
|
aw_i2s_dai_trigger(device_t dev, int go, int pcm_dir)
|
|
{
|
|
struct aw_i2s_softc *sc = device_get_softc(dev);
|
|
uint32_t val;
|
|
|
|
if ((pcm_dir != PCMDIR_PLAY) && (pcm_dir != PCMDIR_REC))
|
|
return (EINVAL);
|
|
|
|
switch (go) {
|
|
case PCMTRIG_START:
|
|
if (pcm_dir == PCMDIR_PLAY) {
|
|
/* Flush FIFO */
|
|
val = I2S_READ(sc, DA_FCTL);
|
|
I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FTX);
|
|
I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FTX);
|
|
|
|
/* Reset TX sample counter */
|
|
I2S_WRITE(sc, DA_TXCNT, 0);
|
|
|
|
/* Enable TX block */
|
|
val = I2S_READ(sc, DA_CTL);
|
|
I2S_WRITE(sc, DA_CTL, val | DA_CTL_TXEN);
|
|
|
|
/* Enable TX underrun interrupt */
|
|
val = I2S_READ(sc, DA_INT);
|
|
I2S_WRITE(sc, DA_INT, val | DA_INT_TXEI_EN);
|
|
}
|
|
|
|
if (pcm_dir == PCMDIR_REC) {
|
|
/* Flush FIFO */
|
|
val = I2S_READ(sc, DA_FCTL);
|
|
I2S_WRITE(sc, DA_FCTL, val | DA_FCTL_FRX);
|
|
I2S_WRITE(sc, DA_FCTL, val & ~DA_FCTL_FRX);
|
|
|
|
/* Reset RX sample counter */
|
|
I2S_WRITE(sc, DA_RXCNT, 0);
|
|
|
|
/* Enable RX block */
|
|
val = I2S_READ(sc, DA_CTL);
|
|
I2S_WRITE(sc, DA_CTL, val | DA_CTL_RXEN);
|
|
|
|
/* Enable RX data available interrupt */
|
|
val = I2S_READ(sc, DA_INT);
|
|
I2S_WRITE(sc, DA_INT, val | DA_INT_RXAI_EN);
|
|
}
|
|
|
|
break;
|
|
|
|
case PCMTRIG_STOP:
|
|
case PCMTRIG_ABORT:
|
|
I2S_LOCK(sc);
|
|
|
|
if (pcm_dir == PCMDIR_PLAY) {
|
|
/* Disable TX block */
|
|
val = I2S_READ(sc, DA_CTL);
|
|
I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_TXEN);
|
|
|
|
/* Enable TX underrun interrupt */
|
|
val = I2S_READ(sc, DA_INT);
|
|
I2S_WRITE(sc, DA_INT, val & ~DA_INT_TXEI_EN);
|
|
|
|
sc->play_ptr = 0;
|
|
} else {
|
|
/* Disable RX block */
|
|
val = I2S_READ(sc, DA_CTL);
|
|
I2S_WRITE(sc, DA_CTL, val & ~DA_CTL_RXEN);
|
|
|
|
/* Disable RX data available interrupt */
|
|
val = I2S_READ(sc, DA_INT);
|
|
I2S_WRITE(sc, DA_INT, val & ~DA_INT_RXAI_EN);
|
|
|
|
sc->rec_ptr = 0;
|
|
}
|
|
|
|
I2S_UNLOCK(sc);
|
|
break;
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static uint32_t
|
|
aw_i2s_dai_get_ptr(device_t dev, int pcm_dir)
|
|
{
|
|
struct aw_i2s_softc *sc;
|
|
uint32_t ptr;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
I2S_LOCK(sc);
|
|
if (pcm_dir == PCMDIR_PLAY)
|
|
ptr = sc->play_ptr;
|
|
else
|
|
ptr = sc->rec_ptr;
|
|
I2S_UNLOCK(sc);
|
|
|
|
return ptr;
|
|
}
|
|
|
|
static int
|
|
aw_i2s_dai_setup_intr(device_t dev, driver_intr_t intr_handler, void *intr_arg)
|
|
{
|
|
struct aw_i2s_softc *sc = device_get_softc(dev);
|
|
|
|
if (bus_setup_intr(dev, sc->res[1],
|
|
INTR_TYPE_MISC | INTR_MPSAFE, NULL, intr_handler, intr_arg,
|
|
&sc->intrhand)) {
|
|
device_printf(dev, "cannot setup interrupt handler\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static uint32_t
|
|
aw_i2s_dai_set_chanformat(device_t dev, uint32_t format)
|
|
{
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
aw_i2s_dai_set_sysclk(device_t dev, unsigned int rate, int dai_dir)
|
|
{
|
|
struct aw_i2s_softc *sc;
|
|
int bclk_val, mclk_val;
|
|
uint32_t val;
|
|
int error;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
error = clk_set_freq(sc->clk, AW_I2S_CLK_RATE, CLK_SET_ROUND_DOWN);
|
|
if (error != 0) {
|
|
device_printf(sc->dev,
|
|
"couldn't set mod clock rate to %u Hz: %d\n", AW_I2S_CLK_RATE, error);
|
|
return error;
|
|
}
|
|
error = clk_enable(sc->clk);
|
|
if (error != 0) {
|
|
device_printf(sc->dev,
|
|
"couldn't enable mod clock: %d\n", error);
|
|
return error;
|
|
}
|
|
|
|
const u_int bclk_prate = I2S_TYPE(sc) == SUNXI_I2S_SUN4I ? rate : AW_I2S_CLK_RATE;
|
|
|
|
const u_int bclk_div = bclk_prate / (2 * 32 * AW_I2S_SAMPLE_RATE);
|
|
const u_int mclk_div = AW_I2S_CLK_RATE / rate;
|
|
|
|
if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
|
|
bclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_bclk_divmap,
|
|
nitems(sun4i_i2s_bclk_divmap), bclk_div);
|
|
mclk_val = sunxi_i2s_div_to_regval(sun4i_i2s_mclk_divmap,
|
|
nitems(sun4i_i2s_mclk_divmap), mclk_div);
|
|
} else {
|
|
bclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap,
|
|
nitems(sun8i_i2s_divmap), bclk_div);
|
|
mclk_val = sunxi_i2s_div_to_regval(sun8i_i2s_divmap,
|
|
nitems(sun8i_i2s_divmap), mclk_div);
|
|
}
|
|
if (bclk_val == -1 || mclk_val == -1) {
|
|
device_printf(sc->dev, "couldn't configure bclk/mclk dividers\n");
|
|
return EIO;
|
|
}
|
|
|
|
val = I2S_READ(sc, DA_CLKD);
|
|
if (I2S_TYPE(sc) == SUNXI_I2S_SUN4I) {
|
|
val |= DA_CLKD_MCLKO_EN_SUN4I;
|
|
val &= ~DA_CLKD_BCLKDIV_SUN4I_MASK;
|
|
val |= DA_CLKD_BCLKDIV_SUN4I(bclk_val);
|
|
} else {
|
|
val |= DA_CLKD_MCLKO_EN_SUN8I;
|
|
val &= ~DA_CLKD_BCLKDIV_SUN8I_MASK;
|
|
val |= DA_CLKD_BCLKDIV_SUN8I(bclk_val);
|
|
}
|
|
val &= ~DA_CLKD_MCLKDIV_MASK;
|
|
val |= DA_CLKD_MCLKDIV(mclk_val);
|
|
I2S_WRITE(sc, DA_CLKD, val);
|
|
|
|
|
|
return (0);
|
|
}
|
|
|
|
static uint32_t
|
|
aw_i2s_dai_set_chanspeed(device_t dev, uint32_t speed)
|
|
{
|
|
|
|
return (speed);
|
|
}
|
|
|
|
static device_method_t aw_i2s_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, aw_i2s_probe),
|
|
DEVMETHOD(device_attach, aw_i2s_attach),
|
|
DEVMETHOD(device_detach, aw_i2s_detach),
|
|
|
|
DEVMETHOD(audio_dai_init, aw_i2s_dai_init),
|
|
DEVMETHOD(audio_dai_setup_intr, aw_i2s_dai_setup_intr),
|
|
DEVMETHOD(audio_dai_set_sysclk, aw_i2s_dai_set_sysclk),
|
|
DEVMETHOD(audio_dai_set_chanspeed, aw_i2s_dai_set_chanspeed),
|
|
DEVMETHOD(audio_dai_set_chanformat, aw_i2s_dai_set_chanformat),
|
|
DEVMETHOD(audio_dai_intr, aw_i2s_dai_intr),
|
|
DEVMETHOD(audio_dai_get_caps, aw_i2s_dai_get_caps),
|
|
DEVMETHOD(audio_dai_trigger, aw_i2s_dai_trigger),
|
|
DEVMETHOD(audio_dai_get_ptr, aw_i2s_dai_get_ptr),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t aw_i2s_driver = {
|
|
"i2s",
|
|
aw_i2s_methods,
|
|
sizeof(struct aw_i2s_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(aw_i2s, simplebus, aw_i2s_driver, 0, 0);
|
|
SIMPLEBUS_PNP_INFO(compat_data);
|