726 lines
18 KiB
C
726 lines
18 KiB
C
/*-
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* Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Allwinner thermal sensor controller
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/eventhandler.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/sysctl.h>
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#include <sys/reboot.h>
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#include <sys/module.h>
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#include <sys/cpu.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/nvmem/nvmem.h>
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#include <arm/allwinner/aw_sid.h>
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#include "cpufreq_if.h"
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#include "nvmem_if.h"
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#define THS_CTRL0 0x00
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#define THS_CTRL1 0x04
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#define ADC_CALI_EN (1 << 17)
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#define THS_CTRL2 0x40
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#define SENSOR_ACQ1_SHIFT 16
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#define SENSOR2_EN (1 << 2)
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#define SENSOR1_EN (1 << 1)
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#define SENSOR0_EN (1 << 0)
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#define THS_INTC 0x44
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#define THS_THERMAL_PER_SHIFT 12
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#define THS_INTS 0x48
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#define THS2_DATA_IRQ_STS (1 << 10)
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#define THS1_DATA_IRQ_STS (1 << 9)
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#define THS0_DATA_IRQ_STS (1 << 8)
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#define SHUT_INT2_STS (1 << 6)
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#define SHUT_INT1_STS (1 << 5)
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#define SHUT_INT0_STS (1 << 4)
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#define ALARM_INT2_STS (1 << 2)
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#define ALARM_INT1_STS (1 << 1)
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#define ALARM_INT0_STS (1 << 0)
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#define THS_ALARM0_CTRL 0x50
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#define ALARM_T_HOT_MASK 0xfff
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#define ALARM_T_HOT_SHIFT 16
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#define ALARM_T_HYST_MASK 0xfff
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#define ALARM_T_HYST_SHIFT 0
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#define THS_SHUTDOWN0_CTRL 0x60
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#define SHUT_T_HOT_MASK 0xfff
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#define SHUT_T_HOT_SHIFT 16
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#define THS_FILTER 0x70
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#define THS_CALIB0 0x74
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#define THS_CALIB1 0x78
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#define THS_DATA0 0x80
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#define THS_DATA1 0x84
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#define THS_DATA2 0x88
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#define DATA_MASK 0xfff
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#define A83T_CLK_RATE 24000000
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#define A83T_ADC_ACQUIRE_TIME 23 /* 24Mhz/(23 + 1) = 1us */
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#define A83T_THERMAL_PER 1 /* 4096 * (1 + 1) / 24Mhz = 341 us */
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#define A83T_FILTER 0x5 /* Filter enabled, avg of 4 */
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#define A83T_TEMP_BASE 2719000
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#define A83T_TEMP_MUL 1000
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#define A83T_TEMP_DIV 14186
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#define A64_CLK_RATE 4000000
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#define A64_ADC_ACQUIRE_TIME 400 /* 4Mhz/(400 + 1) = 100 us */
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#define A64_THERMAL_PER 24 /* 4096 * (24 + 1) / 4Mhz = 25.6 ms */
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#define A64_FILTER 0x6 /* Filter enabled, avg of 8 */
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#define A64_TEMP_BASE 2170000
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#define A64_TEMP_MUL 1000
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#define A64_TEMP_DIV 8560
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#define H3_CLK_RATE 4000000
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#define H3_ADC_ACQUIRE_TIME 0x3f
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#define H3_THERMAL_PER 401
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#define H3_FILTER 0x6 /* Filter enabled, avg of 8 */
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#define H3_TEMP_BASE 217
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#define H3_TEMP_MUL 1000
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#define H3_TEMP_DIV 8253
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#define H3_TEMP_MINUS 1794000
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#define H3_INIT_ALARM 90 /* degC */
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#define H3_INIT_SHUT 105 /* degC */
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#define H5_CLK_RATE 24000000
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#define H5_ADC_ACQUIRE_TIME 479 /* 24Mhz/479 = 20us */
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#define H5_THERMAL_PER 58 /* 4096 * (58 + 1) / 24Mhz = 10ms */
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#define H5_FILTER 0x6 /* Filter enabled, avg of 8 */
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#define H5_TEMP_BASE 233832448
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#define H5_TEMP_MUL 124885
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#define H5_TEMP_DIV 20
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#define H5_TEMP_BASE_CPU 271581184
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#define H5_TEMP_MUL_CPU 152253
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#define H5_TEMP_BASE_GPU 289406976
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#define H5_TEMP_MUL_GPU 166724
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#define H5_INIT_CPU_ALARM 80 /* degC */
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#define H5_INIT_CPU_SHUT 96 /* degC */
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#define H5_INIT_GPU_ALARM 84 /* degC */
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#define H5_INIT_GPU_SHUT 100 /* degC */
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#define TEMP_C_TO_K 273
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#define SENSOR_ENABLE_ALL (SENSOR0_EN|SENSOR1_EN|SENSOR2_EN)
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#define SHUT_INT_ALL (SHUT_INT0_STS|SHUT_INT1_STS|SHUT_INT2_STS)
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#define ALARM_INT_ALL (ALARM_INT0_STS)
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#define MAX_SENSORS 3
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#define MAX_CF_LEVELS 64
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#define THROTTLE_ENABLE_DEFAULT 1
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/* Enable thermal throttling */
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static int aw_thermal_throttle_enable = THROTTLE_ENABLE_DEFAULT;
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TUNABLE_INT("hw.aw_thermal.throttle_enable", &aw_thermal_throttle_enable);
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struct aw_thermal_sensor {
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const char *name;
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const char *desc;
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int init_alarm;
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int init_shut;
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};
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struct aw_thermal_config {
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struct aw_thermal_sensor sensors[MAX_SENSORS];
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int nsensors;
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uint64_t clk_rate;
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uint32_t adc_acquire_time;
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int adc_cali_en;
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uint32_t filter;
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uint32_t thermal_per;
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int (*to_temp)(uint32_t, int);
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uint32_t (*to_reg)(int, int);
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int temp_base;
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int temp_mul;
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int temp_div;
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int calib0, calib1;
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uint32_t calib0_mask, calib1_mask;
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};
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static int
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a83t_to_temp(uint32_t val, int sensor)
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{
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return ((A83T_TEMP_BASE - (val * A83T_TEMP_MUL)) / A83T_TEMP_DIV);
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}
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static const struct aw_thermal_config a83t_config = {
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.nsensors = 3,
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.sensors = {
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[0] = {
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.name = "cluster0",
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.desc = "CPU cluster 0 temperature",
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},
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[1] = {
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.name = "cluster1",
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.desc = "CPU cluster 1 temperature",
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},
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[2] = {
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.name = "gpu",
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.desc = "GPU temperature",
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},
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},
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.clk_rate = A83T_CLK_RATE,
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.adc_acquire_time = A83T_ADC_ACQUIRE_TIME,
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.adc_cali_en = 1,
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.filter = A83T_FILTER,
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.thermal_per = A83T_THERMAL_PER,
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.to_temp = a83t_to_temp,
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.calib0_mask = 0xffffffff,
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.calib1_mask = 0xffff,
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};
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static int
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a64_to_temp(uint32_t val, int sensor)
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{
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return ((A64_TEMP_BASE - (val * A64_TEMP_MUL)) / A64_TEMP_DIV);
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}
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static const struct aw_thermal_config a64_config = {
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.nsensors = 3,
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.sensors = {
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[0] = {
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.name = "cpu",
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.desc = "CPU temperature",
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},
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[1] = {
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.name = "gpu1",
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.desc = "GPU temperature 1",
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},
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[2] = {
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.name = "gpu2",
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.desc = "GPU temperature 2",
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},
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},
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.clk_rate = A64_CLK_RATE,
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.adc_acquire_time = A64_ADC_ACQUIRE_TIME,
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.adc_cali_en = 1,
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.filter = A64_FILTER,
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.thermal_per = A64_THERMAL_PER,
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.to_temp = a64_to_temp,
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.calib0_mask = 0xffffffff,
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.calib1_mask = 0xffff,
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};
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static int
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h3_to_temp(uint32_t val, int sensor)
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{
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return (H3_TEMP_BASE - ((val * H3_TEMP_MUL) / H3_TEMP_DIV));
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}
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static uint32_t
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h3_to_reg(int val, int sensor)
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{
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return ((H3_TEMP_MINUS - (val * H3_TEMP_DIV)) / H3_TEMP_MUL);
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}
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static const struct aw_thermal_config h3_config = {
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.nsensors = 1,
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.sensors = {
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[0] = {
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.name = "cpu",
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.desc = "CPU temperature",
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.init_alarm = H3_INIT_ALARM,
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.init_shut = H3_INIT_SHUT,
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},
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},
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.clk_rate = H3_CLK_RATE,
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.adc_acquire_time = H3_ADC_ACQUIRE_TIME,
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.adc_cali_en = 1,
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.filter = H3_FILTER,
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.thermal_per = H3_THERMAL_PER,
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.to_temp = h3_to_temp,
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.to_reg = h3_to_reg,
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.calib0_mask = 0xffffffff,
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};
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static int
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h5_to_temp(uint32_t val, int sensor)
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{
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int tmp;
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/* Temp is lower than 70 degrees */
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if (val > 0x500) {
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tmp = H5_TEMP_BASE - (val * H5_TEMP_MUL);
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tmp >>= H5_TEMP_DIV;
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return (tmp);
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}
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if (sensor == 0)
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tmp = H5_TEMP_BASE_CPU - (val * H5_TEMP_MUL_CPU);
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else if (sensor == 1)
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tmp = H5_TEMP_BASE_GPU - (val * H5_TEMP_MUL_GPU);
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else {
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printf("Unknown sensor %d\n", sensor);
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return (val);
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}
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tmp >>= H5_TEMP_DIV;
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return (tmp);
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}
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static uint32_t
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h5_to_reg(int val, int sensor)
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{
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int tmp;
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if (val < 70) {
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tmp = H5_TEMP_BASE - (val << H5_TEMP_DIV);
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tmp /= H5_TEMP_MUL;
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} else {
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if (sensor == 0) {
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tmp = H5_TEMP_BASE_CPU - (val << H5_TEMP_DIV);
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tmp /= H5_TEMP_MUL_CPU;
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} else if (sensor == 1) {
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tmp = H5_TEMP_BASE_GPU - (val << H5_TEMP_DIV);
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tmp /= H5_TEMP_MUL_GPU;
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} else {
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printf("Unknown sensor %d\n", sensor);
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return (val);
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}
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}
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return ((uint32_t)tmp);
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}
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static const struct aw_thermal_config h5_config = {
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.nsensors = 2,
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.sensors = {
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[0] = {
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.name = "cpu",
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.desc = "CPU temperature",
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.init_alarm = H5_INIT_CPU_ALARM,
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.init_shut = H5_INIT_CPU_SHUT,
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},
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[1] = {
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.name = "gpu",
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.desc = "GPU temperature",
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.init_alarm = H5_INIT_GPU_ALARM,
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.init_shut = H5_INIT_GPU_SHUT,
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},
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},
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.clk_rate = H5_CLK_RATE,
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.adc_acquire_time = H5_ADC_ACQUIRE_TIME,
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.filter = H5_FILTER,
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.thermal_per = H5_THERMAL_PER,
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.to_temp = h5_to_temp,
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.to_reg = h5_to_reg,
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.calib0_mask = 0xffffffff,
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};
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun8i-a83t-ths", (uintptr_t)&a83t_config },
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{ "allwinner,sun8i-h3-ths", (uintptr_t)&h3_config },
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{ "allwinner,sun50i-a64-ths", (uintptr_t)&a64_config },
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{ "allwinner,sun50i-h5-ths", (uintptr_t)&h5_config },
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{ NULL, (uintptr_t)NULL }
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};
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#define THS_CONF(d) \
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(void *)ofw_bus_search_compatible((d), compat_data)->ocd_data
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struct aw_thermal_softc {
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device_t dev;
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struct resource *res[2];
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struct aw_thermal_config *conf;
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struct task cf_task;
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int throttle;
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int min_freq;
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struct cf_level levels[MAX_CF_LEVELS];
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eventhandler_tag cf_pre_tag;
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clk_t clk_apb;
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clk_t clk_ths;
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};
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static struct resource_spec aw_thermal_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ SYS_RES_IRQ, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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#define RD4(sc, reg) bus_read_4((sc)->res[0], (reg))
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#define WR4(sc, reg, val) bus_write_4((sc)->res[0], (reg), (val))
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static int
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aw_thermal_init(struct aw_thermal_softc *sc)
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{
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phandle_t node;
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uint32_t calib[2];
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int error;
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node = ofw_bus_get_node(sc->dev);
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if (nvmem_get_cell_len(node, "calibration") > sizeof(calib)) {
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device_printf(sc->dev, "calibration nvmem cell is too large\n");
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return (ENXIO);
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}
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error = nvmem_read_cell_by_name(node, "calibration",
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(void *)&calib, nvmem_get_cell_len(node, "calibration"));
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/* Read calibration settings from EFUSE */
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if (error != 0) {
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device_printf(sc->dev, "Cannot read THS efuse\n");
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return (error);
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}
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calib[0] &= sc->conf->calib0_mask;
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calib[1] &= sc->conf->calib1_mask;
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/* Write calibration settings to thermal controller */
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if (calib[0] != 0)
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WR4(sc, THS_CALIB0, calib[0]);
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if (calib[1] != 0)
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WR4(sc, THS_CALIB1, calib[1]);
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/* Configure ADC acquire time (CLK_IN/(N+1)) and enable sensors */
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WR4(sc, THS_CTRL1, ADC_CALI_EN);
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WR4(sc, THS_CTRL0, sc->conf->adc_acquire_time);
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WR4(sc, THS_CTRL2, sc->conf->adc_acquire_time << SENSOR_ACQ1_SHIFT);
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/* Set thermal period */
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WR4(sc, THS_INTC, sc->conf->thermal_per << THS_THERMAL_PER_SHIFT);
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/* Enable average filter */
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WR4(sc, THS_FILTER, sc->conf->filter);
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/* Enable interrupts */
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WR4(sc, THS_INTS, RD4(sc, THS_INTS));
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WR4(sc, THS_INTC, RD4(sc, THS_INTC) | SHUT_INT_ALL | ALARM_INT_ALL);
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/* Enable sensors */
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WR4(sc, THS_CTRL2, RD4(sc, THS_CTRL2) | SENSOR_ENABLE_ALL);
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return (0);
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}
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static int
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aw_thermal_gettemp(struct aw_thermal_softc *sc, int sensor)
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{
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uint32_t val;
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val = RD4(sc, THS_DATA0 + (sensor * 4));
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return (sc->conf->to_temp(val, sensor));
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}
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static int
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aw_thermal_getshut(struct aw_thermal_softc *sc, int sensor)
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{
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uint32_t val;
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val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
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val = (val >> SHUT_T_HOT_SHIFT) & SHUT_T_HOT_MASK;
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return (sc->conf->to_temp(val, sensor));
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}
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static void
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aw_thermal_setshut(struct aw_thermal_softc *sc, int sensor, int temp)
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{
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uint32_t val;
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val = RD4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4));
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val &= ~(SHUT_T_HOT_MASK << SHUT_T_HOT_SHIFT);
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val |= (sc->conf->to_reg(temp, sensor) << SHUT_T_HOT_SHIFT);
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WR4(sc, THS_SHUTDOWN0_CTRL + (sensor * 4), val);
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}
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static int
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aw_thermal_gethyst(struct aw_thermal_softc *sc, int sensor)
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{
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uint32_t val;
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val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
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val = (val >> ALARM_T_HYST_SHIFT) & ALARM_T_HYST_MASK;
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return (sc->conf->to_temp(val, sensor));
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}
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static int
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aw_thermal_getalarm(struct aw_thermal_softc *sc, int sensor)
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|
{
|
|
uint32_t val;
|
|
|
|
val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
|
|
val = (val >> ALARM_T_HOT_SHIFT) & ALARM_T_HOT_MASK;
|
|
|
|
return (sc->conf->to_temp(val, sensor));
|
|
}
|
|
|
|
static void
|
|
aw_thermal_setalarm(struct aw_thermal_softc *sc, int sensor, int temp)
|
|
{
|
|
uint32_t val;
|
|
|
|
val = RD4(sc, THS_ALARM0_CTRL + (sensor * 4));
|
|
val &= ~(ALARM_T_HOT_MASK << ALARM_T_HOT_SHIFT);
|
|
val |= (sc->conf->to_reg(temp, sensor) << ALARM_T_HOT_SHIFT);
|
|
WR4(sc, THS_ALARM0_CTRL + (sensor * 4), val);
|
|
}
|
|
|
|
static int
|
|
aw_thermal_sysctl(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
struct aw_thermal_softc *sc;
|
|
int sensor, val;
|
|
|
|
sc = arg1;
|
|
sensor = arg2;
|
|
|
|
val = aw_thermal_gettemp(sc, sensor) + TEMP_C_TO_K;
|
|
|
|
return sysctl_handle_opaque(oidp, &val, sizeof(val), req);
|
|
}
|
|
|
|
static void
|
|
aw_thermal_throttle(struct aw_thermal_softc *sc, int enable)
|
|
{
|
|
device_t cf_dev;
|
|
int count, error;
|
|
|
|
if (enable == sc->throttle)
|
|
return;
|
|
|
|
if (enable != 0) {
|
|
/* Set the lowest available frequency */
|
|
cf_dev = devclass_get_device(devclass_find("cpufreq"), 0);
|
|
if (cf_dev == NULL)
|
|
return;
|
|
count = MAX_CF_LEVELS;
|
|
error = CPUFREQ_LEVELS(cf_dev, sc->levels, &count);
|
|
if (error != 0 || count == 0)
|
|
return;
|
|
sc->min_freq = sc->levels[count - 1].total_set.freq;
|
|
error = CPUFREQ_SET(cf_dev, &sc->levels[count - 1],
|
|
CPUFREQ_PRIO_USER);
|
|
if (error != 0)
|
|
return;
|
|
}
|
|
|
|
sc->throttle = enable;
|
|
}
|
|
|
|
static void
|
|
aw_thermal_cf_task(void *arg, int pending)
|
|
{
|
|
struct aw_thermal_softc *sc;
|
|
|
|
sc = arg;
|
|
|
|
aw_thermal_throttle(sc, 1);
|
|
}
|
|
|
|
static void
|
|
aw_thermal_cf_pre_change(void *arg, const struct cf_level *level, int *status)
|
|
{
|
|
struct aw_thermal_softc *sc;
|
|
int temp_cur, temp_alarm;
|
|
|
|
sc = arg;
|
|
|
|
if (aw_thermal_throttle_enable == 0 || sc->throttle == 0 ||
|
|
level->total_set.freq == sc->min_freq)
|
|
return;
|
|
|
|
temp_cur = aw_thermal_gettemp(sc, 0);
|
|
temp_alarm = aw_thermal_getalarm(sc, 0);
|
|
|
|
if (temp_cur < temp_alarm)
|
|
aw_thermal_throttle(sc, 0);
|
|
else
|
|
*status = ENXIO;
|
|
}
|
|
|
|
static void
|
|
aw_thermal_intr(void *arg)
|
|
{
|
|
struct aw_thermal_softc *sc;
|
|
device_t dev;
|
|
uint32_t ints;
|
|
|
|
dev = arg;
|
|
sc = device_get_softc(dev);
|
|
|
|
ints = RD4(sc, THS_INTS);
|
|
WR4(sc, THS_INTS, ints);
|
|
|
|
if ((ints & SHUT_INT_ALL) != 0) {
|
|
device_printf(dev,
|
|
"WARNING - current temperature exceeds safe limits\n");
|
|
shutdown_nice(RB_POWEROFF);
|
|
}
|
|
|
|
if ((ints & ALARM_INT_ALL) != 0)
|
|
taskqueue_enqueue(taskqueue_thread, &sc->cf_task);
|
|
}
|
|
|
|
static int
|
|
aw_thermal_probe(device_t dev)
|
|
{
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (THS_CONF(dev) == NULL)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Allwinner Thermal Sensor Controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
aw_thermal_attach(device_t dev)
|
|
{
|
|
struct aw_thermal_softc *sc;
|
|
hwreset_t rst;
|
|
int i, error;
|
|
void *ih;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
rst = NULL;
|
|
ih = NULL;
|
|
|
|
sc->conf = THS_CONF(dev);
|
|
TASK_INIT(&sc->cf_task, 0, aw_thermal_cf_task, sc);
|
|
|
|
if (bus_alloc_resources(dev, aw_thermal_spec, sc->res) != 0) {
|
|
device_printf(dev, "cannot allocate resources for device\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "bus", &sc->clk_apb) == 0) {
|
|
error = clk_enable(sc->clk_apb);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot enable apb clock\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
if (clk_get_by_ofw_name(dev, 0, "mod", &sc->clk_ths) == 0) {
|
|
error = clk_set_freq(sc->clk_ths, sc->conf->clk_rate, 0);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot set ths clock rate\n");
|
|
goto fail;
|
|
}
|
|
error = clk_enable(sc->clk_ths);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot enable ths clock\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
if (hwreset_get_by_ofw_idx(dev, 0, 0, &rst) == 0) {
|
|
error = hwreset_deassert(rst);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot de-assert reset\n");
|
|
goto fail;
|
|
}
|
|
}
|
|
|
|
error = bus_setup_intr(dev, sc->res[1], INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, aw_thermal_intr, dev, &ih);
|
|
if (error != 0) {
|
|
device_printf(dev, "cannot setup interrupt handler\n");
|
|
goto fail;
|
|
}
|
|
|
|
for (i = 0; i < sc->conf->nsensors; i++) {
|
|
if (sc->conf->sensors[i].init_alarm > 0)
|
|
aw_thermal_setalarm(sc, i,
|
|
sc->conf->sensors[i].init_alarm);
|
|
if (sc->conf->sensors[i].init_shut > 0)
|
|
aw_thermal_setshut(sc, i,
|
|
sc->conf->sensors[i].init_shut);
|
|
}
|
|
|
|
if (aw_thermal_init(sc) != 0)
|
|
goto fail;
|
|
|
|
for (i = 0; i < sc->conf->nsensors; i++)
|
|
SYSCTL_ADD_PROC(device_get_sysctl_ctx(dev),
|
|
SYSCTL_CHILDREN(device_get_sysctl_tree(dev)),
|
|
OID_AUTO, sc->conf->sensors[i].name,
|
|
CTLTYPE_INT | CTLFLAG_RD | CTLFLAG_NEEDGIANT,
|
|
sc, i, aw_thermal_sysctl, "IK0",
|
|
sc->conf->sensors[i].desc);
|
|
|
|
if (bootverbose)
|
|
for (i = 0; i < sc->conf->nsensors; i++) {
|
|
device_printf(dev,
|
|
"%s: alarm %dC hyst %dC shut %dC\n",
|
|
sc->conf->sensors[i].name,
|
|
aw_thermal_getalarm(sc, i),
|
|
aw_thermal_gethyst(sc, i),
|
|
aw_thermal_getshut(sc, i));
|
|
}
|
|
|
|
sc->cf_pre_tag = EVENTHANDLER_REGISTER(cpufreq_pre_change,
|
|
aw_thermal_cf_pre_change, sc, EVENTHANDLER_PRI_FIRST);
|
|
|
|
return (0);
|
|
|
|
fail:
|
|
if (ih != NULL)
|
|
bus_teardown_intr(dev, sc->res[1], ih);
|
|
if (rst != NULL)
|
|
hwreset_release(rst);
|
|
if (sc->clk_apb != NULL)
|
|
clk_release(sc->clk_apb);
|
|
if (sc->clk_ths != NULL)
|
|
clk_release(sc->clk_ths);
|
|
bus_release_resources(dev, aw_thermal_spec, sc->res);
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static device_method_t aw_thermal_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, aw_thermal_probe),
|
|
DEVMETHOD(device_attach, aw_thermal_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t aw_thermal_driver = {
|
|
"aw_thermal",
|
|
aw_thermal_methods,
|
|
sizeof(struct aw_thermal_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(aw_thermal, simplebus, aw_thermal_driver, 0, 0);
|
|
MODULE_VERSION(aw_thermal, 1);
|
|
MODULE_DEPEND(aw_thermal, aw_sid, 1, 1, 1);
|
|
SIMPLEBUS_PNP_INFO(compat_data);
|