296 lines
7.8 KiB
C
296 lines
7.8 KiB
C
/* $NetBSD: sunxi_usb3phy.c,v 1.1 2018/05/01 23:59:42 jmcneill Exp $ */
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/*-
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* Copyright (c) 2018 Jared McNeill <jmcneill@invisible.ca>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
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* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
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* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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/*
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* Allwinner USB3PHY
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/extres/phy/phy_usb.h>
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#include "phynode_if.h"
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#define USB3PHY_APP 0x00
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#define APP_FORCE_VBUS (0x3 << 12)
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#define USB3PHY_PIPE_CLOCK_CONTROL 0x14
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#define PCC_PIPE_CLK_OPEN (1 << 6)
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#define USB3PHY_PHY_TUNE_LOW 0x18
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#define PTL_MAGIC 0x0047fc87
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#define USB3PHY_PHY_TUNE_HIGH 0x1c
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#define PTH_TX_DEEMPH_3P5DB (0x1F << 19)
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#define PTH_TX_DEEMPH_6DB (0x3F << 13)
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#define PTH_TX_SWING_FULL (0x7F << 6)
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#define PTH_LOS_BIAS (0x7 << 3)
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#define PTH_TX_BOOST_LVL (0x7 << 0)
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#define USB3PHY_PHY_EXTERNAL_CONTROL 0x20
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#define PEC_REF_SSP_EN (1 << 26)
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#define PEC_SSC_EN (1 << 24)
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#define PEC_EXTERN_VBUS (0x3 << 1)
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#define __LOWEST_SET_BIT(__mask) ((((__mask) - 1) & (__mask)) ^ (__mask))
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#define __SHIFTIN(__x, __mask) ((__x) * __LOWEST_SET_BIT(__mask))
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static struct ofw_compat_data compat_data[] = {
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{ "allwinner,sun50i-h6-usb3-phy", 1 },
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{ NULL, 0 }
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};
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static struct resource_spec aw_usb3phy_spec[] = {
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{ SYS_RES_MEMORY, 0, RF_ACTIVE },
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{ -1, 0 }
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};
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struct awusb3phy_softc {
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struct resource * res;
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regulator_t reg;
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int mode;
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};
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/* Phy class and methods. */
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static int awusb3phy_phy_enable(struct phynode *phy, bool enable);
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static int awusb3phy_get_mode(struct phynode *phy, int *mode);
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static int awusb3phy_set_mode(struct phynode *phy, int mode);
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static phynode_usb_method_t awusb3phy_phynode_methods[] = {
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PHYNODEMETHOD(phynode_enable, awusb3phy_phy_enable),
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PHYNODEMETHOD(phynode_usb_get_mode, awusb3phy_get_mode),
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PHYNODEMETHOD(phynode_usb_set_mode, awusb3phy_set_mode),
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PHYNODEMETHOD_END
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};
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DEFINE_CLASS_1(awusb3phy_phynode, awusb3phy_phynode_class, awusb3phy_phynode_methods,
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sizeof(struct phynode_usb_sc), phynode_usb_class);
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#define RD4(res, o) bus_read_4(res, (o))
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#define WR4(res, o, v) bus_write_4(res, (o), (v))
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static int
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awusb3phy_phy_enable(struct phynode *phynode, bool enable)
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{
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struct awusb3phy_softc *sc;
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device_t dev;
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uint32_t val;
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int error = 0;
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dev = phynode_get_device(phynode);
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sc = device_get_softc(dev);
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device_printf(dev, "%s: called\n", __func__);
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if (enable) {
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val = RD4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL);
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device_printf(dev, "EXTERNAL_CONTROL: %x\n", val);
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val |= PEC_EXTERN_VBUS;
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val |= PEC_SSC_EN;
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val |= PEC_REF_SSP_EN;
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device_printf(dev, "EXTERNAL_CONTROL: %x\n", val);
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WR4(sc->res, USB3PHY_PHY_EXTERNAL_CONTROL, val);
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val = RD4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL);
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device_printf(dev, "PIPE_CONTROL: %x\n", val);
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val |= PCC_PIPE_CLK_OPEN;
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device_printf(dev, "PIPE_CONTROL: %x\n", val);
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WR4(sc->res, USB3PHY_PIPE_CLOCK_CONTROL, val);
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val = RD4(sc->res, USB3PHY_APP);
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device_printf(dev, "APP: %x\n", val);
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val |= APP_FORCE_VBUS;
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device_printf(dev, "APP: %x\n", val);
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WR4(sc->res, USB3PHY_APP, val);
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WR4(sc->res, USB3PHY_PHY_TUNE_LOW, PTL_MAGIC);
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val = RD4(sc->res, USB3PHY_PHY_TUNE_HIGH);
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device_printf(dev, "PHY_TUNE_HIGH: %x\n", val);
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val |= PTH_TX_BOOST_LVL;
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val |= PTH_LOS_BIAS;
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val &= ~PTH_TX_SWING_FULL;
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val |= __SHIFTIN(0x55, PTH_TX_SWING_FULL);
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val &= ~PTH_TX_DEEMPH_6DB;
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val |= __SHIFTIN(0x20, PTH_TX_DEEMPH_6DB);
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val &= ~PTH_TX_DEEMPH_3P5DB;
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val |= __SHIFTIN(0x15, PTH_TX_DEEMPH_3P5DB);
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device_printf(dev, "PHY_TUNE_HIGH: %x\n", val);
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WR4(sc->res, USB3PHY_PHY_TUNE_HIGH, val);
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if (sc->reg)
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error = regulator_enable(sc->reg);
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} else {
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if (sc->reg)
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error = regulator_disable(sc->reg);
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}
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if (error != 0) {
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device_printf(dev,
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"couldn't %s regulator for phy\n",
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enable ? "enable" : "disable");
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return (error);
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}
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return (0);
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}
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static int
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awusb3phy_get_mode(struct phynode *phynode, int *mode)
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{
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struct awusb3phy_softc *sc;
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device_t dev;
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dev = phynode_get_device(phynode);
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sc = device_get_softc(dev);
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*mode = sc->mode;
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return (0);
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}
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static int
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awusb3phy_set_mode(struct phynode *phynode, int mode)
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{
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device_t dev;
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struct awusb3phy_softc *sc;
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dev = phynode_get_device(phynode);
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sc = device_get_softc(dev);
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if (mode != PHY_USB_MODE_HOST)
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return (EINVAL);
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sc->mode = mode;
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return (0);
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}
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static int
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awusb3phy_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Allwinner USB3PHY");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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awusb3phy_attach(device_t dev)
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{
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struct phynode *phynode;
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struct phynode_init_def phy_init;
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struct awusb3phy_softc *sc;
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clk_t clk;
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hwreset_t rst;
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phandle_t node;
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int error, i;
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sc = device_get_softc(dev);
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node = ofw_bus_get_node(dev);
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if (bus_alloc_resources(dev, aw_usb3phy_spec, &sc->res) != 0) {
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device_printf(dev, "cannot allocate resources for device\n");
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return (ENXIO);
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}
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/* Enable clocks */
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for (i = 0; clk_get_by_ofw_index(dev, 0, i, &clk) == 0; i++) {
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error = clk_enable(clk);
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if (error != 0) {
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device_printf(dev, "couldn't enable clock %s\n",
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clk_get_name(clk));
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return (error);
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}
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}
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/* De-assert resets */
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for (i = 0; hwreset_get_by_ofw_idx(dev, 0, i, &rst) == 0; i++) {
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error = hwreset_deassert(rst);
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if (error != 0) {
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device_printf(dev, "couldn't de-assert reset %d\n",
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i);
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return (error);
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}
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}
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/* Get regulators */
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regulator_get_by_ofw_property(dev, node, "phy-supply", &sc->reg);
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/* Create the phy */
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phy_init.ofw_node = ofw_bus_get_node(dev);
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phynode = phynode_create(dev, &awusb3phy_phynode_class,
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&phy_init);
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if (phynode == NULL) {
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device_printf(dev, "failed to create USB PHY\n");
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return (ENXIO);
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}
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if (phynode_register(phynode) == NULL) {
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device_printf(dev, "failed to create USB PHY\n");
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return (ENXIO);
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}
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return (error);
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}
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static device_method_t awusb3phy_methods[] = {
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/* Device interface */
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DEVMETHOD(device_probe, awusb3phy_probe),
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DEVMETHOD(device_attach, awusb3phy_attach),
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DEVMETHOD_END
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};
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static driver_t awusb3phy_driver = {
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"awusb3phy",
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awusb3phy_methods,
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sizeof(struct awusb3phy_softc)
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};
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/* aw_usb3phy needs to come up after regulators/gpio/etc, but before ehci/ohci */
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EARLY_DRIVER_MODULE(awusb3phy, simplebus, awusb3phy_driver, 0, 0,
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BUS_PASS_SUPPORTDEV + BUS_PASS_ORDER_MIDDLE);
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MODULE_VERSION(awusb3phy, 1);
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