232 lines
6.1 KiB
C
232 lines
6.1 KiB
C
/*-
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* Copyright (c) 2014-2017 Ruslan Bukin <br@bsdpad.com>
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* All rights reserved.
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*
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* This software was developed by SRI International and the University of
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* Cambridge Computer Laboratory under DARPA/AFRL contract (FA8750-10-C-0237)
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* ("CTSRD"), as part of the DARPA CRASH research programme.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include "opt_platform.h"
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/smp.h>
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#include <vm/vm.h>
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#include <vm/pmap.h>
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#include <machine/cpu.h>
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#include <machine/smp.h>
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#include <machine/fdt.h>
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#include <machine/intr.h>
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#include <machine/platformvar.h>
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#include <arm/altera/socfpga/socfpga_mp.h>
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#include <arm/altera/socfpga/socfpga_rstmgr.h>
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#define SCU_PHYSBASE 0xFFFEC000
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#define SCU_PHYSBASE_A10 0xFFFFC000
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#define SCU_SIZE 0x100
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#define SCU_CONTROL_REG 0x00
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#define SCU_CONTROL_ENABLE (1 << 0)
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#define SCU_CONFIG_REG 0x04
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#define SCU_CONFIG_REG_NCPU_MASK 0x03
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#define SCU_CPUPOWER_REG 0x08
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#define SCU_INV_TAGS_REG 0x0c
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#define SCU_DIAG_CONTROL 0x30
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#define SCU_DIAG_DISABLE_MIGBIT (1 << 0)
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#define SCU_FILTER_START_REG 0x40
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#define SCU_FILTER_END_REG 0x44
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#define SCU_SECURE_ACCESS_REG 0x50
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#define SCU_NONSECURE_ACCESS_REG 0x54
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#define RSTMGR_PHYSBASE 0xFFD05000
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#define RSTMGR_SIZE 0x100
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#define RAM_PHYSBASE 0x0
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#define RAM_SIZE 0x1000
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#define SOCFPGA_ARRIA10 1
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#define SOCFPGA_CYCLONE5 2
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extern char *mpentry_addr;
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static void socfpga_trampoline(void);
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static void
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socfpga_trampoline(void)
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{
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__asm __volatile(
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"ldr pc, 1f\n"
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".globl mpentry_addr\n"
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"mpentry_addr:\n"
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"1: .space 4\n");
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}
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void
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socfpga_mp_setmaxid(platform_t plat)
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{
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int hwcpu, ncpu;
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/* If we've already set this don't bother to do it again. */
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if (mp_ncpus != 0)
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return;
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hwcpu = 2;
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ncpu = hwcpu;
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TUNABLE_INT_FETCH("hw.ncpu", &ncpu);
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if (ncpu < 1 || ncpu > hwcpu)
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ncpu = hwcpu;
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mp_ncpus = ncpu;
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mp_maxid = ncpu - 1;
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}
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static void
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_socfpga_mp_start_ap(uint32_t platid)
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{
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bus_space_handle_t scu, rst, ram;
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int reg;
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switch (platid) {
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#if defined(SOC_ALTERA_ARRIA10)
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case SOCFPGA_ARRIA10:
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE_A10,
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SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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break;
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#endif
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#if defined(SOC_ALTERA_CYCLONE5)
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case SOCFPGA_CYCLONE5:
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if (bus_space_map(fdtbus_bs_tag, SCU_PHYSBASE,
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SCU_SIZE, 0, &scu) != 0)
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panic("Couldn't map the SCU\n");
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break;
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#endif
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default:
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panic("Unknown platform id %d\n", platid);
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}
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if (bus_space_map(fdtbus_bs_tag, RSTMGR_PHYSBASE,
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RSTMGR_SIZE, 0, &rst) != 0)
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panic("Couldn't map the reset manager (RSTMGR)\n");
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if (bus_space_map(fdtbus_bs_tag, RAM_PHYSBASE,
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RAM_SIZE, 0, &ram) != 0)
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panic("Couldn't map the first physram page\n");
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/* Invalidate SCU cache tags */
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bus_space_write_4(fdtbus_bs_tag, scu,
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SCU_INV_TAGS_REG, 0x0000ffff);
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/*
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* Erratum ARM/MP: 764369 (problems with cache maintenance).
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* Setting the "disable-migratory bit" in the undocumented SCU
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* Diagnostic Control Register helps work around the problem.
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*/
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reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL);
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reg |= (SCU_DIAG_DISABLE_MIGBIT);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_DIAG_CONTROL, reg);
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/* Put CPU1 to reset state */
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switch (platid) {
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#if defined(SOC_ALTERA_ARRIA10)
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case SOCFPGA_ARRIA10:
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_A10_MPUMODRST, MPUMODRST_CPU1);
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break;
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#endif
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#if defined(SOC_ALTERA_CYCLONE5)
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case SOCFPGA_CYCLONE5:
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_MPUMODRST, MPUMODRST_CPU1);
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break;
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#endif
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default:
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panic("Unknown platform id %d\n", platid);
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}
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/* Enable the SCU, then clean the cache on this core */
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reg = bus_space_read_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG);
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reg |= (SCU_CONTROL_ENABLE);
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bus_space_write_4(fdtbus_bs_tag, scu, SCU_CONTROL_REG, reg);
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/* Set up trampoline code */
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mpentry_addr = (char *)pmap_kextract((vm_offset_t)mpentry);
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bus_space_write_region_4(fdtbus_bs_tag, ram, 0,
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(uint32_t *)&socfpga_trampoline, 8);
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dcache_wbinv_poc_all();
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/* Put CPU1 out from reset */
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switch (platid) {
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#if defined(SOC_ALTERA_ARRIA10)
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case SOCFPGA_ARRIA10:
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_A10_MPUMODRST, 0);
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break;
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#endif
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#if defined(SOC_ALTERA_CYCLONE5)
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case SOCFPGA_CYCLONE5:
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bus_space_write_4(fdtbus_bs_tag, rst,
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RSTMGR_MPUMODRST, 0);
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break;
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#endif
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default:
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panic("Unknown platform id %d\n", platid);
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}
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dsb();
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sev();
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bus_space_unmap(fdtbus_bs_tag, scu, SCU_SIZE);
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bus_space_unmap(fdtbus_bs_tag, rst, RSTMGR_SIZE);
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bus_space_unmap(fdtbus_bs_tag, ram, RAM_SIZE);
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}
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#if defined(SOC_ALTERA_ARRIA10)
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void
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socfpga_a10_mp_start_ap(platform_t plat)
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{
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_socfpga_mp_start_ap(SOCFPGA_ARRIA10);
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}
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#endif
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#if defined(SOC_ALTERA_CYCLONE5)
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void
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socfpga_mp_start_ap(platform_t plat)
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{
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_socfpga_mp_start_ap(SOCFPGA_CYCLONE5);
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}
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#endif
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