867 lines
24 KiB
C
867 lines
24 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <sys/taskqueue.h>
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#include <machine/bus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/mmc/bridge.h>
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#include <dev/mmc/mmcreg.h>
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#include <dev/mmc/mmc_fdt_helpers.h>
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#include <dev/sdhci/sdhci.h>
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#include "mmcbr_if.h"
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#include "sdhci_if.h"
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#include "opt_mmccam.h"
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#include "bcm2835_dma.h"
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#include <arm/broadcom/bcm2835/bcm2835_mbox_prop.h>
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#ifdef NOTYET
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#include <arm/broadcom/bcm2835/bcm2835_clkman.h>
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#endif
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#include <arm/broadcom/bcm2835/bcm2835_vcbus.h>
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#define BCM2835_DEFAULT_SDHCI_FREQ 50
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#define BCM2838_DEFAULT_SDHCI_FREQ 100
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#define BCM_SDHCI_BUFFER_SIZE 512
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/*
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* NUM_DMA_SEGS is the number of DMA segments we want to accommodate on average.
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* We add in a number of segments based on how much we may need to spill into
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* another segment due to crossing page boundaries. e.g. up to PAGE_SIZE, an
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* extra page is needed as we can cross a page boundary exactly once.
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*/
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#define NUM_DMA_SEGS 1
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#define NUM_DMA_SPILL_SEGS \
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((((NUM_DMA_SEGS * BCM_SDHCI_BUFFER_SIZE) - 1) / PAGE_SIZE) + 1)
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#define ALLOCATED_DMA_SEGS (NUM_DMA_SEGS + NUM_DMA_SPILL_SEGS)
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#define BCM_DMA_MAXSIZE (NUM_DMA_SEGS * BCM_SDHCI_BUFFER_SIZE)
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#define BCM_SDHCI_SLOT_LEFT(slot) \
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((slot)->curcmd->data->len - (slot)->offset)
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#define BCM_SDHCI_SEGSZ_LEFT(slot) \
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min(BCM_DMA_MAXSIZE, \
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rounddown(BCM_SDHCI_SLOT_LEFT(slot), BCM_SDHCI_BUFFER_SIZE))
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#define DATA_PENDING_MASK (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)
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#define DATA_XFER_MASK (DATA_PENDING_MASK | SDHCI_INT_DATA_END)
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#ifdef DEBUG
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static int bcm2835_sdhci_debug = 0;
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TUNABLE_INT("hw.bcm2835.sdhci.debug", &bcm2835_sdhci_debug);
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SYSCTL_INT(_hw_sdhci, OID_AUTO, bcm2835_sdhci_debug, CTLFLAG_RWTUN,
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&bcm2835_sdhci_debug, 0, "bcm2835 SDHCI debug level");
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#define dprintf(fmt, args...) \
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do { \
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if (bcm2835_sdhci_debug) \
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printf("%s: " fmt, __func__, ##args); \
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} while (0)
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#else
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#define dprintf(fmt, args...)
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#endif
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static int bcm2835_sdhci_hs = 1;
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static int bcm2835_sdhci_pio_mode = 0;
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struct bcm_mmc_conf {
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int clock_id;
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int clock_src;
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int default_freq;
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int quirks;
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int emmc_dreq;
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};
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struct bcm_mmc_conf bcm2835_sdhci_conf = {
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.clock_id = BCM2835_MBOX_CLOCK_ID_EMMC,
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.clock_src = -1,
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.default_freq = BCM2835_DEFAULT_SDHCI_FREQ,
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.quirks = SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK |
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SDHCI_QUIRK_BROKEN_TIMEOUT_VAL | SDHCI_QUIRK_DONT_SET_HISPD_BIT |
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SDHCI_QUIRK_MISSING_CAPS,
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.emmc_dreq = BCM_DMA_DREQ_EMMC,
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};
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struct bcm_mmc_conf bcm2838_emmc2_conf = {
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.clock_id = BCM2838_MBOX_CLOCK_ID_EMMC2,
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.clock_src = -1,
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.default_freq = BCM2838_DEFAULT_SDHCI_FREQ,
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.quirks = 0,
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.emmc_dreq = BCM_DMA_DREQ_NONE,
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};
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static struct ofw_compat_data compat_data[] = {
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{"broadcom,bcm2835-sdhci", (uintptr_t)&bcm2835_sdhci_conf},
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{"brcm,bcm2835-sdhci", (uintptr_t)&bcm2835_sdhci_conf},
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{"brcm,bcm2835-mmc", (uintptr_t)&bcm2835_sdhci_conf},
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{"brcm,bcm2711-emmc2", (uintptr_t)&bcm2838_emmc2_conf},
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{"brcm,bcm2838-emmc2", (uintptr_t)&bcm2838_emmc2_conf},
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{NULL, 0}
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};
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TUNABLE_INT("hw.bcm2835.sdhci.hs", &bcm2835_sdhci_hs);
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TUNABLE_INT("hw.bcm2835.sdhci.pio_mode", &bcm2835_sdhci_pio_mode);
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struct bcm_sdhci_softc {
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device_t sc_dev;
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struct resource * sc_mem_res;
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struct resource * sc_irq_res;
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bus_space_tag_t sc_bst;
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bus_space_handle_t sc_bsh;
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void * sc_intrhand;
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struct mmc_request * sc_req;
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struct sdhci_slot sc_slot;
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struct mmc_helper sc_mmc_helper;
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int sc_dma_ch;
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bus_dma_tag_t sc_dma_tag;
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bus_dmamap_t sc_dma_map;
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vm_paddr_t sc_sdhci_buffer_phys;
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bus_addr_t dmamap_seg_addrs[ALLOCATED_DMA_SEGS];
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bus_size_t dmamap_seg_sizes[ALLOCATED_DMA_SEGS];
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int dmamap_seg_count;
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int dmamap_seg_index;
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int dmamap_status;
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uint32_t blksz_and_count;
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uint32_t cmd_and_mode;
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bool need_update_blk;
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#ifdef NOTYET
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device_t clkman;
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#endif
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struct bcm_mmc_conf * conf;
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};
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static int bcm_sdhci_probe(device_t);
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static int bcm_sdhci_attach(device_t);
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static int bcm_sdhci_detach(device_t);
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static void bcm_sdhci_intr(void *);
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static int bcm_sdhci_get_ro(device_t, device_t);
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static void bcm_sdhci_dma_intr(int ch, void *arg);
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static void bcm_sdhci_start_dma(struct sdhci_slot *slot);
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static void
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bcm_sdhci_dmacb(void *arg, bus_dma_segment_t *segs, int nseg, int err)
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{
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struct bcm_sdhci_softc *sc = arg;
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int i;
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/* Sanity check: we can only ever have one mapping at a time. */
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KASSERT(sc->dmamap_seg_count == 0, ("leaked DMA segment"));
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sc->dmamap_status = err;
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sc->dmamap_seg_count = nseg;
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/* Note nseg is guaranteed to be zero if err is non-zero. */
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for (i = 0; i < nseg; i++) {
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sc->dmamap_seg_addrs[i] = segs[i].ds_addr;
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sc->dmamap_seg_sizes[i] = segs[i].ds_len;
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}
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}
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static int
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bcm_sdhci_probe(device_t dev)
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{
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
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return (ENXIO);
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device_set_desc(dev, "Broadcom 2708 SDHCI controller");
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return (BUS_PROBE_DEFAULT);
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}
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static int
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bcm_sdhci_attach(device_t dev)
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{
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struct bcm_sdhci_softc *sc = device_get_softc(dev);
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int rid, err;
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phandle_t node;
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pcell_t cell;
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u_int default_freq;
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sc->sc_dev = dev;
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sc->sc_req = NULL;
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sc->conf = (struct bcm_mmc_conf *)ofw_bus_search_compatible(dev,
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compat_data)->ocd_data;
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if (sc->conf == 0)
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return (ENXIO);
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err = bcm2835_mbox_set_power_state(BCM2835_MBOX_POWER_ID_EMMC, TRUE);
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if (err != 0) {
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if (bootverbose)
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device_printf(dev, "Unable to enable the power\n");
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return (err);
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}
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default_freq = 0;
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err = bcm2835_mbox_get_clock_rate(sc->conf->clock_id, &default_freq);
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if (err == 0) {
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/* Convert to MHz */
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default_freq /= 1000000;
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}
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if (default_freq == 0) {
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node = ofw_bus_get_node(sc->sc_dev);
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if ((OF_getencprop(node, "clock-frequency", &cell,
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sizeof(cell))) > 0)
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default_freq = cell / 1000000;
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}
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if (default_freq == 0)
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default_freq = sc->conf->default_freq;
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if (bootverbose)
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device_printf(dev, "SDHCI frequency: %dMHz\n", default_freq);
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#ifdef NOTYET
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if (sc->conf->clock_src > 0) {
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uint32_t f;
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sc->clkman = devclass_get_device(
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devclass_find("bcm2835_clkman"), 0);
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if (sc->clkman == NULL) {
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device_printf(dev, "cannot find Clock Manager\n");
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return (ENXIO);
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}
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f = bcm2835_clkman_set_frequency(sc->clkman,
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sc->conf->clock_src, default_freq);
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if (f == 0)
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return (EINVAL);
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if (bootverbose)
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device_printf(dev, "Clock source frequency: %dMHz\n",
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f);
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}
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#endif
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rid = 0;
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sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
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RF_ACTIVE);
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if (!sc->sc_mem_res) {
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device_printf(dev, "cannot allocate memory window\n");
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err = ENXIO;
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goto fail;
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}
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sc->sc_bst = rman_get_bustag(sc->sc_mem_res);
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sc->sc_bsh = rman_get_bushandle(sc->sc_mem_res);
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rid = 0;
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sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
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RF_ACTIVE | RF_SHAREABLE);
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if (!sc->sc_irq_res) {
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device_printf(dev, "cannot allocate interrupt\n");
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err = ENXIO;
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goto fail;
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}
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if (bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_BIO | INTR_MPSAFE,
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NULL, bcm_sdhci_intr, sc, &sc->sc_intrhand)) {
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device_printf(dev, "cannot setup interrupt handler\n");
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err = ENXIO;
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goto fail;
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}
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if (!bcm2835_sdhci_pio_mode)
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sc->sc_slot.opt = SDHCI_PLATFORM_TRANSFER;
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sc->sc_slot.caps = SDHCI_CAN_VDD_330 | SDHCI_CAN_VDD_180;
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if (bcm2835_sdhci_hs)
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sc->sc_slot.caps |= SDHCI_CAN_DO_HISPD;
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sc->sc_slot.caps |= (default_freq << SDHCI_CLOCK_BASE_SHIFT);
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sc->sc_slot.quirks = sc->conf->quirks;
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sdhci_init_slot(dev, &sc->sc_slot, 0);
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mmc_fdt_parse(dev, 0, &sc->sc_mmc_helper, &sc->sc_slot.host);
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sc->sc_dma_ch = bcm_dma_allocate(BCM_DMA_CH_ANY);
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if (sc->sc_dma_ch == BCM_DMA_CH_INVALID)
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goto fail;
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err = bcm_dma_setup_intr(sc->sc_dma_ch, bcm_sdhci_dma_intr, sc);
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if (err != 0) {
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device_printf(dev,
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"cannot setup dma interrupt handler\n");
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err = ENXIO;
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goto fail;
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}
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/* Allocate bus_dma resources. */
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err = bus_dma_tag_create(bus_get_dma_tag(dev),
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1, 0, bcm283x_dmabus_peripheral_lowaddr(),
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BUS_SPACE_MAXADDR, NULL, NULL,
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BCM_DMA_MAXSIZE, ALLOCATED_DMA_SEGS, BCM_SDHCI_BUFFER_SIZE,
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BUS_DMA_ALLOCNOW, NULL, NULL,
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&sc->sc_dma_tag);
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if (err) {
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device_printf(dev, "failed allocate DMA tag");
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goto fail;
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}
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err = bus_dmamap_create(sc->sc_dma_tag, 0, &sc->sc_dma_map);
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if (err) {
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device_printf(dev, "bus_dmamap_create failed\n");
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goto fail;
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}
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/* FIXME: Fix along with other BUS_SPACE_PHYSADDR instances */
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sc->sc_sdhci_buffer_phys = rman_get_start(sc->sc_mem_res) +
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SDHCI_BUFFER;
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bus_generic_probe(dev);
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bus_generic_attach(dev);
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sdhci_start_slot(&sc->sc_slot);
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/* Seed our copies. */
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sc->blksz_and_count = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_BLOCK_SIZE);
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sc->cmd_and_mode = SDHCI_READ_4(dev, &sc->sc_slot, SDHCI_TRANSFER_MODE);
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return (0);
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fail:
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if (sc->sc_intrhand)
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bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_intrhand);
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if (sc->sc_irq_res)
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bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
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if (sc->sc_mem_res)
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bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
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return (err);
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}
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static int
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bcm_sdhci_detach(device_t dev)
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{
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return (EBUSY);
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}
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static void
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bcm_sdhci_intr(void *arg)
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{
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struct bcm_sdhci_softc *sc = arg;
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sdhci_generic_intr(&sc->sc_slot);
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}
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|
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static int
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bcm_sdhci_update_ios(device_t bus, device_t child)
|
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{
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struct bcm_sdhci_softc *sc;
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struct mmc_ios *ios;
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int rv;
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|
|
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sc = device_get_softc(bus);
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ios = &sc->sc_slot.host.ios;
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|
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if (ios->power_mode == power_up) {
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if (sc->sc_mmc_helper.vmmc_supply)
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regulator_enable(sc->sc_mmc_helper.vmmc_supply);
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if (sc->sc_mmc_helper.vqmmc_supply)
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regulator_enable(sc->sc_mmc_helper.vqmmc_supply);
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}
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|
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rv = sdhci_generic_update_ios(bus, child);
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if (rv != 0)
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return (rv);
|
|
|
|
if (ios->power_mode == power_off) {
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if (sc->sc_mmc_helper.vmmc_supply)
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regulator_disable(sc->sc_mmc_helper.vmmc_supply);
|
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if (sc->sc_mmc_helper.vqmmc_supply)
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regulator_disable(sc->sc_mmc_helper.vqmmc_supply);
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}
|
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|
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return (0);
|
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}
|
|
|
|
static int
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bcm_sdhci_get_ro(device_t bus, device_t child)
|
|
{
|
|
|
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return (0);
|
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}
|
|
|
|
static inline uint32_t
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RD4(struct bcm_sdhci_softc *sc, bus_size_t off)
|
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{
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uint32_t val = bus_space_read_4(sc->sc_bst, sc->sc_bsh, off);
|
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return val;
|
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}
|
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|
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static inline void
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WR4(struct bcm_sdhci_softc *sc, bus_size_t off, uint32_t val)
|
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{
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|
|
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bus_space_write_4(sc->sc_bst, sc->sc_bsh, off, val);
|
|
/*
|
|
* The Arasan HC has a bug where it may lose the content of
|
|
* consecutive writes to registers that are within two SD-card
|
|
* clock cycles of each other (a clock domain crossing problem).
|
|
*/
|
|
if (sc->sc_slot.clock > 0)
|
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DELAY(((2 * 1000000) / sc->sc_slot.clock) + 1);
|
|
}
|
|
|
|
static uint8_t
|
|
bcm_sdhci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
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uint32_t val = RD4(sc, off & ~3);
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|
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return ((val >> (off & 3)*8) & 0xff);
|
|
}
|
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|
|
static uint16_t
|
|
bcm_sdhci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
uint32_t val32;
|
|
|
|
/*
|
|
* Standard 32-bit handling of command and transfer mode, as
|
|
* well as block size and count.
|
|
*/
|
|
if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) &&
|
|
sc->need_update_blk)
|
|
val32 = sc->blksz_and_count;
|
|
else if (off == SDHCI_TRANSFER_MODE || off == SDHCI_COMMAND_FLAGS)
|
|
val32 = sc->cmd_and_mode;
|
|
else
|
|
val32 = RD4(sc, off & ~3);
|
|
|
|
return ((val32 >> (off & 3)*8) & 0xffff);
|
|
}
|
|
|
|
static uint32_t
|
|
bcm_sdhci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
return RD4(sc, off);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_read_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
uint32_t *data, bus_size_t count)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
bus_space_read_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
uint8_t val)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
uint32_t val32 = RD4(sc, off & ~3);
|
|
val32 &= ~(0xff << (off & 3)*8);
|
|
val32 |= (val << (off & 3)*8);
|
|
WR4(sc, off & ~3, val32);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
uint16_t val)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
uint32_t val32;
|
|
|
|
/*
|
|
* If we have a queued up 16bit value for blk size or count, use and
|
|
* update the saved value rather than doing any real register access.
|
|
* If we did not touch either since the last write, then read from
|
|
* register as at least block count can change.
|
|
* Similarly, if we are about to issue a command, always use the saved
|
|
* value for transfer mode as we can never write that without issuing
|
|
* a command.
|
|
*/
|
|
if ((off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) &&
|
|
sc->need_update_blk)
|
|
val32 = sc->blksz_and_count;
|
|
else if (off == SDHCI_COMMAND_FLAGS)
|
|
val32 = sc->cmd_and_mode;
|
|
else
|
|
val32 = RD4(sc, off & ~3);
|
|
|
|
val32 &= ~(0xffff << (off & 3)*8);
|
|
val32 |= (val << (off & 3)*8);
|
|
|
|
if (off == SDHCI_TRANSFER_MODE)
|
|
sc->cmd_and_mode = val32;
|
|
else if (off == SDHCI_BLOCK_SIZE || off == SDHCI_BLOCK_COUNT) {
|
|
sc->blksz_and_count = val32;
|
|
sc->need_update_blk = true;
|
|
} else {
|
|
if (off == SDHCI_COMMAND_FLAGS) {
|
|
/* If we saved blk writes, do them now before cmd. */
|
|
if (sc->need_update_blk) {
|
|
WR4(sc, SDHCI_BLOCK_SIZE, sc->blksz_and_count);
|
|
sc->need_update_blk = false;
|
|
}
|
|
/* Always save cmd and mode registers. */
|
|
sc->cmd_and_mode = val32;
|
|
}
|
|
WR4(sc, off & ~3, val32);
|
|
}
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
uint32_t val)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
WR4(sc, off, val);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_write_multi_4(device_t dev, struct sdhci_slot *slot, bus_size_t off,
|
|
uint32_t *data, bus_size_t count)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(dev);
|
|
|
|
bus_space_write_multi_4(sc->sc_bst, sc->sc_bsh, off, data, count);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_start_dma_seg(struct bcm_sdhci_softc *sc)
|
|
{
|
|
struct sdhci_slot *slot;
|
|
vm_paddr_t pdst, psrc;
|
|
int err __diagused, idx, len, sync_op, width;
|
|
|
|
slot = &sc->sc_slot;
|
|
mtx_assert(&slot->mtx, MA_OWNED);
|
|
idx = sc->dmamap_seg_index++;
|
|
len = sc->dmamap_seg_sizes[idx];
|
|
slot->offset += len;
|
|
width = (len & 0xf ? BCM_DMA_32BIT : BCM_DMA_128BIT);
|
|
|
|
if (slot->curcmd->data->flags & MMC_DATA_READ) {
|
|
/*
|
|
* Peripherals on the AXI bus do not need DREQ pacing for reads
|
|
* from the ARM core, so we can safely set this to NONE.
|
|
*/
|
|
bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
|
|
BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
|
|
bcm_dma_setup_dst(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
|
|
BCM_DMA_INC_ADDR, width);
|
|
psrc = sc->sc_sdhci_buffer_phys;
|
|
pdst = sc->dmamap_seg_addrs[idx];
|
|
sync_op = BUS_DMASYNC_PREREAD;
|
|
} else {
|
|
/*
|
|
* The ordering here is important, because the last write to
|
|
* dst/src in the dma control block writes the real dreq value.
|
|
*/
|
|
bcm_dma_setup_src(sc->sc_dma_ch, BCM_DMA_DREQ_NONE,
|
|
BCM_DMA_INC_ADDR, width);
|
|
bcm_dma_setup_dst(sc->sc_dma_ch, sc->conf->emmc_dreq,
|
|
BCM_DMA_SAME_ADDR, BCM_DMA_32BIT);
|
|
psrc = sc->dmamap_seg_addrs[idx];
|
|
pdst = sc->sc_sdhci_buffer_phys;
|
|
sync_op = BUS_DMASYNC_PREWRITE;
|
|
}
|
|
|
|
/*
|
|
* When starting a new DMA operation do the busdma sync operation, and
|
|
* disable SDCHI data interrrupts because we'll be driven by DMA
|
|
* interrupts (or SDHCI error interrupts) until the IO is done.
|
|
*/
|
|
if (idx == 0) {
|
|
bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map, sync_op);
|
|
|
|
slot->intmask &= ~DATA_XFER_MASK;
|
|
bcm_sdhci_write_4(sc->sc_dev, slot, SDHCI_SIGNAL_ENABLE,
|
|
slot->intmask);
|
|
}
|
|
|
|
/*
|
|
* Start the DMA transfer. Only programming errors (like failing to
|
|
* allocate a channel) cause a non-zero return from bcm_dma_start().
|
|
*/
|
|
err = bcm_dma_start(sc->sc_dma_ch, psrc, pdst, len);
|
|
KASSERT((err == 0), ("bcm2835_sdhci: failed DMA start"));
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_dma_exit(struct bcm_sdhci_softc *sc)
|
|
{
|
|
struct sdhci_slot *slot = &sc->sc_slot;
|
|
|
|
mtx_assert(&slot->mtx, MA_OWNED);
|
|
|
|
/* Re-enable interrupts */
|
|
slot->intmask |= DATA_XFER_MASK;
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_SIGNAL_ENABLE,
|
|
slot->intmask);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_dma_unload(struct bcm_sdhci_softc *sc)
|
|
{
|
|
struct sdhci_slot *slot = &sc->sc_slot;
|
|
|
|
if (sc->dmamap_seg_count == 0)
|
|
return;
|
|
if ((slot->curcmd->data->flags & MMC_DATA_READ) != 0)
|
|
bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
|
|
BUS_DMASYNC_POSTREAD);
|
|
else
|
|
bus_dmamap_sync(sc->sc_dma_tag, sc->sc_dma_map,
|
|
BUS_DMASYNC_POSTWRITE);
|
|
bus_dmamap_unload(sc->sc_dma_tag, sc->sc_dma_map);
|
|
|
|
sc->dmamap_seg_count = 0;
|
|
sc->dmamap_seg_index = 0;
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_dma_intr(int ch, void *arg)
|
|
{
|
|
struct bcm_sdhci_softc *sc = (struct bcm_sdhci_softc *)arg;
|
|
struct sdhci_slot *slot = &sc->sc_slot;
|
|
uint32_t reg;
|
|
|
|
mtx_lock(&slot->mtx);
|
|
if (slot->curcmd == NULL)
|
|
goto out;
|
|
/*
|
|
* If there are more segments for the current dma, start the next one.
|
|
* Otherwise unload the dma map and decide what to do next based on the
|
|
* status of the sdhci controller and whether there's more data left.
|
|
*/
|
|
if (sc->dmamap_seg_index < sc->dmamap_seg_count) {
|
|
bcm_sdhci_start_dma_seg(sc);
|
|
goto out;
|
|
}
|
|
|
|
bcm_sdhci_dma_unload(sc);
|
|
|
|
/*
|
|
* If we had no further segments pending, we need to determine how to
|
|
* proceed next. If the 'data/space pending' bit is already set and we
|
|
* can continue via DMA, do so. Otherwise, re-enable interrupts and
|
|
* return.
|
|
*/
|
|
reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS) &
|
|
DATA_XFER_MASK;
|
|
if ((reg & DATA_PENDING_MASK) != 0 &&
|
|
BCM_SDHCI_SEGSZ_LEFT(slot) >= BCM_SDHCI_BUFFER_SIZE) {
|
|
/* ACK any pending interrupts */
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS,
|
|
DATA_PENDING_MASK);
|
|
|
|
bcm_sdhci_start_dma(slot);
|
|
if (slot->curcmd->error != 0) {
|
|
/* We won't recover from this error for this command. */
|
|
bcm_sdhci_dma_unload(sc);
|
|
bcm_sdhci_dma_exit(sc);
|
|
sdhci_finish_data(slot);
|
|
}
|
|
} else if ((reg & SDHCI_INT_DATA_END) != 0) {
|
|
bcm_sdhci_dma_exit(sc);
|
|
bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS,
|
|
reg);
|
|
slot->flags &= ~PLATFORM_DATA_STARTED;
|
|
sdhci_finish_data(slot);
|
|
} else {
|
|
bcm_sdhci_dma_exit(sc);
|
|
}
|
|
out:
|
|
mtx_unlock(&slot->mtx);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_start_dma(struct sdhci_slot *slot)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
|
|
uint8_t *buf;
|
|
size_t left;
|
|
|
|
mtx_assert(&slot->mtx, MA_OWNED);
|
|
|
|
left = BCM_SDHCI_SEGSZ_LEFT(slot);
|
|
buf = (uint8_t *)slot->curcmd->data->data + slot->offset;
|
|
KASSERT(left != 0,
|
|
("%s: DMA handling incorrectly indicated", __func__));
|
|
|
|
/*
|
|
* No need to check segment count here; if we've not yet unloaded
|
|
* previous segments, we'll catch that in bcm_sdhci_dmacb.
|
|
*/
|
|
if (bus_dmamap_load(sc->sc_dma_tag, sc->sc_dma_map, buf, left,
|
|
bcm_sdhci_dmacb, sc, BUS_DMA_NOWAIT) != 0 ||
|
|
sc->dmamap_status != 0) {
|
|
slot->curcmd->error = MMC_ERR_NO_MEMORY;
|
|
return;
|
|
}
|
|
|
|
/* DMA start */
|
|
bcm_sdhci_start_dma_seg(sc);
|
|
}
|
|
|
|
static int
|
|
bcm_sdhci_will_handle_transfer(device_t dev, struct sdhci_slot *slot)
|
|
{
|
|
#ifdef INVARIANTS
|
|
struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
|
|
#endif
|
|
|
|
/*
|
|
* We don't want to perform DMA in this context -- interrupts are
|
|
* disabled, and a transaction may already be in progress.
|
|
*/
|
|
if (dumping)
|
|
return (0);
|
|
|
|
/*
|
|
* This indicates that we somehow let a data interrupt slip by into the
|
|
* SDHCI framework, when it should not have. This really needs to be
|
|
* caught and fixed ASAP, as it really shouldn't happen.
|
|
*/
|
|
KASSERT(sc->dmamap_seg_count == 0,
|
|
("data pending interrupt pushed through SDHCI framework"));
|
|
|
|
/*
|
|
* Do not use DMA for transfers less than our block size. Checking
|
|
* alignment serves little benefit, as we round transfer sizes down to
|
|
* a multiple of the block size and push the transfer back to
|
|
* SDHCI-driven PIO once we're below the block size.
|
|
*/
|
|
if (BCM_SDHCI_SEGSZ_LEFT(slot) < BCM_DMA_BLOCK_SIZE)
|
|
return (0);
|
|
|
|
return (1);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_start_transfer(device_t dev, struct sdhci_slot *slot,
|
|
uint32_t *intmask)
|
|
{
|
|
|
|
/* DMA transfer FIFO 1KB */
|
|
bcm_sdhci_start_dma(slot);
|
|
}
|
|
|
|
static void
|
|
bcm_sdhci_finish_transfer(device_t dev, struct sdhci_slot *slot)
|
|
{
|
|
struct bcm_sdhci_softc *sc = device_get_softc(slot->bus);
|
|
|
|
/*
|
|
* Clean up. Interrupts are clearly enabled, because we received an
|
|
* SDHCI_INT_DATA_END to get this far -- just make sure we don't leave
|
|
* anything laying around.
|
|
*/
|
|
if (sc->dmamap_seg_count != 0) {
|
|
/*
|
|
* Our segment math should have worked out such that we would
|
|
* never finish the transfer without having used up all of the
|
|
* segments. If we haven't, that means we must have erroneously
|
|
* regressed to SDHCI-driven PIO to finish the operation and
|
|
* this is certainly caused by developer-error.
|
|
*/
|
|
bcm_sdhci_dma_unload(sc);
|
|
}
|
|
|
|
sdhci_finish_data(slot);
|
|
}
|
|
|
|
static device_method_t bcm_sdhci_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, bcm_sdhci_probe),
|
|
DEVMETHOD(device_attach, bcm_sdhci_attach),
|
|
DEVMETHOD(device_detach, bcm_sdhci_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
|
|
DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
|
|
DEVMETHOD(bus_add_child, bus_generic_add_child),
|
|
|
|
/* MMC bridge interface */
|
|
DEVMETHOD(mmcbr_update_ios, bcm_sdhci_update_ios),
|
|
DEVMETHOD(mmcbr_request, sdhci_generic_request),
|
|
DEVMETHOD(mmcbr_get_ro, bcm_sdhci_get_ro),
|
|
DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
|
|
DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
|
|
|
|
/* Platform transfer methods */
|
|
DEVMETHOD(sdhci_platform_will_handle, bcm_sdhci_will_handle_transfer),
|
|
DEVMETHOD(sdhci_platform_start_transfer, bcm_sdhci_start_transfer),
|
|
DEVMETHOD(sdhci_platform_finish_transfer, bcm_sdhci_finish_transfer),
|
|
/* SDHCI registers accessors */
|
|
DEVMETHOD(sdhci_read_1, bcm_sdhci_read_1),
|
|
DEVMETHOD(sdhci_read_2, bcm_sdhci_read_2),
|
|
DEVMETHOD(sdhci_read_4, bcm_sdhci_read_4),
|
|
DEVMETHOD(sdhci_read_multi_4, bcm_sdhci_read_multi_4),
|
|
DEVMETHOD(sdhci_write_1, bcm_sdhci_write_1),
|
|
DEVMETHOD(sdhci_write_2, bcm_sdhci_write_2),
|
|
DEVMETHOD(sdhci_write_4, bcm_sdhci_write_4),
|
|
DEVMETHOD(sdhci_write_multi_4, bcm_sdhci_write_multi_4),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t bcm_sdhci_driver = {
|
|
"sdhci_bcm",
|
|
bcm_sdhci_methods,
|
|
sizeof(struct bcm_sdhci_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(sdhci_bcm, simplebus, bcm_sdhci_driver, NULL, NULL);
|
|
#ifdef NOTYET
|
|
MODULE_DEPEND(sdhci_bcm, bcm2835_clkman, 1, 1, 1);
|
|
#endif
|
|
SDHCI_DEPEND(sdhci_bcm);
|
|
#ifndef MMCCAM
|
|
MMC_DECLARE_BRIDGE(sdhci_bcm);
|
|
#endif
|