782 lines
23 KiB
C
782 lines
23 KiB
C
/*-
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* Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* AHCI driver for Tegra SoCs.
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*/
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#include <sys/param.h>
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#include <sys/module.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/endian.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/malloc.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <dev/ahci/ahci.h>
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#include <dev/extres/clk/clk.h>
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#include <dev/extres/hwreset/hwreset.h>
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#include <dev/extres/phy/phy.h>
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#include <dev/extres/regulator/regulator.h>
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#include <dev/fdt/fdt_pinctrl.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/nvidia/tegra_efuse.h>
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#include <arm/nvidia/tegra_pmc.h>
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#define SATA_CONFIGURATION 0x180
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#define SATA_CONFIGURATION_CLK_OVERRIDE (1U << 31)
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#define SATA_CONFIGURATION_EN_FPCI (1 << 0)
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#define SATA_FPCI_BAR5 0x94
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#define SATA_FPCI_BAR_START(x) (((x) & 0xFFFFFFF) << 4)
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#define SATA_FPCI_BAR_ACCESS_TYPE (1 << 0)
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#define SATA_INTR_MASK 0x188
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#define SATA_INTR_MASK_IP_INT_MASK (1 << 16)
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#define SCFG_OFFSET 0x1000
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#define T_SATA0_CFG_1 0x04
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#define T_SATA0_CFG_1_IO_SPACE (1 << 0)
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#define T_SATA0_CFG_1_MEMORY_SPACE (1 << 1)
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#define T_SATA0_CFG_1_BUS_MASTER (1 << 2)
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#define T_SATA0_CFG_1_SERR (1 << 8)
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#define T_SATA0_CFG_9 0x24
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#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13
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#define T_SATA0_CFG_35 0x94
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#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2)
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#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2)
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#define T_SATA0_AHCI_IDP1 0x98
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#define T_SATA0_AHCI_IDP1_DATA 0x400040
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#define T_SATA0_CFG_PHY_1 0x12c
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#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN (1 << 23)
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#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN (1 << 22)
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#define T_SATA0_NVOOB 0x114
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#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24)
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#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24)
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#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16)
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#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16)
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#define T_SATA0_CFG_PHY 0x120
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#define T_SATA0_CFG_PHY_MASK_SQUELCH (1 << 24)
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#define T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD (1 << 11)
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#define T_SATA0_CFG2NVOOB_2 0x134
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#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18)
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#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18)
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#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP (1 << 26)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14)
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#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13)
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#define T_SATA0_BKDOOR_CC 0x4a4
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#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16)
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#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16)
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#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8)
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#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8)
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#define T_SATA0_CFG_SATA 0x54c
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#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN (1 << 12)
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#define T_SATA0_CFG_MISC 0x550
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#define T_SATA0_INDEX 0x680
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#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff
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#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0
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#define T_SATA0_CHX_PHY_CTRL2 0x69c
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#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23
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#define T_SATA0_CHX_PHY_CTRL11 0x6d0
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#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16)
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#define T_SATA0_CHX_PHY_CTRL17 0x6e8
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#define T_SATA0_CHX_PHY_CTRL18 0x6ec
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#define T_SATA0_CHX_PHY_CTRL20 0x6f4
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#define T_SATA0_CHX_PHY_CTRL21 0x6f8
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#define FUSE_SATA_CALIB 0x124
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#define FUSE_SATA_CALIB_MASK 0x3
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#define SATA_AUX_MISC_CNTL 0x1108
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#define SATA_AUX_PAD_PLL_CTRL_0 0x1120
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#define SATA_AUX_PAD_PLL_CTRL_1 0x1124
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#define SATA_AUX_PAD_PLL_CTRL_2 0x1128
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#define SATA_AUX_PAD_PLL_CTRL_3 0x112c
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#define T_AHCI_HBA_CCC_PORTS 0x0018
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#define T_AHCI_HBA_CAP_BKDR 0x00A0
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#define T_AHCI_HBA_CAP_BKDR_S64A (1 << 31)
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#define T_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30)
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#define T_AHCI_HBA_CAP_BKDR_SSNTF (1 << 29)
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#define T_AHCI_HBA_CAP_BKDR_SMPS (1 << 28)
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#define T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP (1 << 27)
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#define T_AHCI_HBA_CAP_BKDR_SALP (1 << 26)
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#define T_AHCI_HBA_CAP_BKDR_SAL (1 << 25)
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#define T_AHCI_HBA_CAP_BKDR_SUPP_CLO (1 << 24)
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#define T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x) (((x) & 0xF) << 20)
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#define T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET (1 << 19)
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#define T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY (1 << 18)
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#define T_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17)
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#define T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING (1 << 16)
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#define T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK (1 << 15)
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#define T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14)
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#define T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13)
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#define T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x) (((x) & 0x1F) << 8)
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#define T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING (1 << 7)
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#define T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP (1 << 6)
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#define T_AHCI_HBA_CAP_BKDR_EXT_SATA (1 << 5)
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#define T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x) (((x) & 0xF) << 0)
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#define T_AHCI_PORT_BKDR 0x0170
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#define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24)
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#define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16)
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#define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE (1 << 15)
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#define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE (1 << 14)
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#define T_AHCI_PORT_BKDR_PXDEVSLP_DM(x) (((x) & 0xF) << 10)
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#define T_AHCI_PORT_BKDR_PORT_UNCONNECTED (1 << 9)
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#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH (1 << 8)
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#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 << 7)
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#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP (1 << 6)
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#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP (1 << 5)
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#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP (1 << 4)
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#define T_AHCI_PORT_BKDR_HOTPLUG_CAP (1 << 3)
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#define T_AHCI_PORT_BKDR_MECH_SWITCH (1 << 2)
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#define T_AHCI_PORT_BKDR_COLD_PRSN_DET (1 << 1)
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#define T_AHCI_PORT_BKDR_EXT_SATA_SUPP (1 << 0)
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/* AUX registers */
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#define SATA_AUX_MISC_CNTL_1 0x008
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#define SATA_AUX_MISC_CNTL_1_DEVSLP_OVERRIDE (1 << 17)
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#define SATA_AUX_MISC_CNTL_1_SDS_SUPPORT (1 << 13)
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#define SATA_AUX_MISC_CNTL_1_DESO_SUPPORT (1 << 15)
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#define AHCI_WR4(_sc, _r, _v) bus_write_4((_sc)->ctlr.r_mem, (_r), (_v))
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#define AHCI_RD4(_sc, _r) bus_read_4((_sc)->ctlr.r_mem, (_r))
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#define SATA_WR4(_sc, _r, _v) bus_write_4((_sc)->sata_mem, (_r), (_v))
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#define SATA_RD4(_sc, _r) bus_read_4((_sc)->sata_mem, (_r))
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struct sata_pad_calibration {
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uint32_t gen1_tx_amp;
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uint32_t gen1_tx_peak;
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uint32_t gen2_tx_amp;
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uint32_t gen2_tx_peak;
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};
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static const struct sata_pad_calibration tegra124_pad_calibration[] = {
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{0x18, 0x04, 0x18, 0x0a},
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{0x0e, 0x04, 0x14, 0x0a},
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{0x0e, 0x07, 0x1a, 0x0e},
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{0x14, 0x0e, 0x1a, 0x0e},
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};
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struct ahci_soc;
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struct tegra_ahci_sc {
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struct ahci_controller ctlr; /* Must be first */
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device_t dev;
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struct ahci_soc *soc;
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struct resource *sata_mem;
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struct resource *aux_mem;
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clk_t clk_sata;
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clk_t clk_sata_oob;
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clk_t clk_pll_e;
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clk_t clk_cml;
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hwreset_t hwreset_sata;
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hwreset_t hwreset_sata_oob;
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hwreset_t hwreset_sata_cold;
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regulator_t regulators[16]; /* Safe maximum */
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phy_t phy;
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};
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struct ahci_soc {
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char **regulator_names;
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int (*init)(struct tegra_ahci_sc *sc);
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};
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/* Tegra 124 config. */
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static char *tegra124_reg_names[] = {
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"hvdd-supply",
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"vddio-supply",
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"avdd-supply",
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"target-5v-supply",
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"target-12v-supply",
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NULL
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};
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static int tegra124_ahci_init(struct tegra_ahci_sc *sc);
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static struct ahci_soc tegra124_soc = {
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.regulator_names = tegra124_reg_names,
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.init = tegra124_ahci_init,
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};
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/* Tegra 210 config. */
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static char *tegra210_reg_names[] = {
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NULL
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};
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static struct ahci_soc tegra210_soc = {
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.regulator_names = tegra210_reg_names,
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};
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static struct ofw_compat_data compat_data[] = {
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{"nvidia,tegra124-ahci", (uintptr_t)&tegra124_soc},
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{"nvidia,tegra210-ahci", (uintptr_t)&tegra210_soc},
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{NULL, 0}
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};
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static int
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get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node)
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{
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int i, rv;
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/* Regulators. */
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for (i = 0; sc->soc->regulator_names[i] != NULL; i++) {
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if (i >= nitems(sc->regulators)) {
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device_printf(sc->dev,
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"Too many regulators present in DT.\n");
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return (EOVERFLOW);
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}
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rv = regulator_get_by_ofw_property(sc->dev, 0,
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sc->soc->regulator_names[i], sc->regulators + i);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot get '%s' regulator\n",
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sc->soc->regulator_names[i]);
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return (ENXIO);
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}
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}
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/* Resets. */
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata );
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata' reset\n");
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return (ENXIO);
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}
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob",
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&sc->hwreset_sata_oob);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata oob' reset\n");
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return (ENXIO);
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}
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rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold",
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&sc->hwreset_sata_cold);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata cold' reset\n");
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return (ENXIO);
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}
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/* Phy */
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rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy);
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if (rv != 0) {
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rv = phy_get_by_ofw_idx(sc->dev, 0, 0, &sc->phy);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata' phy\n");
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return (ENXIO);
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}
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}
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/* Clocks. */
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rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata' clock\n");
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return (ENXIO);
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}
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rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot get 'sata oob' clock\n");
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return (ENXIO);
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}
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/* These are optional */
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rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml);
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if (rv != 0)
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sc->clk_cml = NULL;
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rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e);
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if (rv != 0)
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sc->clk_pll_e = NULL;
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return (0);
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}
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static int
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enable_fdt_resources(struct tegra_ahci_sc *sc)
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{
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int i, rv;
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/* Enable regulators. */
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for (i = 0; i < nitems(sc->regulators); i++) {
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if (sc->regulators[i] == NULL)
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continue;
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rv = regulator_enable(sc->regulators[i]);
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if (rv != 0) {
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device_printf(sc->dev,
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"Cannot enable '%s' regulator\n",
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sc->soc->regulator_names[i]);
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return (rv);
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}
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}
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/* Stop clocks */
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clk_stop(sc->clk_sata);
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clk_stop(sc->clk_sata_oob);
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tegra_powergate_power_off(TEGRA_POWERGATE_SAX);
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rv = hwreset_assert(sc->hwreset_sata);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot assert 'sata' reset\n");
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return (rv);
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}
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rv = hwreset_assert(sc->hwreset_sata_oob);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot assert 'sata oob' reset\n");
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return (rv);
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}
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rv = hwreset_assert(sc->hwreset_sata_cold);
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if (rv != 0) {
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device_printf(sc->dev, "Cannot assert 'sata cold' reset\n");
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|
return (rv);
|
|
}
|
|
rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX,
|
|
sc->clk_sata, sc->hwreset_sata);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot enable 'SAX' powergate\n");
|
|
return (rv);
|
|
}
|
|
|
|
rv = clk_enable(sc->clk_sata_oob);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot enable 'sata oob' clock\n");
|
|
return (rv);
|
|
}
|
|
if (sc->clk_cml != NULL) {
|
|
rv = clk_enable(sc->clk_cml);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot enable 'cml' clock\n");
|
|
return (rv);
|
|
}
|
|
}
|
|
if (sc->clk_pll_e != NULL) {
|
|
rv = clk_enable(sc->clk_pll_e);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot enable 'pll e' clock\n");
|
|
return (rv);
|
|
}
|
|
}
|
|
|
|
rv = hwreset_deassert(sc->hwreset_sata_cold);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n");
|
|
return (rv);
|
|
}
|
|
rv = hwreset_deassert(sc->hwreset_sata_oob);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n");
|
|
return (rv);
|
|
}
|
|
|
|
rv = phy_enable(sc->phy);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Cannot enable SATA phy\n");
|
|
return (rv);
|
|
}
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra124_ahci_init(struct tegra_ahci_sc *sc)
|
|
{
|
|
uint32_t val;
|
|
const struct sata_pad_calibration *calib;
|
|
|
|
/* Pad calibration. */
|
|
val = tegra_fuse_read_4(FUSE_SATA_CALIB);
|
|
calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK);
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1);
|
|
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1);
|
|
val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK <<
|
|
T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT);
|
|
val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK <<
|
|
T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT);
|
|
val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT;
|
|
val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val);
|
|
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2);
|
|
val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK <<
|
|
T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT);
|
|
val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK <<
|
|
T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT);
|
|
val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT;
|
|
val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val);
|
|
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11,
|
|
T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ);
|
|
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2,
|
|
T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1);
|
|
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc)
|
|
{
|
|
uint32_t val;
|
|
int rv;
|
|
|
|
/* Enable SATA MMIO. */
|
|
val = SATA_RD4(sc, SATA_FPCI_BAR5);
|
|
val &= ~SATA_FPCI_BAR_START(~0);
|
|
val |= SATA_FPCI_BAR_START(0x10000);
|
|
val |= SATA_FPCI_BAR_ACCESS_TYPE;
|
|
SATA_WR4(sc, SATA_FPCI_BAR5, val);
|
|
|
|
/* Enable FPCI access */
|
|
val = SATA_RD4(sc, SATA_CONFIGURATION);
|
|
val |= SATA_CONFIGURATION_EN_FPCI;
|
|
SATA_WR4(sc, SATA_CONFIGURATION, val);
|
|
|
|
/* Recommended electrical settings for phy */
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17, 0x55010000);
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18, 0x55010000);
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20, 0x1);
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21, 0x1);
|
|
|
|
/* SQUELCH and Gen3 */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY);
|
|
val |= T_SATA0_CFG_PHY_MASK_SQUELCH;
|
|
val &= ~T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY, val);
|
|
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_NVOOB);
|
|
val &= ~T_SATA0_NVOOB_COMMA_CNT_MASK;
|
|
val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK;
|
|
val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK;
|
|
val |= T_SATA0_NVOOB_COMMA_CNT;
|
|
val |= T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH;
|
|
val |= T_SATA0_NVOOB_SQUELCH_FILTER_MODE;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_NVOOB, val);
|
|
|
|
/* Setup COMWAKE_IDLE_CNT */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2);
|
|
val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK;
|
|
val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2, val);
|
|
|
|
if (sc->soc->init != NULL) {
|
|
rv = sc->soc->init(sc);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev,
|
|
"SOC specific intialization failed: %d\n", rv);
|
|
return (rv);
|
|
}
|
|
}
|
|
|
|
/* Enable backdoor programming. */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
|
|
|
|
/* Set device class and interface */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC);
|
|
val &= ~T_SATA0_BKDOOR_CC_CLASS_CODE_MASK;
|
|
val &= ~T_SATA0_BKDOOR_CC_PROG_IF_MASK;
|
|
val |= T_SATA0_BKDOOR_CC_CLASS_CODE;
|
|
val |= T_SATA0_BKDOOR_CC_PROG_IF;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, val);
|
|
|
|
/* Enable LPM capabilities */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR);
|
|
val |= T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP;
|
|
val |= T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP;
|
|
val |= T_SATA0_AHCI_HBA_CAP_BKDR_SALP;
|
|
val |= T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR, val);
|
|
|
|
/* Disable backdoor programming. */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA);
|
|
val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val);
|
|
|
|
/* SATA Second Level Clock Gating */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_35);
|
|
val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK;
|
|
val |= T_SATA0_CFG_35_IDP_INDEX;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_35, val);
|
|
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_IDP1, 0x400040);
|
|
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1);
|
|
val |= T_SATA0_CFG_PHY_1_PADS_IDDQ_EN;
|
|
val |= T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1, val);
|
|
|
|
/*
|
|
* Indicate Sata only has the capability to enter DevSleep
|
|
* from slumber link.
|
|
*/
|
|
if (sc->aux_mem != NULL) {
|
|
val = bus_read_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1);
|
|
val |= SATA_AUX_MISC_CNTL_1_DESO_SUPPORT;
|
|
bus_write_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1, val);
|
|
}
|
|
|
|
/* Enable IPFS Clock Gating */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + SATA_CONFIGURATION);
|
|
val &= ~SATA_CONFIGURATION_CLK_OVERRIDE;
|
|
SATA_WR4(sc, SCFG_OFFSET + SATA_CONFIGURATION, val);
|
|
|
|
|
|
/* Enable IO & memory access, bus master mode */
|
|
val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1);
|
|
val |= T_SATA0_CFG_1_IO_SPACE;
|
|
val |= T_SATA0_CFG_1_MEMORY_SPACE;
|
|
val |= T_SATA0_CFG_1_BUS_MASTER;
|
|
val |= T_SATA0_CFG_1_SERR;
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val);
|
|
|
|
/* AHCI bar */
|
|
SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_9,
|
|
0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT);
|
|
|
|
/* Unmask interrupts. */
|
|
val = SATA_RD4(sc, SATA_INTR_MASK);
|
|
val |= SATA_INTR_MASK_IP_INT_MASK;
|
|
SATA_WR4(sc, SATA_INTR_MASK, val);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_ctlr_reset(device_t dev)
|
|
{
|
|
struct tegra_ahci_sc *sc;
|
|
int rv;
|
|
uint32_t reg;
|
|
|
|
sc = device_get_softc(dev);
|
|
rv = ahci_ctlr_reset(dev);
|
|
if (rv != 0)
|
|
return (0);
|
|
AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1);
|
|
|
|
/* Overwrite AHCI capabilites. */
|
|
reg = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR);
|
|
reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0);
|
|
reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0);
|
|
reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA;
|
|
reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING;
|
|
reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING;
|
|
reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM;
|
|
reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO;
|
|
reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP;
|
|
AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg);
|
|
|
|
/* Overwrite AHCI portcapabilites. */
|
|
reg = AHCI_RD4(sc, T_AHCI_PORT_BKDR);
|
|
reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET;
|
|
reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP;
|
|
reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP;
|
|
AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data)
|
|
return (ENXIO);
|
|
|
|
device_set_desc_copy(dev, "AHCI SATA controller");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_attach(device_t dev)
|
|
{
|
|
struct tegra_ahci_sc *sc;
|
|
struct ahci_controller *ctlr;
|
|
phandle_t node;
|
|
int rv, rid;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
ctlr = &sc->ctlr;
|
|
node = ofw_bus_get_node(dev);
|
|
sc->soc = (struct ahci_soc *)ofw_bus_search_compatible(dev,
|
|
compat_data)->ocd_data;
|
|
|
|
ctlr->r_rid = 0;
|
|
ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&ctlr->r_rid, RF_ACTIVE);
|
|
if (ctlr->r_mem == NULL)
|
|
return (ENXIO);
|
|
|
|
rid = 1;
|
|
sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&rid, RF_ACTIVE);
|
|
if (sc->sata_mem == NULL) {
|
|
rv = ENXIO;
|
|
goto fail;
|
|
}
|
|
|
|
/* Aux is optionall */
|
|
rid = 2;
|
|
sc->aux_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
|
|
&rid, RF_ACTIVE);
|
|
|
|
rv = get_fdt_resources(sc, node);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Failed to allocate FDT resource(s)\n");
|
|
goto fail;
|
|
}
|
|
|
|
rv = enable_fdt_resources(sc);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Failed to enable FDT resource(s)\n");
|
|
goto fail;
|
|
}
|
|
rv = tegra_ahci_ctrl_init(sc);
|
|
if (rv != 0) {
|
|
device_printf(sc->dev, "Failed to initialize controller)\n");
|
|
goto fail;
|
|
}
|
|
|
|
/* Setup controller defaults. */
|
|
ctlr->msi = 0;
|
|
ctlr->numirqs = 1;
|
|
ctlr->ccc = 0;
|
|
|
|
/* Reset controller. */
|
|
rv = tegra_ahci_ctlr_reset(dev);
|
|
if (rv != 0)
|
|
goto fail;
|
|
rv = ahci_attach(dev);
|
|
return (rv);
|
|
|
|
fail:
|
|
/* XXX FDT stuff */
|
|
if (sc->sata_mem != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem);
|
|
if (ctlr->r_mem != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid,
|
|
ctlr->r_mem);
|
|
return (rv);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_detach(device_t dev)
|
|
{
|
|
|
|
ahci_detach(dev);
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_suspend(device_t dev)
|
|
{
|
|
struct tegra_ahci_sc *sc = device_get_softc(dev);
|
|
|
|
bus_generic_suspend(dev);
|
|
/* Disable interupts, so the state change(s) doesn't trigger. */
|
|
ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC,
|
|
ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
tegra_ahci_resume(device_t dev)
|
|
{
|
|
int res;
|
|
|
|
if ((res = tegra_ahci_ctlr_reset(dev)) != 0)
|
|
return (res);
|
|
ahci_ctlr_setup(dev);
|
|
return (bus_generic_resume(dev));
|
|
}
|
|
|
|
static device_method_t tegra_ahci_methods[] = {
|
|
DEVMETHOD(device_probe, tegra_ahci_probe),
|
|
DEVMETHOD(device_attach, tegra_ahci_attach),
|
|
DEVMETHOD(device_detach, tegra_ahci_detach),
|
|
DEVMETHOD(device_suspend, tegra_ahci_suspend),
|
|
DEVMETHOD(device_resume, tegra_ahci_resume),
|
|
DEVMETHOD(bus_print_child, ahci_print_child),
|
|
DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, ahci_release_resource),
|
|
DEVMETHOD(bus_setup_intr, ahci_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, ahci_teardown_intr),
|
|
DEVMETHOD(bus_child_location, ahci_child_location),
|
|
DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods,
|
|
sizeof(struct tegra_ahci_sc));
|
|
DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, NULL, NULL);
|