974 lines
25 KiB
C
974 lines
25 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2011 Ben Gray <ben.r.gray@gmail.com>.
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* Copyright (c) 2014 Luiz Otavio O Souza <loos@freebsd.org>.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/**
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* Driver for the I2C module on the TI SoC.
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*
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* This driver is heavily based on the TWI driver for the AT91 (at91_twi.c).
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*
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* CAUTION: The I2Ci registers are limited to 16 bit and 8 bit data accesses,
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* 32 bit data access is not allowed and can corrupt register content.
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*
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* This driver currently doesn't use DMA for the transfer, although I hope to
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* incorporate that sometime in the future. The idea being that for transaction
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* larger than a certain size the DMA engine is used, for anything less the
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* normal interrupt/fifo driven option is used.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/lock.h>
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#include <sys/mbuf.h>
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#include <sys/malloc.h>
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#include <sys/module.h>
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#include <sys/mutex.h>
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#include <sys/rman.h>
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#include <sys/sysctl.h>
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#include <machine/bus.h>
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#include <dev/ofw/openfirm.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <arm/ti/ti_cpuid.h>
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#include <arm/ti/ti_sysc.h>
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#include <arm/ti/ti_i2c.h>
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#include <dev/iicbus/iiconf.h>
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#include <dev/iicbus/iicbus.h>
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#include "iicbus_if.h"
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/**
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* I2C device driver context, a pointer to this is stored in the device
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* driver structure.
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*/
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struct ti_i2c_softc
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{
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device_t sc_dev;
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struct resource* sc_irq_res;
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struct resource* sc_mem_res;
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device_t sc_iicbus;
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void* sc_irq_h;
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struct mtx sc_mtx;
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struct iic_msg* sc_buffer;
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int sc_bus_inuse;
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int sc_buffer_pos;
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int sc_error;
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int sc_fifo_trsh;
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int sc_timeout;
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uint16_t sc_con_reg;
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uint16_t sc_rev;
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};
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struct ti_i2c_clock_config
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{
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u_int frequency; /* Bus frequency in Hz */
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uint8_t psc; /* Fast/Standard mode prescale divider */
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uint8_t scll; /* Fast/Standard mode SCL low time */
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uint8_t sclh; /* Fast/Standard mode SCL high time */
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uint8_t hsscll; /* High Speed mode SCL low time */
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uint8_t hssclh; /* High Speed mode SCL high time */
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};
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#if defined(SOC_OMAP4)
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/*
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* OMAP4 i2c bus clock is 96MHz / ((psc + 1) * (scll + 7 + sclh + 5)).
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* The prescaler values for 100KHz and 400KHz modes come from the table in the
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* OMAP4 TRM. The table doesn't list 1MHz; these values should give that speed.
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*/
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static struct ti_i2c_clock_config ti_omap4_i2c_clock_configs[] = {
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{ 100000, 23, 13, 15, 0, 0},
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{ 400000, 9, 5, 7, 0, 0},
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{ 1000000, 3, 5, 7, 0, 0},
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/* { 3200000, 1, 113, 115, 7, 10}, - HS mode */
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{ 0 /* Table terminator */ }
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};
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#endif
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#if defined(SOC_TI_AM335X)
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/*
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* AM335x i2c bus clock is 48MHZ / ((psc + 1) * (scll + 7 + sclh + 5))
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* In all cases we prescale the clock to 24MHz as recommended in the manual.
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*/
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static struct ti_i2c_clock_config ti_am335x_i2c_clock_configs[] = {
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{ 100000, 1, 111, 117, 0, 0},
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{ 400000, 1, 23, 25, 0, 0},
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{ 1000000, 1, 5, 7, 0, 0},
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{ 0 /* Table terminator */ }
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};
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#endif
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/**
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* Locking macros used throughout the driver
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*/
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#define TI_I2C_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx)
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#define TI_I2C_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx)
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#define TI_I2C_LOCK_INIT(_sc) \
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mtx_init(&_sc->sc_mtx, device_get_nameunit(_sc->sc_dev), \
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"ti_i2c", MTX_DEF)
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#define TI_I2C_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx)
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#define TI_I2C_ASSERT_LOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_OWNED)
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#define TI_I2C_ASSERT_UNLOCKED(_sc) mtx_assert(&_sc->sc_mtx, MA_NOTOWNED)
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#ifdef DEBUG
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#define ti_i2c_dbg(_sc, fmt, args...) \
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device_printf((_sc)->sc_dev, fmt, ##args)
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#else
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#define ti_i2c_dbg(_sc, fmt, args...)
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#endif
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/**
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* ti_i2c_read_2 - reads a 16-bit value from one of the I2C registers
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* @sc: I2C device context
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* @off: the byte offset within the register bank to read from.
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*
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*
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* LOCKING:
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* No locking required
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*
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* RETURNS:
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* 16-bit value read from the register.
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*/
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static inline uint16_t
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ti_i2c_read_2(struct ti_i2c_softc *sc, bus_size_t off)
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{
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return (bus_read_2(sc->sc_mem_res, off));
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}
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/**
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* ti_i2c_write_2 - writes a 16-bit value to one of the I2C registers
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* @sc: I2C device context
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* @off: the byte offset within the register bank to read from.
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* @val: the value to write into the register
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*
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* LOCKING:
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* No locking required
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*
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* RETURNS:
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* 16-bit value read from the register.
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*/
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static inline void
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ti_i2c_write_2(struct ti_i2c_softc *sc, bus_size_t off, uint16_t val)
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{
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bus_write_2(sc->sc_mem_res, off, val);
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}
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static int
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ti_i2c_transfer_intr(struct ti_i2c_softc* sc, uint16_t status)
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{
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int amount, done, i;
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done = 0;
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amount = 0;
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/* Check for the error conditions. */
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if (status & I2C_STAT_NACK) {
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/* No ACK from slave. */
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ti_i2c_dbg(sc, "NACK\n");
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_NACK);
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sc->sc_error = ENXIO;
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} else if (status & I2C_STAT_AL) {
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/* Arbitration lost. */
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ti_i2c_dbg(sc, "Arbitration lost\n");
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_AL);
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sc->sc_error = ENXIO;
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}
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/* Check if we have finished. */
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if (status & I2C_STAT_ARDY) {
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/* Register access ready - transaction complete basically. */
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ti_i2c_dbg(sc, "ARDY transaction complete\n");
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if (sc->sc_error != 0 && sc->sc_buffer->flags & IIC_M_NOSTOP) {
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ti_i2c_write_2(sc, I2C_REG_CON,
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sc->sc_con_reg | I2C_CON_STP);
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}
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ti_i2c_write_2(sc, I2C_REG_STATUS,
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I2C_STAT_ARDY | I2C_STAT_RDR | I2C_STAT_RRDY |
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I2C_STAT_XDR | I2C_STAT_XRDY);
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return (1);
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}
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if (sc->sc_buffer->flags & IIC_M_RD) {
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/* Read some data. */
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if (status & I2C_STAT_RDR) {
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/*
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* Receive draining interrupt - last data received.
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* The set FIFO threshold won't be reached to trigger
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* RRDY.
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*/
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ti_i2c_dbg(sc, "Receive draining interrupt\n");
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/*
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* Drain the FIFO. Read the pending data in the FIFO.
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*/
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amount = sc->sc_buffer->len - sc->sc_buffer_pos;
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} else if (status & I2C_STAT_RRDY) {
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/*
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* Receive data ready interrupt - FIFO has reached the
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* set threshold.
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*/
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ti_i2c_dbg(sc, "Receive data ready interrupt\n");
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amount = min(sc->sc_fifo_trsh,
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sc->sc_buffer->len - sc->sc_buffer_pos);
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}
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/* Read the bytes from the fifo. */
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for (i = 0; i < amount; i++)
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sc->sc_buffer->buf[sc->sc_buffer_pos++] =
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(uint8_t)(ti_i2c_read_2(sc, I2C_REG_DATA) & 0xff);
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if (status & I2C_STAT_RDR)
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RDR);
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if (status & I2C_STAT_RRDY)
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_RRDY);
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} else {
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/* Write some data. */
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if (status & I2C_STAT_XDR) {
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/*
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* Transmit draining interrupt - FIFO level is below
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* the set threshold and the amount of data still to
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* be transferred won't reach the set FIFO threshold.
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*/
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ti_i2c_dbg(sc, "Transmit draining interrupt\n");
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/*
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* Drain the TX data. Write the pending data in the
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* FIFO.
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*/
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amount = sc->sc_buffer->len - sc->sc_buffer_pos;
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} else if (status & I2C_STAT_XRDY) {
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/*
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* Transmit data ready interrupt - the FIFO level
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* is below the set threshold.
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*/
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ti_i2c_dbg(sc, "Transmit data ready interrupt\n");
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amount = min(sc->sc_fifo_trsh,
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sc->sc_buffer->len - sc->sc_buffer_pos);
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}
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/* Write the bytes from the fifo. */
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for (i = 0; i < amount; i++)
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ti_i2c_write_2(sc, I2C_REG_DATA,
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sc->sc_buffer->buf[sc->sc_buffer_pos++]);
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if (status & I2C_STAT_XDR)
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XDR);
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if (status & I2C_STAT_XRDY)
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ti_i2c_write_2(sc, I2C_REG_STATUS, I2C_STAT_XRDY);
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}
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return (done);
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}
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/**
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* ti_i2c_intr - interrupt handler for the I2C module
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* @dev: i2c device handle
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*
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*
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*
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* LOCKING:
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* Called from timer context
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*
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* RETURNS:
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* EH_HANDLED or EH_NOT_HANDLED
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*/
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static void
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ti_i2c_intr(void *arg)
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{
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int done;
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struct ti_i2c_softc *sc;
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uint16_t events, status;
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sc = (struct ti_i2c_softc *)arg;
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TI_I2C_LOCK(sc);
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status = ti_i2c_read_2(sc, I2C_REG_STATUS);
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if (status == 0) {
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TI_I2C_UNLOCK(sc);
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return;
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}
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/* Save enabled interrupts. */
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events = ti_i2c_read_2(sc, I2C_REG_IRQENABLE_SET);
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/* We only care about enabled interrupts. */
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status &= events;
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done = 0;
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if (sc->sc_buffer != NULL)
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done = ti_i2c_transfer_intr(sc, status);
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else {
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ti_i2c_dbg(sc, "Transfer interrupt without buffer\n");
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sc->sc_error = EINVAL;
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done = 1;
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}
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if (done)
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/* Wakeup the process that started the transaction. */
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wakeup(sc);
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TI_I2C_UNLOCK(sc);
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}
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/**
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* ti_i2c_transfer - called to perform the transfer
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* @dev: i2c device handle
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* @msgs: the messages to send/receive
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* @nmsgs: the number of messages in the msgs array
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*
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*
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* LOCKING:
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* Internally locked
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*
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* RETURNS:
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* 0 on function succeeded
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* EINVAL if invalid message is passed as an arg
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*/
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static int
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ti_i2c_transfer(device_t dev, struct iic_msg *msgs, uint32_t nmsgs)
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{
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int err, i, repstart, timeout;
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struct ti_i2c_softc *sc;
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uint16_t reg;
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sc = device_get_softc(dev);
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TI_I2C_LOCK(sc);
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/* If the controller is busy wait until it is available. */
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while (sc->sc_bus_inuse == 1)
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mtx_sleep(sc, &sc->sc_mtx, 0, "i2cbuswait", 0);
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/* Now we have control over the I2C controller. */
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sc->sc_bus_inuse = 1;
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err = 0;
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repstart = 0;
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for (i = 0; i < nmsgs; i++) {
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sc->sc_buffer = &msgs[i];
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sc->sc_buffer_pos = 0;
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sc->sc_error = 0;
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/* Zero byte transfers aren't allowed. */
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if (sc->sc_buffer == NULL || sc->sc_buffer->buf == NULL ||
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sc->sc_buffer->len == 0) {
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err = EINVAL;
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break;
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}
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/* Check if the i2c bus is free. */
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if (repstart == 0) {
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/*
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* On repeated start we send the START condition while
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* the bus _is_ busy.
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*/
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timeout = 0;
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while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
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if (timeout++ > 100) {
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err = EBUSY;
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goto out;
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}
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DELAY(1000);
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}
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timeout = 0;
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} else
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repstart = 0;
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if (sc->sc_buffer->flags & IIC_M_NOSTOP)
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repstart = 1;
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/* Set the slave address. */
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ti_i2c_write_2(sc, I2C_REG_SA, msgs[i].slave >> 1);
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/* Write the data length. */
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ti_i2c_write_2(sc, I2C_REG_CNT, sc->sc_buffer->len);
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/* Clear the RX and the TX FIFO. */
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reg = ti_i2c_read_2(sc, I2C_REG_BUF);
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reg |= I2C_BUF_RXFIFO_CLR | I2C_BUF_TXFIFO_CLR;
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ti_i2c_write_2(sc, I2C_REG_BUF, reg);
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reg = sc->sc_con_reg | I2C_CON_STT;
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if (repstart == 0)
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reg |= I2C_CON_STP;
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if ((sc->sc_buffer->flags & IIC_M_RD) == 0)
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reg |= I2C_CON_TRX;
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ti_i2c_write_2(sc, I2C_REG_CON, reg);
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/* Wait for an event. */
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err = mtx_sleep(sc, &sc->sc_mtx, 0, "i2ciowait", sc->sc_timeout);
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if (err == 0)
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err = sc->sc_error;
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if (err)
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break;
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}
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out:
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if (timeout == 0) {
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while (ti_i2c_read_2(sc, I2C_REG_STATUS_RAW) & I2C_STAT_BB) {
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if (timeout++ > 100)
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break;
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DELAY(1000);
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}
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}
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/* Put the controller in master mode again. */
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if ((ti_i2c_read_2(sc, I2C_REG_CON) & I2C_CON_MST) == 0)
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ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
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sc->sc_buffer = NULL;
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sc->sc_bus_inuse = 0;
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/* Wake up the processes that are waiting for the bus. */
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wakeup(sc);
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TI_I2C_UNLOCK(sc);
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return (err);
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}
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|
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static int
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ti_i2c_reset(struct ti_i2c_softc *sc, u_char speed)
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{
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int timeout;
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struct ti_i2c_clock_config *clkcfg;
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u_int busfreq;
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uint16_t fifo_trsh, reg, scll, sclh;
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|
|
|
switch (ti_chip()) {
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#ifdef SOC_OMAP4
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case CHIP_OMAP_4:
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clkcfg = ti_omap4_i2c_clock_configs;
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break;
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#endif
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|
#ifdef SOC_TI_AM335X
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case CHIP_AM335X:
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clkcfg = ti_am335x_i2c_clock_configs;
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break;
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#endif
|
|
default:
|
|
panic("Unknown TI SoC, unable to reset the i2c");
|
|
}
|
|
|
|
/*
|
|
* If we haven't attached the bus yet, just init at the default slow
|
|
* speed. This lets us get the hardware initialized enough to attach
|
|
* the bus which is where the real speed configuration is handled. After
|
|
* the bus is attached, get the configured speed from it. Search the
|
|
* configuration table for the best speed we can do that doesn't exceed
|
|
* the requested speed.
|
|
*/
|
|
if (sc->sc_iicbus == NULL)
|
|
busfreq = 100000;
|
|
else
|
|
busfreq = IICBUS_GET_FREQUENCY(sc->sc_iicbus, speed);
|
|
for (;;) {
|
|
if (clkcfg[1].frequency == 0 || clkcfg[1].frequency > busfreq)
|
|
break;
|
|
clkcfg++;
|
|
}
|
|
|
|
/*
|
|
* 23.1.4.3 - HS I2C Software Reset
|
|
* From OMAP4 TRM at page 4068.
|
|
*
|
|
* 1. Ensure that the module is disabled.
|
|
*/
|
|
sc->sc_con_reg = 0;
|
|
ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
|
|
|
|
/* 2. Issue a softreset to the controller. */
|
|
bus_write_2(sc->sc_mem_res, I2C_REG_SYSC, I2C_REG_SYSC_SRST);
|
|
|
|
/*
|
|
* 3. Enable the module.
|
|
* The I2Ci.I2C_SYSS[0] RDONE bit is asserted only after the module
|
|
* is enabled by setting the I2Ci.I2C_CON[15] I2C_EN bit to 1.
|
|
*/
|
|
ti_i2c_write_2(sc, I2C_REG_CON, I2C_CON_I2C_EN);
|
|
|
|
/* 4. Wait for the software reset to complete. */
|
|
timeout = 0;
|
|
while ((ti_i2c_read_2(sc, I2C_REG_SYSS) & I2C_SYSS_RDONE) == 0) {
|
|
if (timeout++ > 100)
|
|
return (EBUSY);
|
|
DELAY(100);
|
|
}
|
|
|
|
/*
|
|
* Disable the I2C controller once again, now that the reset has
|
|
* finished.
|
|
*/
|
|
ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
|
|
|
|
/*
|
|
* The following sequence is taken from the OMAP4 TRM at page 4077.
|
|
*
|
|
* 1. Enable the functional and interface clocks (see Section
|
|
* 23.1.5.1.1.1.1). Done at ti_i2c_activate().
|
|
*
|
|
* 2. Program the prescaler to obtain an approximately 12MHz internal
|
|
* sampling clock (I2Ci_INTERNAL_CLK) by programming the
|
|
* corresponding value in the I2Ci.I2C_PSC[3:0] PSC field.
|
|
* This value depends on the frequency of the functional clock
|
|
* (I2Ci_FCLK). Because this frequency is 96MHz, the
|
|
* I2Ci.I2C_PSC[7:0] PSC field value is 0x7.
|
|
*/
|
|
ti_i2c_write_2(sc, I2C_REG_PSC, clkcfg->psc);
|
|
|
|
/*
|
|
* 3. Program the I2Ci.I2C_SCLL[7:0] SCLL and I2Ci.I2C_SCLH[7:0] SCLH
|
|
* bit fields to obtain a bit rate of 100 Kbps, 400 Kbps or 1Mbps.
|
|
* These values depend on the internal sampling clock frequency
|
|
* (see Table 23-8).
|
|
*/
|
|
scll = clkcfg->scll & I2C_SCLL_MASK;
|
|
sclh = clkcfg->sclh & I2C_SCLH_MASK;
|
|
|
|
/*
|
|
* 4. (Optional) Program the I2Ci.I2C_SCLL[15:8] HSSCLL and
|
|
* I2Ci.I2C_SCLH[15:8] HSSCLH fields to obtain a bit rate of
|
|
* 400K bps or 3.4M bps (for the second phase of HS mode). These
|
|
* values depend on the internal sampling clock frequency (see
|
|
* Table 23-8).
|
|
*
|
|
* 5. (Optional) If a bit rate of 3.4M bps is used and the bus line
|
|
* capacitance exceeds 45 pF, (see Section 18.4.8, PAD Functional
|
|
* Multiplexing and Configuration).
|
|
*/
|
|
switch (ti_chip()) {
|
|
#ifdef SOC_OMAP4
|
|
case CHIP_OMAP_4:
|
|
if ((clkcfg->hsscll + clkcfg->hssclh) > 0) {
|
|
scll |= clkcfg->hsscll << I2C_HSSCLL_SHIFT;
|
|
sclh |= clkcfg->hssclh << I2C_HSSCLH_SHIFT;
|
|
sc->sc_con_reg |= I2C_CON_OPMODE_HS;
|
|
}
|
|
break;
|
|
#endif
|
|
}
|
|
|
|
/* Write the selected bit rate. */
|
|
ti_i2c_write_2(sc, I2C_REG_SCLL, scll);
|
|
ti_i2c_write_2(sc, I2C_REG_SCLH, sclh);
|
|
|
|
/*
|
|
* 6. Configure the Own Address of the I2C controller by storing it in
|
|
* the I2Ci.I2C_OA0 register. Up to four Own Addresses can be
|
|
* programmed in the I2Ci.I2C_OAi registers (where i = 0, 1, 2, 3)
|
|
* for each I2C controller.
|
|
*
|
|
* Note: For a 10-bit address, set the corresponding expand Own Address
|
|
* bit in the I2Ci.I2C_CON register.
|
|
*
|
|
* Driver currently always in single master mode so ignore this step.
|
|
*/
|
|
|
|
/*
|
|
* 7. Set the TX threshold (in transmitter mode) and the RX threshold
|
|
* (in receiver mode) by setting the I2Ci.I2C_BUF[5:0]XTRSH field to
|
|
* (TX threshold - 1) and the I2Ci.I2C_BUF[13:8]RTRSH field to (RX
|
|
* threshold - 1), where the TX and RX thresholds are greater than
|
|
* or equal to 1.
|
|
*
|
|
* The threshold is set to 5 for now.
|
|
*/
|
|
fifo_trsh = (sc->sc_fifo_trsh - 1) & I2C_BUF_TRSH_MASK;
|
|
reg = fifo_trsh | (fifo_trsh << I2C_BUF_RXTRSH_SHIFT);
|
|
ti_i2c_write_2(sc, I2C_REG_BUF, reg);
|
|
|
|
/*
|
|
* 8. Take the I2C controller out of reset by setting the
|
|
* I2Ci.I2C_CON[15] I2C_EN bit to 1.
|
|
*
|
|
* 23.1.5.1.1.1.2 - Initialize the I2C Controller
|
|
*
|
|
* To initialize the I2C controller, perform the following steps:
|
|
*
|
|
* 1. Configure the I2Ci.I2C_CON register:
|
|
* . For master or slave mode, set the I2Ci.I2C_CON[10] MST bit
|
|
* (0: slave, 1: master).
|
|
* . For transmitter or receiver mode, set the I2Ci.I2C_CON[9] TRX
|
|
* bit (0: receiver, 1: transmitter).
|
|
*/
|
|
|
|
/* Enable the I2C controller in master mode. */
|
|
sc->sc_con_reg |= I2C_CON_I2C_EN | I2C_CON_MST;
|
|
ti_i2c_write_2(sc, I2C_REG_CON, sc->sc_con_reg);
|
|
|
|
/*
|
|
* 2. If using an interrupt to transmit/receive data, set the
|
|
* corresponding bit in the I2Ci.I2C_IE register (the I2Ci.I2C_IE[4]
|
|
* XRDY_IE bit for the transmit interrupt, the I2Ci.I2C_IE[3] RRDY
|
|
* bit for the receive interrupt).
|
|
*/
|
|
|
|
/* Set the interrupts we want to be notified. */
|
|
reg = I2C_IE_XDR | /* Transmit draining interrupt. */
|
|
I2C_IE_XRDY | /* Transmit Data Ready interrupt. */
|
|
I2C_IE_RDR | /* Receive draining interrupt. */
|
|
I2C_IE_RRDY | /* Receive Data Ready interrupt. */
|
|
I2C_IE_ARDY | /* Register Access Ready interrupt. */
|
|
I2C_IE_NACK | /* No Acknowledgment interrupt. */
|
|
I2C_IE_AL; /* Arbitration lost interrupt. */
|
|
|
|
/* Enable the interrupts. */
|
|
ti_i2c_write_2(sc, I2C_REG_IRQENABLE_SET, reg);
|
|
|
|
/*
|
|
* 3. If using DMA to receive/transmit data, set to 1 the corresponding
|
|
* bit in the I2Ci.I2C_BUF register (the I2Ci.I2C_BUF[15] RDMA_EN
|
|
* bit for the receive DMA channel, the I2Ci.I2C_BUF[7] XDMA_EN bit
|
|
* for the transmit DMA channel).
|
|
*
|
|
* Not using DMA for now, so ignore this.
|
|
*/
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_i2c_iicbus_reset(device_t dev, u_char speed, u_char addr, u_char *oldaddr)
|
|
{
|
|
struct ti_i2c_softc *sc;
|
|
int err;
|
|
|
|
sc = device_get_softc(dev);
|
|
TI_I2C_LOCK(sc);
|
|
err = ti_i2c_reset(sc, speed);
|
|
TI_I2C_UNLOCK(sc);
|
|
if (err)
|
|
return (err);
|
|
|
|
return (IIC_ENOADDR);
|
|
}
|
|
|
|
static int
|
|
ti_i2c_activate(device_t dev)
|
|
{
|
|
int err;
|
|
struct ti_i2c_softc *sc;
|
|
|
|
sc = (struct ti_i2c_softc*)device_get_softc(dev);
|
|
|
|
/*
|
|
* 1. Enable the functional and interface clocks (see Section
|
|
* 23.1.5.1.1.1.1).
|
|
*/
|
|
err = ti_sysc_clock_enable(device_get_parent(dev));
|
|
if (err)
|
|
return (err);
|
|
|
|
return (ti_i2c_reset(sc, IIC_UNKNOWN));
|
|
}
|
|
|
|
/**
|
|
* ti_i2c_deactivate - deactivates the controller and releases resources
|
|
* @dev: i2c device handle
|
|
*
|
|
*
|
|
*
|
|
* LOCKING:
|
|
* Assumed called in an atomic context.
|
|
*
|
|
* RETURNS:
|
|
* nothing
|
|
*/
|
|
static void
|
|
ti_i2c_deactivate(device_t dev)
|
|
{
|
|
struct ti_i2c_softc *sc = device_get_softc(dev);
|
|
|
|
/* Disable the controller - cancel all transactions. */
|
|
ti_i2c_write_2(sc, I2C_REG_IRQENABLE_CLR, 0xffff);
|
|
ti_i2c_write_2(sc, I2C_REG_STATUS, 0xffff);
|
|
ti_i2c_write_2(sc, I2C_REG_CON, 0);
|
|
|
|
/* Release the interrupt handler. */
|
|
if (sc->sc_irq_h != NULL) {
|
|
bus_teardown_intr(dev, sc->sc_irq_res, sc->sc_irq_h);
|
|
sc->sc_irq_h = NULL;
|
|
}
|
|
|
|
/* Unmap the I2C controller registers. */
|
|
if (sc->sc_mem_res != NULL) {
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
sc->sc_mem_res = NULL;
|
|
}
|
|
|
|
/* Release the IRQ resource. */
|
|
if (sc->sc_irq_res != NULL) {
|
|
bus_release_resource(dev, SYS_RES_IRQ, 0, sc->sc_irq_res);
|
|
sc->sc_irq_res = NULL;
|
|
}
|
|
|
|
/* Finally disable the functional and interface clocks. */
|
|
ti_sysc_clock_disable(device_get_parent(dev));
|
|
}
|
|
|
|
static int
|
|
ti_i2c_sysctl_clk(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
int clk, psc, sclh, scll;
|
|
struct ti_i2c_softc *sc;
|
|
|
|
sc = arg1;
|
|
|
|
TI_I2C_LOCK(sc);
|
|
/* Get the system prescaler value. */
|
|
psc = (int)ti_i2c_read_2(sc, I2C_REG_PSC) + 1;
|
|
|
|
/* Get the bitrate. */
|
|
scll = (int)ti_i2c_read_2(sc, I2C_REG_SCLL) & I2C_SCLL_MASK;
|
|
sclh = (int)ti_i2c_read_2(sc, I2C_REG_SCLH) & I2C_SCLH_MASK;
|
|
|
|
clk = I2C_CLK / psc / (scll + 7 + sclh + 5);
|
|
TI_I2C_UNLOCK(sc);
|
|
|
|
return (sysctl_handle_int(oidp, &clk, 0, req));
|
|
}
|
|
|
|
static int
|
|
ti_i2c_sysctl_timeout(SYSCTL_HANDLER_ARGS)
|
|
{
|
|
struct ti_i2c_softc *sc;
|
|
unsigned int val;
|
|
int err;
|
|
|
|
sc = arg1;
|
|
|
|
/*
|
|
* MTX_DEF lock can't be held while doing uimove in
|
|
* sysctl_handle_int
|
|
*/
|
|
TI_I2C_LOCK(sc);
|
|
val = sc->sc_timeout;
|
|
TI_I2C_UNLOCK(sc);
|
|
|
|
err = sysctl_handle_int(oidp, &val, 0, req);
|
|
/* Write request? */
|
|
if ((err == 0) && (req->newptr != NULL)) {
|
|
TI_I2C_LOCK(sc);
|
|
sc->sc_timeout = val;
|
|
TI_I2C_UNLOCK(sc);
|
|
}
|
|
|
|
return (err);
|
|
}
|
|
|
|
static int
|
|
ti_i2c_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
if (!ofw_bus_is_compatible(dev, "ti,omap4-i2c"))
|
|
return (ENXIO);
|
|
device_set_desc(dev, "TI I2C Controller");
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
ti_i2c_attach(device_t dev)
|
|
{
|
|
int err, rid;
|
|
struct ti_i2c_softc *sc;
|
|
struct sysctl_ctx_list *ctx;
|
|
struct sysctl_oid_list *tree;
|
|
uint16_t fifosz;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->sc_dev = dev;
|
|
|
|
/* Get the memory resource for the register mapping. */
|
|
rid = 0;
|
|
sc->sc_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->sc_mem_res == NULL) {
|
|
device_printf(dev, "Cannot map registers.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
/* Allocate our IRQ resource. */
|
|
rid = 0;
|
|
sc->sc_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE | RF_SHAREABLE);
|
|
if (sc->sc_irq_res == NULL) {
|
|
bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->sc_mem_res);
|
|
device_printf(dev, "Cannot allocate interrupt.\n");
|
|
return (ENXIO);
|
|
}
|
|
|
|
TI_I2C_LOCK_INIT(sc);
|
|
|
|
/* First of all, we _must_ activate the H/W. */
|
|
err = ti_i2c_activate(dev);
|
|
if (err) {
|
|
device_printf(dev, "ti_i2c_activate failed\n");
|
|
goto out;
|
|
}
|
|
|
|
/* Read the version number of the I2C module */
|
|
sc->sc_rev = ti_i2c_read_2(sc, I2C_REG_REVNB_HI) & 0xff;
|
|
|
|
/* Get the fifo size. */
|
|
fifosz = ti_i2c_read_2(sc, I2C_REG_BUFSTAT);
|
|
fifosz >>= I2C_BUFSTAT_FIFODEPTH_SHIFT;
|
|
fifosz &= I2C_BUFSTAT_FIFODEPTH_MASK;
|
|
|
|
device_printf(dev, "I2C revision %d.%d FIFO size: %d bytes\n",
|
|
sc->sc_rev >> 4, sc->sc_rev & 0xf, 8 << fifosz);
|
|
|
|
/* Set the FIFO threshold to 5 for now. */
|
|
sc->sc_fifo_trsh = 5;
|
|
|
|
/* Set I2C bus timeout */
|
|
sc->sc_timeout = 5*hz;
|
|
|
|
ctx = device_get_sysctl_ctx(dev);
|
|
tree = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
|
|
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_clock",
|
|
CTLFLAG_RD | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
|
|
ti_i2c_sysctl_clk, "IU", "I2C bus clock");
|
|
|
|
SYSCTL_ADD_PROC(ctx, tree, OID_AUTO, "i2c_timeout",
|
|
CTLFLAG_RW | CTLTYPE_UINT | CTLFLAG_MPSAFE, sc, 0,
|
|
ti_i2c_sysctl_timeout, "IU", "I2C bus timeout (in ticks)");
|
|
|
|
/* Activate the interrupt. */
|
|
err = bus_setup_intr(dev, sc->sc_irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, ti_i2c_intr, sc, &sc->sc_irq_h);
|
|
if (err)
|
|
goto out;
|
|
|
|
/* Attach the iicbus. */
|
|
if ((sc->sc_iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
|
|
device_printf(dev, "could not allocate iicbus instance\n");
|
|
err = ENXIO;
|
|
goto out;
|
|
}
|
|
|
|
/* Probe and attach the iicbus when interrupts are available. */
|
|
err = bus_delayed_attach_children(dev);
|
|
|
|
out:
|
|
if (err) {
|
|
ti_i2c_deactivate(dev);
|
|
TI_I2C_LOCK_DESTROY(sc);
|
|
}
|
|
|
|
return (err);
|
|
}
|
|
|
|
static int
|
|
ti_i2c_detach(device_t dev)
|
|
{
|
|
struct ti_i2c_softc *sc;
|
|
int rv;
|
|
|
|
sc = device_get_softc(dev);
|
|
|
|
if ((rv = bus_generic_detach(dev)) != 0) {
|
|
device_printf(dev, "cannot detach child devices\n");
|
|
return (rv);
|
|
}
|
|
|
|
if (sc->sc_iicbus &&
|
|
(rv = device_delete_child(dev, sc->sc_iicbus)) != 0)
|
|
return (rv);
|
|
|
|
ti_i2c_deactivate(dev);
|
|
TI_I2C_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
ti_i2c_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
/* Share controller node with iibus device. */
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static device_method_t ti_i2c_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, ti_i2c_probe),
|
|
DEVMETHOD(device_attach, ti_i2c_attach),
|
|
DEVMETHOD(device_detach, ti_i2c_detach),
|
|
|
|
/* Bus interface */
|
|
DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
|
|
DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
|
|
DEVMETHOD(bus_alloc_resource, bus_generic_alloc_resource),
|
|
DEVMETHOD(bus_release_resource, bus_generic_release_resource),
|
|
DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
|
|
DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
|
|
DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource),
|
|
DEVMETHOD(bus_set_resource, bus_generic_rl_set_resource),
|
|
DEVMETHOD(bus_get_resource, bus_generic_rl_get_resource),
|
|
|
|
/* OFW methods */
|
|
DEVMETHOD(ofw_bus_get_node, ti_i2c_get_node),
|
|
|
|
/* iicbus interface */
|
|
DEVMETHOD(iicbus_callback, iicbus_null_callback),
|
|
DEVMETHOD(iicbus_reset, ti_i2c_iicbus_reset),
|
|
DEVMETHOD(iicbus_transfer, ti_i2c_transfer),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t ti_i2c_driver = {
|
|
"iichb",
|
|
ti_i2c_methods,
|
|
sizeof(struct ti_i2c_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(ti_iic, simplebus, ti_i2c_driver, 0, 0);
|
|
DRIVER_MODULE(iicbus, ti_iic, iicbus_driver, 0, 0);
|
|
|
|
MODULE_DEPEND(ti_iic, ti_sysc, 1, 1, 1);
|
|
MODULE_DEPEND(ti_iic, iicbus, 1, 1, 1);
|