500 lines
13 KiB
C
500 lines
13 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* A GPIO driver for Xilinx Zynq-7000.
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*
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* The GPIO peripheral on Zynq allows controlling 114 general purpose I/Os.
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*
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* Pins 53-0 are sent to the MIO. Any MIO pins not used by a PS peripheral are
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* available as a GPIO pin. Pins 64-127 are sent to the PL (FPGA) section of
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* Zynq as EMIO signals.
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*
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* The hardware provides a way to use IOs as interrupt sources but the
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* gpio framework doesn't seem to have hooks for this.
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*
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585. GPIO is covered in
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* chater 14. Register definitions are in appendix B.19.
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*/
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#include <sys/cdefs.h>
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/bus.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/gpio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <dev/gpio/gpiobusvar.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include "gpio_if.h"
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#define ZYNQ7_MAX_BANK 4
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#define ZYNQMP_MAX_BANK 6
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/* Zynq 7000 */
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#define ZYNQ7_BANK0_PIN_MIN 0
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#define ZYNQ7_BANK0_NPIN 32
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#define ZYNQ7_BANK1_PIN_MIN 32
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#define ZYNQ7_BANK1_NPIN 22
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#define ZYNQ7_BANK2_PIN_MIN 64
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#define ZYNQ7_BANK2_NPIN 32
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#define ZYNQ7_BANK3_PIN_MIN 96
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#define ZYNQ7_BANK3_NPIN 32
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#define ZYNQ7_PIN_MIO_MIN 0
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#define ZYNQ7_PIN_MIO_MAX 54
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#define ZYNQ7_PIN_EMIO_MIN 64
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#define ZYNQ7_PIN_EMIO_MAX 118
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/* ZynqMP */
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#define ZYNQMP_BANK0_PIN_MIN 0
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#define ZYNQMP_BANK0_NPIN 26
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#define ZYNQMP_BANK1_PIN_MIN 26
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#define ZYNQMP_BANK1_NPIN 26
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#define ZYNQMP_BANK2_PIN_MIN 52
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#define ZYNQMP_BANK2_NPIN 26
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#define ZYNQMP_BANK3_PIN_MIN 78
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#define ZYNQMP_BANK3_NPIN 32
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#define ZYNQMP_BANK4_PIN_MIN 110
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#define ZYNQMP_BANK4_NPIN 32
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#define ZYNQMP_BANK5_PIN_MIN 142
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#define ZYNQMP_BANK5_NPIN 32
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#define ZYNQMP_PIN_MIO_MIN 0
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#define ZYNQMP_PIN_MIO_MAX 77
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#define ZYNQMP_PIN_EMIO_MIN 78
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#define ZYNQMP_PIN_EMIO_MAX 174
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#define ZYNQ_BANK_NPIN(type, bank) (ZYNQ##type##_BANK##bank##_NPIN)
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#define ZYNQ_BANK_PIN_MIN(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN)
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#define ZYNQ_BANK_PIN_MAX(type, bank) (ZYNQ##type##_BANK##bank##_PIN_MIN + ZYNQ##type##_BANK##bank##_NPIN - 1)
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#define ZYNQ_PIN_IS_MIO(type, pin) (pin >= ZYNQ##type##_PIN_MIO_MIN && \
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pin <= ZYNQ##type##_PIN_MIO_MAX)
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#define ZYNQ_PIN_IS_EMIO(type, pin) (pin >= ZYNQ##type##_PIN_EMIO_MIN && \
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pin <= ZYNQ##type##_PIN_EMIO_MAX)
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#define ZGPIO_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define ZGPIO_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define ZGPIO_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), \
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"gpio", MTX_DEF)
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#define ZGPIO_LOCK_DESTROY(_sc) mtx_destroy(&_sc->sc_mtx);
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enum zynq_gpio_type {
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ZYNQ_7000 = 0,
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ZYNQMP,
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};
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struct zynq_gpio_conf {
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char *name;
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enum zynq_gpio_type type;
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uint32_t nbanks;
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uint32_t maxpin;
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uint32_t bank_min[ZYNQMP_MAX_BANK];
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uint32_t bank_max[ZYNQMP_MAX_BANK];
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};
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struct zy7_gpio_softc {
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device_t dev;
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device_t busdev;
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struct mtx sc_mtx;
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struct resource *mem_res; /* Memory resource */
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struct zynq_gpio_conf *conf;
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};
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static struct zynq_gpio_conf z7_gpio_conf = {
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.name = "Zynq-7000 GPIO Controller",
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.type = ZYNQ_7000,
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.nbanks = ZYNQ7_MAX_BANK,
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.maxpin = ZYNQ7_PIN_EMIO_MAX,
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.bank_min[0] = ZYNQ_BANK_PIN_MIN(7, 0),
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.bank_max[0] = ZYNQ_BANK_PIN_MAX(7, 0),
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.bank_min[1] = ZYNQ_BANK_PIN_MIN(7, 1),
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.bank_max[1] = ZYNQ_BANK_PIN_MAX(7, 1),
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.bank_min[2] = ZYNQ_BANK_PIN_MIN(7, 2),
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.bank_max[2] = ZYNQ_BANK_PIN_MAX(7, 2),
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.bank_min[3] = ZYNQ_BANK_PIN_MIN(7, 3),
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.bank_max[3] = ZYNQ_BANK_PIN_MAX(7, 3),
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};
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static struct zynq_gpio_conf zynqmp_gpio_conf = {
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.name = "ZynqMP GPIO Controller",
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.type = ZYNQMP,
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.nbanks = ZYNQMP_MAX_BANK,
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.maxpin = ZYNQMP_PIN_EMIO_MAX,
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.bank_min[0] = ZYNQ_BANK_PIN_MIN(MP, 0),
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.bank_max[0] = ZYNQ_BANK_PIN_MAX(MP, 0),
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.bank_min[1] = ZYNQ_BANK_PIN_MIN(MP, 1),
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.bank_max[1] = ZYNQ_BANK_PIN_MAX(MP, 1),
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.bank_min[2] = ZYNQ_BANK_PIN_MIN(MP, 2),
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.bank_max[2] = ZYNQ_BANK_PIN_MAX(MP, 2),
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.bank_min[3] = ZYNQ_BANK_PIN_MIN(MP, 3),
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.bank_max[3] = ZYNQ_BANK_PIN_MAX(MP, 3),
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.bank_min[4] = ZYNQ_BANK_PIN_MIN(MP, 4),
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.bank_max[4] = ZYNQ_BANK_PIN_MAX(MP, 4),
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.bank_min[5] = ZYNQ_BANK_PIN_MIN(MP, 5),
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.bank_max[5] = ZYNQ_BANK_PIN_MAX(MP, 5),
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};
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static struct ofw_compat_data compat_data[] = {
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{"xlnx,zy7_gpio", (uintptr_t)&z7_gpio_conf},
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{"xlnx,zynqmp-gpio-1.0", (uintptr_t)&zynqmp_gpio_conf},
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{NULL, 0},
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};
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#define WR4(sc, off, val) bus_write_4((sc)->mem_res, (off), (val))
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#define RD4(sc, off) bus_read_4((sc)->mem_res, (off))
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/* Xilinx Zynq-7000 GPIO register definitions:
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*/
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#define ZY7_GPIO_MASK_DATA_LSW(b) (0x0000+8*(b)) /* maskable wr lo */
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#define ZY7_GPIO_MASK_DATA_MSW(b) (0x0004+8*(b)) /* maskable wr hi */
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#define ZY7_GPIO_DATA(b) (0x0040+4*(b)) /* in/out data */
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#define ZY7_GPIO_DATA_RO(b) (0x0060+4*(b)) /* input data */
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#define ZY7_GPIO_DIRM(b) (0x0204+0x40*(b)) /* direction mode */
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#define ZY7_GPIO_OEN(b) (0x0208+0x40*(b)) /* output enable */
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#define ZY7_GPIO_INT_MASK(b) (0x020c+0x40*(b)) /* int mask */
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#define ZY7_GPIO_INT_EN(b) (0x0210+0x40*(b)) /* int enable */
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#define ZY7_GPIO_INT_DIS(b) (0x0214+0x40*(b)) /* int disable */
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#define ZY7_GPIO_INT_STAT(b) (0x0218+0x40*(b)) /* int status */
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#define ZY7_GPIO_INT_TYPE(b) (0x021c+0x40*(b)) /* int type */
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#define ZY7_GPIO_INT_POLARITY(b) (0x0220+0x40*(b)) /* int polarity */
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#define ZY7_GPIO_INT_ANY(b) (0x0224+0x40*(b)) /* any edge */
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static device_t
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zy7_gpio_get_bus(device_t dev)
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{
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struct zy7_gpio_softc *sc;
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sc = device_get_softc(dev);
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return (sc->busdev);
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}
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static int
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zy7_gpio_pin_max(device_t dev, int *maxpin)
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{
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struct zy7_gpio_softc *sc;
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sc = device_get_softc(dev);
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*maxpin = sc->conf->maxpin;
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return (0);
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}
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static inline bool
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zy7_pin_valid(device_t dev, uint32_t pin)
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{
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struct zy7_gpio_softc *sc;
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int i;
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bool found = false;
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sc = device_get_softc(dev);
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for (i = 0; i < sc->conf->nbanks; i++) {
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if (pin >= sc->conf->bank_min[i] && pin <= sc->conf->bank_max[i]) {
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found = true;
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break;
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}
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}
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return (found);
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}
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/* Get a specific pin's capabilities. */
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static int
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zy7_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps)
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{
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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*caps = (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
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return (0);
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}
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/* Get a specific pin's name. */
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static int
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zy7_gpio_pin_getname(device_t dev, uint32_t pin, char *name)
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{
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struct zy7_gpio_softc *sc;
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uint32_t emio_min;
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bool is_mio;
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sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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switch (sc->conf->type) {
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case ZYNQ_7000:
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is_mio = ZYNQ_PIN_IS_MIO(7, pin);
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emio_min = ZYNQ7_PIN_EMIO_MIN;
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break;
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case ZYNQMP:
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is_mio = ZYNQ_PIN_IS_MIO(MP, pin);
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emio_min = ZYNQMP_PIN_EMIO_MIN;
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break;
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default:
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return (EINVAL);
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}
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if (is_mio) {
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snprintf(name, GPIOMAXNAME, "MIO_%d", pin);
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name[GPIOMAXNAME - 1] = '\0';
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} else {
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snprintf(name, GPIOMAXNAME, "EMIO_%d", pin - emio_min);
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name[GPIOMAXNAME - 1] = '\0';
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}
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return (0);
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}
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/* Get a specific pin's current in/out/tri state. */
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static int
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zy7_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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if ((RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & (1 << (pin & 31))) != 0) {
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/* output */
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if ((RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & (1 << (pin & 31))) == 0)
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*flags = (GPIO_PIN_OUTPUT | GPIO_PIN_TRISTATE);
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else
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*flags = GPIO_PIN_OUTPUT;
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} else
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/* input */
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*flags = GPIO_PIN_INPUT;
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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/* Set a specific pin's in/out/tri state. */
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static int
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zy7_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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if ((flags & GPIO_PIN_OUTPUT) != 0) {
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/* Output. Set or reset OEN too. */
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WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
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RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) | (1 << (pin & 31)));
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if ((flags & GPIO_PIN_TRISTATE) != 0)
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) &
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~(1 << (pin & 31)));
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else
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) |
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(1 << (pin & 31)));
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} else {
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/* Input. Turn off OEN. */
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WR4(sc, ZY7_GPIO_DIRM(pin >> 5),
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RD4(sc, ZY7_GPIO_DIRM(pin >> 5)) & ~(1 << (pin & 31)));
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WR4(sc, ZY7_GPIO_OEN(pin >> 5),
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RD4(sc, ZY7_GPIO_OEN(pin >> 5)) & ~(1 << (pin & 31)));
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}
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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/* Set a specific output pin's value. */
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static int
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zy7_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin) || value > 1)
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return (EINVAL);
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/* Fancy register tricks allow atomic set or reset. */
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if ((pin & 16) != 0)
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WR4(sc, ZY7_GPIO_MASK_DATA_MSW(pin >> 5),
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(0xffff0000 ^ (0x10000 << (pin & 15))) |
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(value << (pin & 15)));
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else
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WR4(sc, ZY7_GPIO_MASK_DATA_LSW(pin >> 5),
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(0xffff0000 ^ (0x10000 << (pin & 15))) |
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(value << (pin & 15)));
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return (0);
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}
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/* Get a specific pin's input value. */
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static int
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zy7_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *value)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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*value = (RD4(sc, ZY7_GPIO_DATA_RO(pin >> 5)) >> (pin & 31)) & 1;
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return (0);
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}
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/* Toggle a pin's output value. */
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static int
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zy7_gpio_pin_toggle(device_t dev, uint32_t pin)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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if (!zy7_pin_valid(dev, pin))
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return (EINVAL);
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ZGPIO_LOCK(sc);
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WR4(sc, ZY7_GPIO_DATA(pin >> 5),
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RD4(sc, ZY7_GPIO_DATA(pin >> 5)) ^ (1 << (pin & 31)));
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ZGPIO_UNLOCK(sc);
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return (0);
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}
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static int
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zy7_gpio_probe(device_t dev)
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{
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struct zynq_gpio_conf *conf;
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if (!ofw_bus_status_okay(dev))
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return (ENXIO);
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conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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if (conf == 0)
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return (ENXIO);
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device_set_desc(dev, conf->name);
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return (0);
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}
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static int zy7_gpio_detach(device_t dev);
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static int
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zy7_gpio_attach(device_t dev)
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{
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struct zy7_gpio_softc *sc = device_get_softc(dev);
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int rid;
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sc->dev = dev;
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sc->conf = (struct zynq_gpio_conf *)ofw_bus_search_compatible(dev, compat_data)->ocd_data;
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ZGPIO_LOCK_INIT(sc);
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/* Allocate memory. */
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rid = 0;
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sc->mem_res = bus_alloc_resource_any(dev,
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SYS_RES_MEMORY, &rid, RF_ACTIVE);
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if (sc->mem_res == NULL) {
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device_printf(dev, "Can't allocate memory for device");
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zy7_gpio_detach(dev);
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return (ENOMEM);
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}
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sc->busdev = gpiobus_attach_bus(dev);
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if (sc->busdev == NULL) {
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zy7_gpio_detach(dev);
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return (ENOMEM);
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}
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return (0);
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}
|
|
|
|
static int
|
|
zy7_gpio_detach(device_t dev)
|
|
{
|
|
struct zy7_gpio_softc *sc = device_get_softc(dev);
|
|
|
|
gpiobus_detach_bus(dev);
|
|
|
|
if (sc->mem_res != NULL) {
|
|
/* Release memory resource. */
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
rman_get_rid(sc->mem_res), sc->mem_res);
|
|
}
|
|
|
|
ZGPIO_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static device_method_t zy7_gpio_methods[] = {
|
|
/* device_if */
|
|
DEVMETHOD(device_probe, zy7_gpio_probe),
|
|
DEVMETHOD(device_attach, zy7_gpio_attach),
|
|
DEVMETHOD(device_detach, zy7_gpio_detach),
|
|
|
|
/* GPIO protocol */
|
|
DEVMETHOD(gpio_get_bus, zy7_gpio_get_bus),
|
|
DEVMETHOD(gpio_pin_max, zy7_gpio_pin_max),
|
|
DEVMETHOD(gpio_pin_getname, zy7_gpio_pin_getname),
|
|
DEVMETHOD(gpio_pin_getflags, zy7_gpio_pin_getflags),
|
|
DEVMETHOD(gpio_pin_getcaps, zy7_gpio_pin_getcaps),
|
|
DEVMETHOD(gpio_pin_setflags, zy7_gpio_pin_setflags),
|
|
DEVMETHOD(gpio_pin_get, zy7_gpio_pin_get),
|
|
DEVMETHOD(gpio_pin_set, zy7_gpio_pin_set),
|
|
DEVMETHOD(gpio_pin_toggle, zy7_gpio_pin_toggle),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t zy7_gpio_driver = {
|
|
"gpio",
|
|
zy7_gpio_methods,
|
|
sizeof(struct zy7_gpio_softc),
|
|
};
|
|
|
|
EARLY_DRIVER_MODULE(zy7_gpio, simplebus, zy7_gpio_driver, 0, 0,
|
|
BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE);
|