752 lines
21 KiB
C
752 lines
21 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Thomas Skibo <thomasskibo@yahoo.com>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/cdefs.h>
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/*
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* This is a driver for the Quad-SPI Flash Controller in the Xilinx
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* Zynq-7000 SoC.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/conf.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <sys/sysctl.h>
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#include <sys/lock.h>
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#include <sys/mutex.h>
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#include <sys/resource.h>
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#include <sys/rman.h>
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#include <sys/uio.h>
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#include <machine/bus.h>
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#include <machine/resource.h>
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#include <machine/stdarg.h>
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#include <dev/fdt/fdt_common.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/spibus/spi.h>
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#include <dev/spibus/spibusvar.h>
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#include <dev/flash/mx25lreg.h>
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#include "spibus_if.h"
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static struct ofw_compat_data compat_data[] = {
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{"xlnx,zy7_qspi", 1},
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{"xlnx,zynq-qspi-1.0", 1},
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{NULL, 0}
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};
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struct zy7_qspi_softc {
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device_t dev;
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device_t child;
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struct mtx sc_mtx;
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struct resource *mem_res;
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struct resource *irq_res;
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void *intrhandle;
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uint32_t cfg_reg_shadow;
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uint32_t lqspi_cfg_shadow;
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uint32_t spi_clock;
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uint32_t ref_clock;
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unsigned int spi_clk_real_freq;
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unsigned int rx_overflows;
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unsigned int tx_underflows;
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unsigned int interrupts;
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unsigned int stray_ints;
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struct spi_command *cmd;
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int tx_bytes; /* tx_cmd_sz + tx_data_sz */
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int tx_bytes_sent;
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int rx_bytes; /* rx_cmd_sz + rx_data_sz */
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int rx_bytes_rcvd;
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int busy;
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int is_dual;
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int is_stacked;
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int is_dio;
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};
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#define ZY7_QSPI_DEFAULT_SPI_CLOCK 50000000
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#define QSPI_SC_LOCK(sc) mtx_lock(&(sc)->sc_mtx)
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#define QSPI_SC_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)
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#define QSPI_SC_LOCK_INIT(sc) \
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mtx_init(&(sc)->sc_mtx, device_get_nameunit((sc)->dev), NULL, MTX_DEF)
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#define QSPI_SC_LOCK_DESTROY(sc) mtx_destroy(&(sc)->sc_mtx)
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#define QSPI_SC_ASSERT_LOCKED(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED)
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#define RD4(sc, off) (bus_read_4((sc)->mem_res, (off)))
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#define WR4(sc, off, val) (bus_write_4((sc)->mem_res, (off), (val)))
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/*
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* QSPI device registers.
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.12.2) July 1, 2018. Xilinx doc UG585.
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*/
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#define ZY7_QSPI_CONFIG_REG 0x0000
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#define ZY7_QSPI_CONFIG_IFMODE (1U << 31)
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#define ZY7_QSPI_CONFIG_ENDIAN (1 << 26)
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#define ZY7_QSPI_CONFIG_HOLDB_DR (1 << 19)
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#define ZY7_QSPI_CONFIG_RSVD1 (1 << 17) /* must be 1 */
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#define ZY7_QSPI_CONFIG_MANSTRT (1 << 16)
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#define ZY7_QSPI_CONFIG_MANSTRTEN (1 << 15)
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#define ZY7_QSPI_CONFIG_SSFORCE (1 << 14)
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#define ZY7_QSPI_CONFIG_PCS (1 << 10)
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#define ZY7_QSPI_CONFIG_REF_CLK (1 << 8)
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#define ZY7_QSPI_CONFIG_FIFO_WIDTH_MASK (3 << 6)
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#define ZY7_QSPI_CONFIG_FIFO_WIDTH32 (3 << 6)
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#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_MASK (7 << 3)
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#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV_SHIFT 3
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#define ZY7_QSPI_CONFIG_BAUD_RATE_DIV(x) ((x) << 3) /* divide by 2<<x */
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#define ZY7_QSPI_CONFIG_CLK_PH (1 << 2) /* clock phase */
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#define ZY7_QSPI_CONFIG_CLK_POL (1 << 1) /* clock polarity */
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#define ZY7_QSPI_CONFIG_MODE_SEL (1 << 0) /* master enable */
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#define ZY7_QSPI_INTR_STAT_REG 0x0004
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#define ZY7_QSPI_INTR_EN_REG 0x0008
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#define ZY7_QSPI_INTR_DIS_REG 0x000c
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#define ZY7_QSPI_INTR_MASK_REG 0x0010
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#define ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW (1 << 6)
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#define ZY7_QSPI_INTR_RX_FIFO_FULL (1 << 5)
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#define ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY (1 << 4)
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#define ZY7_QSPI_INTR_TX_FIFO_FULL (1 << 3)
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#define ZY7_QSPI_INTR_TX_FIFO_NOT_FULL (1 << 2)
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#define ZY7_QSPI_INTR_RX_OVERFLOW (1 << 0)
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#define ZY7_QSPI_EN_REG 0x0014
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#define ZY7_SPI_ENABLE 1
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#define ZY7_QSPI_DELAY_REG 0x0018
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#define ZY7_QSPI_DELAY_NSS_MASK (0xffU << 24)
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#define ZY7_QSPI_DELAY_NSS_SHIFT 24
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#define ZY7_QSPI_DELAY_NSS(x) ((x) << 24)
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#define ZY7_QSPI_DELAY_BTWN_MASK (0xff << 16)
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#define ZY7_QSPI_DELAY_BTWN_SHIFT 16
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#define ZY7_QSPI_DELAY_BTWN(x) ((x) << 16)
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#define ZY7_QSPI_DELAY_AFTER_MASK (0xff << 8)
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#define ZY7_QSPI_DELAY_AFTER_SHIFT 8
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#define ZY7_QSPI_DELAY_AFTER(x) ((x) << 8)
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#define ZY7_QSPI_DELAY_INIT_MASK 0xff
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#define ZY7_QSPI_DELAY_INIT_SHIFT 0
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#define ZY7_QSPI_DELAY_INIT(x) (x)
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#define ZY7_QSPI_TXD0_REG 0x001c
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#define ZY7_QSPI_RX_DATA_REG 0x0020
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#define ZY7_QSPI_SLV_IDLE_CT_REG 0x0024
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#define ZY7_QSPI_SLV_IDLE_CT_MASK 0xff
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#define ZY7_QSPI_TX_THRESH_REG 0x0028
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#define ZY7_QSPI_RX_THRESH_REG 0x002c
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#define ZY7_QSPI_GPIO_REG 0x0030
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#define ZY7_QSPI_GPIO_WP_N 1
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#define ZY7_QSPI_LPBK_DLY_ADJ_REG 0x0038
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#define ZY7_QSPI_LPBK_DLY_ADJ_LPBK_SEL (1 << 8)
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#define ZY7_QSPI_LPBK_DLY_ADJ_LPBK_PH (1 << 7)
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#define ZY7_QSPI_LPBK_DLY_ADJ_USE_LPBK (1 << 5)
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY1_MASK (3 << 3)
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY1_SHIFT 3
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY1(x) ((x) << 3)
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY0_MASK 7
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY0_SHIFT 0
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#define ZY7_QSPI_LPBK_DLY_ADJ_DLY0(x) (x)
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#define ZY7_QSPI_TXD1_REG 0x0080
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#define ZY7_QSPI_TXD2_REG 0x0084
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#define ZY7_QSPI_TXD3_REG 0x0088
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#define ZY7_QSPI_LQSPI_CFG_REG 0x00a0
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#define ZY7_QSPI_LQSPI_CFG_LINEAR (1U << 31)
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#define ZY7_QSPI_LQSPI_CFG_TWO_MEM (1 << 30)
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#define ZY7_QSPI_LQSPI_CFG_SEP_BUS (1 << 29)
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#define ZY7_QSPI_LQSPI_CFG_U_PAGE (1 << 28)
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#define ZY7_QSPI_LQSPI_CFG_MODE_EN (1 << 25)
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#define ZY7_QSPI_LQSPI_CFG_MODE_ON (1 << 24)
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#define ZY7_QSPI_LQSPI_CFG_MODE_BITS_MASK (0xff << 16)
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#define ZY7_QSPI_LQSPI_CFG_MODE_BITS_SHIFT 16
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#define ZY7_QSPI_LQSPI_CFG_MODE_BITS(x) ((x) << 16)
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#define ZY7_QSPI_LQSPI_CFG_DUMMY_BYTES_MASK (7 << 8)
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#define ZY7_QSPI_LQSPI_CFG_DUMMY_BYTES_SHIFT 8
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#define ZY7_QSPI_LQSPI_CFG_DUMMY_BYTES(x) ((x) << 8)
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#define ZY7_QSPI_LQSPI_CFG_INST_CODE_MASK 0xff
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#define ZY7_QSPI_LQSPI_CFG_INST_CODE_SHIFT 0
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#define ZY7_QSPI_LQSPI_CFG_INST_CODE(x) (x)
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#define ZY7_QSPI_LQSPI_STS_REG 0x00a4
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#define ZY7_QSPI_LQSPI_STS_D_FSM_ERR (1 << 2)
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#define ZY7_QSPI_LQSPI_STS_WR_RECVD (1 << 1)
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#define ZY7_QSPI_MOD_ID_REG 0x00fc
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static int zy7_qspi_detach(device_t);
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/* Fill hardware fifo with command and data bytes. */
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static void
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zy7_qspi_write_fifo(struct zy7_qspi_softc *sc, int nbytes)
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{
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int n, nvalid;
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uint32_t data;
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while (nbytes > 0) {
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nvalid = MIN(4, nbytes);
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data = 0xffffffff;
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/*
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* A hardware bug forces us to wait until the tx fifo is
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* empty before writing partial words. We'll come back
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* next tx interrupt.
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*/
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if (nvalid < 4 && (RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
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ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) == 0)
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return;
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if (sc->tx_bytes_sent < sc->cmd->tx_cmd_sz) {
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/* Writing command. */
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n = MIN(nvalid, sc->cmd->tx_cmd_sz -
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sc->tx_bytes_sent);
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memcpy(&data, (uint8_t *)sc->cmd->tx_cmd +
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sc->tx_bytes_sent, n);
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if (nvalid > n) {
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/* Writing start of data. */
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memcpy((uint8_t *)&data + n,
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sc->cmd->tx_data, nvalid - n);
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}
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} else
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/* Writing data. */
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memcpy(&data, (uint8_t *)sc->cmd->tx_data +
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(sc->tx_bytes_sent - sc->cmd->tx_cmd_sz), nvalid);
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switch (nvalid) {
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case 1:
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WR4(sc, ZY7_QSPI_TXD1_REG, data);
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break;
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case 2:
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WR4(sc, ZY7_QSPI_TXD2_REG, data);
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break;
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case 3:
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WR4(sc, ZY7_QSPI_TXD3_REG, data);
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break;
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case 4:
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WR4(sc, ZY7_QSPI_TXD0_REG, data);
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break;
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}
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sc->tx_bytes_sent += nvalid;
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nbytes -= nvalid;
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}
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}
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/* Read hardware fifo data into command response and data buffers. */
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static void
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zy7_qspi_read_fifo(struct zy7_qspi_softc *sc)
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{
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int n, nbytes;
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uint32_t data;
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do {
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data = RD4(sc, ZY7_QSPI_RX_DATA_REG);
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nbytes = MIN(4, sc->rx_bytes - sc->rx_bytes_rcvd);
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/*
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* Last word in non-word-multiple transfer is packed
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* non-intuitively.
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*/
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if (nbytes < 4)
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data >>= 8 * (4 - nbytes);
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if (sc->rx_bytes_rcvd < sc->cmd->rx_cmd_sz) {
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/* Reading command. */
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n = MIN(nbytes, sc->cmd->rx_cmd_sz -
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sc->rx_bytes_rcvd);
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memcpy((uint8_t *)sc->cmd->rx_cmd + sc->rx_bytes_rcvd,
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&data, n);
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sc->rx_bytes_rcvd += n;
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nbytes -= n;
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data >>= 8 * n;
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}
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if (nbytes > 0) {
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/* Reading data. */
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memcpy((uint8_t *)sc->cmd->rx_data +
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(sc->rx_bytes_rcvd - sc->cmd->rx_cmd_sz),
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&data, nbytes);
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sc->rx_bytes_rcvd += nbytes;
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}
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} while (sc->rx_bytes_rcvd < sc->rx_bytes &&
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(RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
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ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0);
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}
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/* End a transfer early by draining rx fifo and disabling interrupts. */
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static void
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zy7_qspi_abort_transfer(struct zy7_qspi_softc *sc)
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{
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/* Drain receive fifo. */
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while ((RD4(sc, ZY7_QSPI_INTR_STAT_REG) &
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ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0)
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(void)RD4(sc, ZY7_QSPI_RX_DATA_REG);
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/* Shut down interrupts. */
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WR4(sc, ZY7_QSPI_INTR_DIS_REG,
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ZY7_QSPI_INTR_RX_OVERFLOW |
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ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY |
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ZY7_QSPI_INTR_TX_FIFO_NOT_FULL);
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}
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static void
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zy7_qspi_intr(void *arg)
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{
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struct zy7_qspi_softc *sc = (struct zy7_qspi_softc *)arg;
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uint32_t istatus;
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QSPI_SC_LOCK(sc);
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sc->interrupts++;
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istatus = RD4(sc, ZY7_QSPI_INTR_STAT_REG);
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/* Stray interrupts can happen if a transfer gets interrupted. */
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if (!sc->busy) {
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sc->stray_ints++;
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QSPI_SC_UNLOCK(sc);
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return;
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}
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if ((istatus & ZY7_QSPI_INTR_RX_OVERFLOW) != 0) {
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device_printf(sc->dev, "rx fifo overflow!\n");
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sc->rx_overflows++;
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/* Clear status bit. */
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WR4(sc, ZY7_QSPI_INTR_STAT_REG,
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ZY7_QSPI_INTR_RX_OVERFLOW);
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}
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/* Empty receive fifo before any more transmit data is sent. */
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if (sc->rx_bytes_rcvd < sc->rx_bytes &&
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(istatus & ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY) != 0) {
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zy7_qspi_read_fifo(sc);
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if (sc->rx_bytes_rcvd == sc->rx_bytes)
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/* Disable receive interrupts. */
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WR4(sc, ZY7_QSPI_INTR_DIS_REG,
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ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY |
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ZY7_QSPI_INTR_RX_OVERFLOW);
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}
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/*
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* Transmit underflows aren't really a bug because a hardware
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* bug forces us to allow the tx fifo to go empty between full
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* and partial fifo writes. Why bother counting?
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*/
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if ((istatus & ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW) != 0) {
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sc->tx_underflows++;
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/* Clear status bit. */
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WR4(sc, ZY7_QSPI_INTR_STAT_REG,
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ZY7_QSPI_INTR_TX_FIFO_UNDERFLOW);
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}
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/* Fill transmit fifo. */
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if (sc->tx_bytes_sent < sc->tx_bytes &&
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(istatus & ZY7_QSPI_INTR_TX_FIFO_NOT_FULL) != 0) {
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zy7_qspi_write_fifo(sc, MIN(240, sc->tx_bytes -
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sc->tx_bytes_sent));
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if (sc->tx_bytes_sent == sc->tx_bytes) {
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/*
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* Disable transmit FIFO interrupt, enable receive
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* FIFO interrupt.
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*/
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WR4(sc, ZY7_QSPI_INTR_DIS_REG,
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ZY7_QSPI_INTR_TX_FIFO_NOT_FULL);
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WR4(sc, ZY7_QSPI_INTR_EN_REG,
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ZY7_QSPI_INTR_RX_FIFO_NOT_EMPTY);
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}
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}
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/* Finished with transfer? */
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if (sc->tx_bytes_sent == sc->tx_bytes &&
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sc->rx_bytes_rcvd == sc->rx_bytes) {
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/* De-assert CS. */
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sc->cfg_reg_shadow |= ZY7_QSPI_CONFIG_PCS;
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WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
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wakeup(sc->dev);
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}
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QSPI_SC_UNLOCK(sc);
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}
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/* Initialize hardware. */
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static int
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zy7_qspi_init_hw(struct zy7_qspi_softc *sc)
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{
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uint32_t baud_div;
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/* Configure LQSPI Config register. Disable linear mode. */
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sc->lqspi_cfg_shadow = RD4(sc, ZY7_QSPI_LQSPI_CFG_REG);
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sc->lqspi_cfg_shadow &= ~(ZY7_QSPI_LQSPI_CFG_LINEAR |
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ZY7_QSPI_LQSPI_CFG_TWO_MEM |
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ZY7_QSPI_LQSPI_CFG_SEP_BUS);
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if (sc->is_dual) {
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sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_TWO_MEM;
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if (sc->is_stacked) {
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sc->lqspi_cfg_shadow &=
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|
~ZY7_QSPI_LQSPI_CFG_INST_CODE_MASK;
|
|
sc->lqspi_cfg_shadow |=
|
|
ZY7_QSPI_LQSPI_CFG_INST_CODE(sc->is_dio ?
|
|
CMD_READ_DUAL_IO : CMD_READ_QUAD_OUTPUT);
|
|
} else
|
|
sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_SEP_BUS;
|
|
}
|
|
WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow);
|
|
|
|
/* Find best clock divider. */
|
|
baud_div = 0;
|
|
while ((sc->ref_clock >> (baud_div + 1)) > sc->spi_clock &&
|
|
baud_div < 8)
|
|
baud_div++;
|
|
if (baud_div >= 8) {
|
|
device_printf(sc->dev, "cannot configure clock divider: ref=%d"
|
|
" spi=%d.\n", sc->ref_clock, sc->spi_clock);
|
|
return (EINVAL);
|
|
}
|
|
sc->spi_clk_real_freq = sc->ref_clock >> (baud_div + 1);
|
|
|
|
/*
|
|
* If divider is 2 (the max speed), use internal loopback master
|
|
* clock for read data. (See section 12.3.1 in ref man.)
|
|
*/
|
|
if (baud_div == 0)
|
|
WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG,
|
|
ZY7_QSPI_LPBK_DLY_ADJ_USE_LPBK |
|
|
ZY7_QSPI_LPBK_DLY_ADJ_DLY1(0) |
|
|
ZY7_QSPI_LPBK_DLY_ADJ_DLY0(0));
|
|
else
|
|
WR4(sc, ZY7_QSPI_LPBK_DLY_ADJ_REG, 0);
|
|
|
|
/* Set up configuration register. */
|
|
sc->cfg_reg_shadow =
|
|
ZY7_QSPI_CONFIG_IFMODE |
|
|
ZY7_QSPI_CONFIG_HOLDB_DR |
|
|
ZY7_QSPI_CONFIG_RSVD1 |
|
|
ZY7_QSPI_CONFIG_SSFORCE |
|
|
ZY7_QSPI_CONFIG_PCS |
|
|
ZY7_QSPI_CONFIG_FIFO_WIDTH32 |
|
|
ZY7_QSPI_CONFIG_BAUD_RATE_DIV(baud_div) |
|
|
ZY7_QSPI_CONFIG_MODE_SEL;
|
|
WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
|
|
|
|
/*
|
|
* Set thresholds. We must use 1 for tx threshold because there
|
|
* is no fifo empty flag and we need one to implement a bug
|
|
* workaround.
|
|
*/
|
|
WR4(sc, ZY7_QSPI_TX_THRESH_REG, 1);
|
|
WR4(sc, ZY7_QSPI_RX_THRESH_REG, 1);
|
|
|
|
/* Clear and disable all interrupts. */
|
|
WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0);
|
|
WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0);
|
|
|
|
/* Enable SPI. */
|
|
WR4(sc, ZY7_QSPI_EN_REG, ZY7_SPI_ENABLE);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static void
|
|
zy7_qspi_add_sysctls(device_t dev)
|
|
{
|
|
struct zy7_qspi_softc *sc = device_get_softc(dev);
|
|
struct sysctl_ctx_list *ctx;
|
|
struct sysctl_oid_list *child;
|
|
|
|
ctx = device_get_sysctl_ctx(dev);
|
|
child = SYSCTL_CHILDREN(device_get_sysctl_tree(dev));
|
|
|
|
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "spi_clk_real_freq", CTLFLAG_RD,
|
|
&sc->spi_clk_real_freq, 0, "SPI clock real frequency");
|
|
|
|
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "rx_overflows", CTLFLAG_RD,
|
|
&sc->rx_overflows, 0, "RX FIFO overflow events");
|
|
|
|
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "tx_underflows", CTLFLAG_RD,
|
|
&sc->tx_underflows, 0, "TX FIFO underflow events");
|
|
|
|
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "interrupts", CTLFLAG_RD,
|
|
&sc->interrupts, 0, "interrupt calls");
|
|
|
|
SYSCTL_ADD_UINT(ctx, child, OID_AUTO, "stray_ints", CTLFLAG_RD,
|
|
&sc->stray_ints, 0, "stray interrupts");
|
|
}
|
|
|
|
static int
|
|
zy7_qspi_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
|
|
return (ENXIO);
|
|
|
|
device_set_desc(dev, "Zynq Quad-SPI Flash Controller");
|
|
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
static int
|
|
zy7_qspi_attach(device_t dev)
|
|
{
|
|
struct zy7_qspi_softc *sc;
|
|
int rid, err;
|
|
phandle_t node;
|
|
pcell_t cell;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
QSPI_SC_LOCK_INIT(sc);
|
|
|
|
/* Get ref-clock, spi-clock, and other properties. */
|
|
node = ofw_bus_get_node(dev);
|
|
if (OF_getprop(node, "ref-clock", &cell, sizeof(cell)) > 0)
|
|
sc->ref_clock = fdt32_to_cpu(cell);
|
|
else {
|
|
device_printf(dev, "must have ref-clock property\n");
|
|
return (ENXIO);
|
|
}
|
|
if (OF_getprop(node, "spi-clock", &cell, sizeof(cell)) > 0)
|
|
sc->spi_clock = fdt32_to_cpu(cell);
|
|
else
|
|
sc->spi_clock = ZY7_QSPI_DEFAULT_SPI_CLOCK;
|
|
if (OF_getprop(node, "is-stacked", &cell, sizeof(cell)) > 0 &&
|
|
fdt32_to_cpu(cell) != 0) {
|
|
sc->is_dual = 1;
|
|
sc->is_stacked = 1;
|
|
} else if (OF_getprop(node, "is-dual", &cell, sizeof(cell)) > 0 &&
|
|
fdt32_to_cpu(cell) != 0)
|
|
sc->is_dual = 1;
|
|
if (OF_getprop(node, "is-dio", &cell, sizeof(cell)) > 0 &&
|
|
fdt32_to_cpu(cell) != 0)
|
|
sc->is_dio = 1;
|
|
|
|
/* Get memory resource. */
|
|
rid = 0;
|
|
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->mem_res == NULL) {
|
|
device_printf(dev, "could not allocate memory resources.\n");
|
|
zy7_qspi_detach(dev);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Allocate IRQ. */
|
|
rid = 0;
|
|
sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
|
|
RF_ACTIVE);
|
|
if (sc->irq_res == NULL) {
|
|
device_printf(dev, "could not allocate IRQ resource.\n");
|
|
zy7_qspi_detach(dev);
|
|
return (ENOMEM);
|
|
}
|
|
|
|
/* Activate the interrupt. */
|
|
err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
|
|
NULL, zy7_qspi_intr, sc, &sc->intrhandle);
|
|
if (err) {
|
|
device_printf(dev, "could not setup IRQ.\n");
|
|
zy7_qspi_detach(dev);
|
|
return (err);
|
|
}
|
|
|
|
/* Configure the device. */
|
|
err = zy7_qspi_init_hw(sc);
|
|
if (err) {
|
|
zy7_qspi_detach(dev);
|
|
return (err);
|
|
}
|
|
|
|
sc->child = device_add_child(dev, "spibus", -1);
|
|
|
|
zy7_qspi_add_sysctls(dev);
|
|
|
|
/* Attach spibus driver as a child later when interrupts work. */
|
|
config_intrhook_oneshot((ich_func_t)bus_generic_attach, dev);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static int
|
|
zy7_qspi_detach(device_t dev)
|
|
{
|
|
struct zy7_qspi_softc *sc = device_get_softc(dev);
|
|
|
|
if (device_is_attached(dev))
|
|
bus_generic_detach(dev);
|
|
|
|
/* Delete child bus. */
|
|
if (sc->child)
|
|
device_delete_child(dev, sc->child);
|
|
|
|
/* Disable hardware. */
|
|
if (sc->mem_res != NULL) {
|
|
/* Disable SPI. */
|
|
WR4(sc, ZY7_QSPI_EN_REG, 0);
|
|
|
|
/* Clear and disable all interrupts. */
|
|
WR4(sc, ZY7_QSPI_INTR_STAT_REG, ~0);
|
|
WR4(sc, ZY7_QSPI_INTR_DIS_REG, ~0);
|
|
}
|
|
|
|
/* Teardown and release interrupt. */
|
|
if (sc->irq_res != NULL) {
|
|
if (sc->intrhandle)
|
|
bus_teardown_intr(dev, sc->irq_res, sc->intrhandle);
|
|
bus_release_resource(dev, SYS_RES_IRQ,
|
|
rman_get_rid(sc->irq_res), sc->irq_res);
|
|
}
|
|
|
|
/* Release memory resource. */
|
|
if (sc->mem_res != NULL)
|
|
bus_release_resource(dev, SYS_RES_MEMORY,
|
|
rman_get_rid(sc->mem_res), sc->mem_res);
|
|
|
|
QSPI_SC_LOCK_DESTROY(sc);
|
|
|
|
return (0);
|
|
}
|
|
|
|
static phandle_t
|
|
zy7_qspi_get_node(device_t bus, device_t dev)
|
|
{
|
|
|
|
return (ofw_bus_get_node(bus));
|
|
}
|
|
|
|
static int
|
|
zy7_qspi_transfer(device_t dev, device_t child, struct spi_command *cmd)
|
|
{
|
|
struct zy7_qspi_softc *sc = device_get_softc(dev);
|
|
int err = 0;
|
|
|
|
KASSERT(cmd->tx_cmd_sz == cmd->rx_cmd_sz,
|
|
("TX/RX command sizes should be equal"));
|
|
KASSERT(cmd->tx_data_sz == cmd->rx_data_sz,
|
|
("TX/RX data sizes should be equal"));
|
|
|
|
if (sc->is_dual && cmd->tx_data_sz % 2 != 0) {
|
|
device_printf(dev, "driver does not support odd byte data "
|
|
"transfers in dual mode. (sz=%d)\n", cmd->tx_data_sz);
|
|
return (EINVAL);
|
|
}
|
|
|
|
QSPI_SC_LOCK(sc);
|
|
|
|
/* Wait for controller available. */
|
|
while (sc->busy != 0) {
|
|
err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi0", 0);
|
|
if (err) {
|
|
QSPI_SC_UNLOCK(sc);
|
|
return (err);
|
|
}
|
|
}
|
|
|
|
/* Start transfer. */
|
|
sc->busy = 1;
|
|
sc->cmd = cmd;
|
|
sc->tx_bytes = sc->cmd->tx_cmd_sz + sc->cmd->tx_data_sz;
|
|
sc->tx_bytes_sent = 0;
|
|
sc->rx_bytes = sc->cmd->rx_cmd_sz + sc->cmd->rx_data_sz;
|
|
sc->rx_bytes_rcvd = 0;
|
|
|
|
/* Enable interrupts. zy7_qspi_intr() will handle transfer. */
|
|
WR4(sc, ZY7_QSPI_INTR_EN_REG,
|
|
ZY7_QSPI_INTR_TX_FIFO_NOT_FULL |
|
|
ZY7_QSPI_INTR_RX_OVERFLOW);
|
|
|
|
#ifdef SPI_XFER_U_PAGE /* XXX: future support for stacked memories. */
|
|
if (sc->is_stacked) {
|
|
if ((cmd->flags & SPI_XFER_U_PAGE) != 0)
|
|
sc->lqspi_cfg_shadow |= ZY7_QSPI_LQSPI_CFG_U_PAGE;
|
|
else
|
|
sc->lqspi_cfg_shadow &= ~ZY7_QSPI_LQSPI_CFG_U_PAGE;
|
|
WR4(sc, ZY7_QSPI_LQSPI_CFG_REG, sc->lqspi_cfg_shadow);
|
|
}
|
|
#endif
|
|
|
|
/* Assert CS. */
|
|
sc->cfg_reg_shadow &= ~ZY7_QSPI_CONFIG_PCS;
|
|
WR4(sc, ZY7_QSPI_CONFIG_REG, sc->cfg_reg_shadow);
|
|
|
|
/* Wait for completion. */
|
|
err = mtx_sleep(dev, &sc->sc_mtx, 0, "zqspi1", hz * 2);
|
|
if (err)
|
|
zy7_qspi_abort_transfer(sc);
|
|
|
|
/* Release controller. */
|
|
sc->busy = 0;
|
|
wakeup_one(dev);
|
|
|
|
QSPI_SC_UNLOCK(sc);
|
|
|
|
return (err);
|
|
}
|
|
|
|
static device_method_t zy7_qspi_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, zy7_qspi_probe),
|
|
DEVMETHOD(device_attach, zy7_qspi_attach),
|
|
DEVMETHOD(device_detach, zy7_qspi_detach),
|
|
|
|
/* SPI interface */
|
|
DEVMETHOD(spibus_transfer, zy7_qspi_transfer),
|
|
|
|
/* ofw_bus interface */
|
|
DEVMETHOD(ofw_bus_get_node, zy7_qspi_get_node),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
static driver_t zy7_qspi_driver = {
|
|
"zy7_qspi",
|
|
zy7_qspi_methods,
|
|
sizeof(struct zy7_qspi_softc),
|
|
};
|
|
|
|
DRIVER_MODULE(zy7_qspi, simplebus, zy7_qspi_driver, 0, 0);
|
|
DRIVER_MODULE(ofw_spibus, zy7_qspi, ofw_spibus_driver, 0, 0);
|
|
SIMPLEBUS_PNP_INFO(compat_data);
|
|
MODULE_DEPEND(zy7_qspi, ofw_spibus, 1, 1, 1);
|