72 lines
2.6 KiB
C
72 lines
2.6 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2012-2013 Thomas Skibo
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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/*
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* Address regions of Zynq-7000.
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* Reference: Zynq-7000 All Programmable SoC Technical Reference Manual.
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* (v1.4) November 16, 2012. Xilinx doc UG585.
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*/
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#ifndef _ZY7_REG_H_
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#define _ZY7_REG_H_
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/* PL AXI buses: General Purpose Port #0, M_AXI_GP0. */
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#define ZYNQ7_PLGP0_HWBASE 0x40000000
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#define ZYNQ7_PLGP0_SIZE 0x40000000
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/* PL AXI buses: General Purpose Port #1, M_AXI_GP1. */
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#define ZYNQ7_PLGP1_HWBASE 0x80000000
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#define ZYNQ7_PLGP1_SIZE 0x40000000
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/* I/O Peripheral registers. */
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#define ZYNQ7_PSIO_HWBASE 0xE0000000
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#define ZYNQ7_PSIO_SIZE 0x00300000
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/* UART0 and UART1 */
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#define ZYNQ7_UART0_HWBASE (ZYNQ7_PSIO_HWBASE)
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#define ZYNQ7_UART0_SIZE 0x1000
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#define ZYNQ7_UART1_HWBASE (ZYNQ7_PSIO_HWBASE+0x1000)
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#define ZYNQ7_UART1_SIZE 0x1000
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/* SMC Memories not mapped for now. */
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#define ZYNQ7_SMC_HWBASE 0xE1000000
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#define ZYNQ7_SMC_SIZE 0x05000000
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/* SLCR, PS system, and CPU private registers combined in this region. */
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#define ZYNQ7_PSCTL_HWBASE 0xF8000000
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#define ZYNQ7_PSCTL_SIZE 0x01000000
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#define ZYNQ7_SLCR_HWBASE (ZYNQ7_PSCTL_HWBASE)
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#define ZYNQ7_SLCR_SIZE 0x1000
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#define ZYNQ7_DEVCFG_HWBASE (ZYNQ7_PSCTL_HWBASE+0x7000)
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#define ZYNQ7_DEVCFG_SIZE 0x1000
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#endif /* _ZY7_REG_H_ */
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