a297028904
never actually ran on these chips (other than using SA1 support in an emulator to do the early porting to FreeBSD long long ago). The clutter and complexity of some of this code keeps getting in the way of other maintenance, so it's time to go.
678 lines
20 KiB
C
678 lines
20 KiB
C
/* $NetBSD: cpufunc.h,v 1.29 2003/09/06 09:08:35 rearnsha Exp $ */
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/*-
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* Copyright (c) 1997 Mark Brinicombe.
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* Copyright (c) 1997 Causality Limited
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Causality Limited.
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* 4. The name of Causality Limited may not be used to endorse or promote
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* products derived from this software without specific prior written
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* permission.
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*
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* THIS SOFTWARE IS PROVIDED BY CAUSALITY LIMITED ``AS IS'' AND ANY EXPRESS
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* OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL CAUSALITY LIMITED BE LIABLE FOR ANY DIRECT,
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* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* RiscBSD kernel project
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*
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* cpufunc.h
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*
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* Prototypes for cpu, mmu and tlb related functions.
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*
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPUFUNC_H_
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#define _MACHINE_CPUFUNC_H_
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#ifdef _KERNEL
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#include <sys/types.h>
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#include <machine/cpuconf.h>
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#include <machine/katelib.h> /* For in[bwl] and out[bwl] */
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static __inline void
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breakpoint(void)
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{
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__asm(".word 0xe7ffffff");
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}
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struct cpu_functions {
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/* CPU functions */
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u_int (*cf_id) (void);
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void (*cf_cpwait) (void);
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/* MMU functions */
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u_int (*cf_control) (u_int bic, u_int eor);
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void (*cf_domains) (u_int domains);
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void (*cf_setttb) (u_int ttb);
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u_int (*cf_faultstatus) (void);
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u_int (*cf_faultaddress) (void);
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/* TLB functions */
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void (*cf_tlb_flushID) (void);
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void (*cf_tlb_flushID_SE) (u_int va);
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void (*cf_tlb_flushI) (void);
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void (*cf_tlb_flushI_SE) (u_int va);
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void (*cf_tlb_flushD) (void);
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void (*cf_tlb_flushD_SE) (u_int va);
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/*
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* Cache operations:
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*
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* We define the following primitives:
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*
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* icache_sync_all Synchronize I-cache
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* icache_sync_range Synchronize I-cache range
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*
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* dcache_wbinv_all Write-back and Invalidate D-cache
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* dcache_wbinv_range Write-back and Invalidate D-cache range
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* dcache_inv_range Invalidate D-cache range
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* dcache_wb_range Write-back D-cache range
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*
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* idcache_wbinv_all Write-back and Invalidate D-cache,
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* Invalidate I-cache
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* idcache_wbinv_range Write-back and Invalidate D-cache,
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* Invalidate I-cache range
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*
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* Note that the ARM term for "write-back" is "clean". We use
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* the term "write-back" since it's a more common way to describe
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* the operation.
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*
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* There are some rules that must be followed:
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*
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* ID-cache Invalidate All:
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* Unlike other functions, this one must never write back.
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* It is used to intialize the MMU when it is in an unknown
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* state (such as when it may have lines tagged as valid
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* that belong to a previous set of mappings).
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*
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* I-cache Synch (all or range):
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* The goal is to synchronize the instruction stream,
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* so you may beed to write-back dirty D-cache blocks
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* first. If a range is requested, and you can't
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* synchronize just a range, you have to hit the whole
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* thing.
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*
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* D-cache Write-Back and Invalidate range:
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* If you can't WB-Inv a range, you must WB-Inv the
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* entire D-cache.
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*
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* D-cache Invalidate:
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* If you can't Inv the D-cache, you must Write-Back
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* and Invalidate. Code that uses this operation
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* MUST NOT assume that the D-cache will not be written
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* back to memory.
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*
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* D-cache Write-Back:
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* If you can't Write-back without doing an Inv,
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* that's fine. Then treat this as a WB-Inv.
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* Skipping the invalidate is merely an optimization.
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*
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* All operations:
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* Valid virtual addresses must be passed to each
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* cache operation.
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*/
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void (*cf_icache_sync_all) (void);
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void (*cf_icache_sync_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_wbinv_all) (void);
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void (*cf_dcache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_inv_range) (vm_offset_t, vm_size_t);
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void (*cf_dcache_wb_range) (vm_offset_t, vm_size_t);
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void (*cf_idcache_inv_all) (void);
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void (*cf_idcache_wbinv_all) (void);
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void (*cf_idcache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_wbinv_all) (void);
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void (*cf_l2cache_wbinv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_inv_range) (vm_offset_t, vm_size_t);
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void (*cf_l2cache_wb_range) (vm_offset_t, vm_size_t);
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/* Other functions */
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void (*cf_flush_prefetchbuf) (void);
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void (*cf_drain_writebuf) (void);
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void (*cf_flush_brnchtgt_C) (void);
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void (*cf_flush_brnchtgt_E) (u_int va);
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void (*cf_sleep) (int mode);
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/* Soft functions */
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int (*cf_dataabt_fixup) (void *arg);
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int (*cf_prefetchabt_fixup) (void *arg);
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void (*cf_context_switch) (void);
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void (*cf_setup) (char *string);
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};
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extern struct cpu_functions cpufuncs;
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extern u_int cputype;
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#define cpu_id() cpufuncs.cf_id()
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#define cpu_cpwait() cpufuncs.cf_cpwait()
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#define cpu_control(c, e) cpufuncs.cf_control(c, e)
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#define cpu_domains(d) cpufuncs.cf_domains(d)
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#define cpu_setttb(t) cpufuncs.cf_setttb(t)
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#define cpu_faultstatus() cpufuncs.cf_faultstatus()
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#define cpu_faultaddress() cpufuncs.cf_faultaddress()
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#ifndef SMP
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#define cpu_tlb_flushID() cpufuncs.cf_tlb_flushID()
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#define cpu_tlb_flushID_SE(e) cpufuncs.cf_tlb_flushID_SE(e)
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#define cpu_tlb_flushI() cpufuncs.cf_tlb_flushI()
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#define cpu_tlb_flushI_SE(e) cpufuncs.cf_tlb_flushI_SE(e)
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#define cpu_tlb_flushD() cpufuncs.cf_tlb_flushD()
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#define cpu_tlb_flushD_SE(e) cpufuncs.cf_tlb_flushD_SE(e)
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#else
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void tlb_broadcast(int);
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#if defined(CPU_CORTEXA) || defined(CPU_MV_PJ4B) || defined(CPU_KRAIT)
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#define TLB_BROADCAST /* No need to explicitely send an IPI */
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#else
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#define TLB_BROADCAST tlb_broadcast(7)
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#endif
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#define cpu_tlb_flushID() do { \
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cpufuncs.cf_tlb_flushID(); \
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TLB_BROADCAST; \
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} while(0)
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#define cpu_tlb_flushID_SE(e) do { \
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cpufuncs.cf_tlb_flushID_SE(e); \
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TLB_BROADCAST; \
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} while(0)
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#define cpu_tlb_flushI() do { \
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cpufuncs.cf_tlb_flushI(); \
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TLB_BROADCAST; \
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} while(0)
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#define cpu_tlb_flushI_SE(e) do { \
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cpufuncs.cf_tlb_flushI_SE(e); \
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TLB_BROADCAST; \
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} while(0)
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#define cpu_tlb_flushD() do { \
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cpufuncs.cf_tlb_flushD(); \
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TLB_BROADCAST; \
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} while(0)
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#define cpu_tlb_flushD_SE(e) do { \
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cpufuncs.cf_tlb_flushD_SE(e); \
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TLB_BROADCAST; \
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} while(0)
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#endif
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#define cpu_icache_sync_all() cpufuncs.cf_icache_sync_all()
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#define cpu_icache_sync_range(a, s) cpufuncs.cf_icache_sync_range((a), (s))
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#define cpu_dcache_wbinv_all() cpufuncs.cf_dcache_wbinv_all()
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#define cpu_dcache_wbinv_range(a, s) cpufuncs.cf_dcache_wbinv_range((a), (s))
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#define cpu_dcache_inv_range(a, s) cpufuncs.cf_dcache_inv_range((a), (s))
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#define cpu_dcache_wb_range(a, s) cpufuncs.cf_dcache_wb_range((a), (s))
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#define cpu_idcache_inv_all() cpufuncs.cf_idcache_inv_all()
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#define cpu_idcache_wbinv_all() cpufuncs.cf_idcache_wbinv_all()
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#define cpu_idcache_wbinv_range(a, s) cpufuncs.cf_idcache_wbinv_range((a), (s))
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#define cpu_l2cache_wbinv_all() cpufuncs.cf_l2cache_wbinv_all()
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#define cpu_l2cache_wb_range(a, s) cpufuncs.cf_l2cache_wb_range((a), (s))
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#define cpu_l2cache_inv_range(a, s) cpufuncs.cf_l2cache_inv_range((a), (s))
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#define cpu_l2cache_wbinv_range(a, s) cpufuncs.cf_l2cache_wbinv_range((a), (s))
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#define cpu_flush_prefetchbuf() cpufuncs.cf_flush_prefetchbuf()
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#define cpu_drain_writebuf() cpufuncs.cf_drain_writebuf()
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#define cpu_flush_brnchtgt_C() cpufuncs.cf_flush_brnchtgt_C()
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#define cpu_flush_brnchtgt_E(e) cpufuncs.cf_flush_brnchtgt_E(e)
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#define cpu_sleep(m) cpufuncs.cf_sleep(m)
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#define cpu_dataabt_fixup(a) cpufuncs.cf_dataabt_fixup(a)
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#define cpu_prefetchabt_fixup(a) cpufuncs.cf_prefetchabt_fixup(a)
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#define ABORT_FIXUP_OK 0 /* fixup succeeded */
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#define ABORT_FIXUP_FAILED 1 /* fixup failed */
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#define ABORT_FIXUP_RETURN 2 /* abort handler should return */
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#define cpu_setup(a) cpufuncs.cf_setup(a)
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int set_cpufuncs (void);
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#define ARCHITECTURE_NOT_PRESENT 1 /* known but not configured */
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#define ARCHITECTURE_NOT_SUPPORTED 2 /* not known */
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void cpufunc_nullop (void);
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int cpufunc_null_fixup (void *);
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int early_abort_fixup (void *);
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int late_abort_fixup (void *);
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u_int cpufunc_id (void);
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u_int cpufunc_cpuid (void);
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u_int cpufunc_control (u_int clear, u_int bic);
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void cpufunc_domains (u_int domains);
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u_int cpufunc_faultstatus (void);
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u_int cpufunc_faultaddress (void);
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u_int cpu_pfr (int);
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#if defined(CPU_FA526) || defined(CPU_FA626TE)
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void fa526_setup (char *arg);
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void fa526_setttb (u_int ttb);
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void fa526_context_switch (void);
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void fa526_cpu_sleep (int);
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void fa526_tlb_flushI_SE (u_int);
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void fa526_tlb_flushID_SE (u_int);
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void fa526_flush_prefetchbuf (void);
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void fa526_flush_brnchtgt_E (u_int);
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void fa526_icache_sync_all (void);
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void fa526_icache_sync_range(vm_offset_t start, vm_size_t end);
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void fa526_dcache_wbinv_all (void);
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void fa526_dcache_wbinv_range(vm_offset_t start, vm_size_t end);
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void fa526_dcache_inv_range (vm_offset_t start, vm_size_t end);
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void fa526_dcache_wb_range (vm_offset_t start, vm_size_t end);
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void fa526_idcache_wbinv_all(void);
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void fa526_idcache_wbinv_range(vm_offset_t start, vm_size_t end);
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#endif
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#ifdef CPU_ARM9
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void arm9_setttb (u_int);
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void arm9_tlb_flushID_SE (u_int va);
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void arm9_icache_sync_all (void);
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void arm9_icache_sync_range (vm_offset_t, vm_size_t);
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void arm9_dcache_wbinv_all (void);
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void arm9_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm9_dcache_inv_range (vm_offset_t, vm_size_t);
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void arm9_dcache_wb_range (vm_offset_t, vm_size_t);
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void arm9_idcache_wbinv_all (void);
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void arm9_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm9_context_switch (void);
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void arm9_setup (char *string);
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extern unsigned arm9_dcache_sets_max;
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extern unsigned arm9_dcache_sets_inc;
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extern unsigned arm9_dcache_index_max;
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extern unsigned arm9_dcache_index_inc;
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#endif
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#if defined(CPU_ARM9E) || defined(CPU_ARM10)
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void arm10_setttb (u_int);
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void arm10_tlb_flushID_SE (u_int);
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void arm10_tlb_flushI_SE (u_int);
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void arm10_icache_sync_all (void);
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void arm10_icache_sync_range (vm_offset_t, vm_size_t);
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void arm10_dcache_wbinv_all (void);
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void arm10_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm10_dcache_inv_range (vm_offset_t, vm_size_t);
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void arm10_dcache_wb_range (vm_offset_t, vm_size_t);
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void arm10_idcache_wbinv_all (void);
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void arm10_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void arm10_context_switch (void);
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void arm10_setup (char *string);
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extern unsigned arm10_dcache_sets_max;
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extern unsigned arm10_dcache_sets_inc;
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extern unsigned arm10_dcache_index_max;
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extern unsigned arm10_dcache_index_inc;
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u_int sheeva_control_ext (u_int, u_int);
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void sheeva_cpu_sleep (int);
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void sheeva_setttb (u_int);
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void sheeva_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_dcache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wbinv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_inv_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wb_range (vm_offset_t, vm_size_t);
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void sheeva_l2cache_wbinv_all (void);
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#endif
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#if defined(CPU_ARM1136) || defined(CPU_ARM1176) || \
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defined(CPU_MV_PJ4B) || defined(CPU_CORTEXA) || defined(CPU_KRAIT)
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void arm11_setttb (u_int);
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void arm11_sleep (int);
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void arm11_tlb_flushID_SE (u_int);
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void arm11_tlb_flushI_SE (u_int);
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void arm11_context_switch (void);
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void arm11_setup (char *string);
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void arm11_tlb_flushID (void);
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void arm11_tlb_flushI (void);
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void arm11_tlb_flushD (void);
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void arm11_tlb_flushD_SE (u_int va);
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void arm11_drain_writebuf (void);
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void pj4b_setttb (u_int);
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void pj4b_drain_readbuf (void);
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void pj4b_flush_brnchtgt_all (void);
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void pj4b_flush_brnchtgt_va (u_int);
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void pj4b_sleep (int);
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void armv6_icache_sync_all (void);
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void armv6_icache_sync_range (vm_offset_t, vm_size_t);
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void armv6_dcache_wbinv_all (void);
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void armv6_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv6_dcache_inv_range (vm_offset_t, vm_size_t);
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void armv6_dcache_wb_range (vm_offset_t, vm_size_t);
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void armv6_idcache_inv_all (void);
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void armv6_idcache_wbinv_all (void);
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void armv6_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv7_setttb (u_int);
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void armv7_tlb_flushID (void);
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void armv7_tlb_flushID_SE (u_int);
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void armv7_icache_sync_range (vm_offset_t, vm_size_t);
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void armv7_idcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv7_idcache_inv_all (void);
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void armv7_dcache_wbinv_all (void);
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void armv7_idcache_wbinv_all (void);
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void armv7_dcache_wbinv_range (vm_offset_t, vm_size_t);
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void armv7_dcache_inv_range (vm_offset_t, vm_size_t);
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void armv7_dcache_wb_range (vm_offset_t, vm_size_t);
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void armv7_cpu_sleep (int);
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void armv7_setup (char *string);
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void armv7_context_switch (void);
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void armv7_drain_writebuf (void);
|
|
void armv7_sev (void);
|
|
void armv7_sleep (int unused);
|
|
u_int armv7_auxctrl (u_int, u_int);
|
|
void pj4bv7_setup (char *string);
|
|
void pj4b_config (void);
|
|
|
|
int get_core_id (void);
|
|
|
|
void armadaxp_idcache_wbinv_all (void);
|
|
|
|
void cortexa_setup (char *);
|
|
#endif
|
|
|
|
#if defined(CPU_ARM1136) || defined(CPU_ARM1176)
|
|
void arm11x6_setttb (u_int);
|
|
void arm11x6_idcache_wbinv_all (void);
|
|
void arm11x6_dcache_wbinv_all (void);
|
|
void arm11x6_icache_sync_all (void);
|
|
void arm11x6_flush_prefetchbuf (void);
|
|
void arm11x6_icache_sync_range (vm_offset_t, vm_size_t);
|
|
void arm11x6_idcache_wbinv_range (vm_offset_t, vm_size_t);
|
|
void arm11x6_setup (char *string);
|
|
void arm11x6_sleep (int); /* no ref. for errata */
|
|
#endif
|
|
#if defined(CPU_ARM1136)
|
|
void arm1136_sleep_rev0 (int); /* for errata 336501 */
|
|
#endif
|
|
|
|
#if defined(CPU_ARM9E) || defined (CPU_ARM10)
|
|
void armv5_ec_setttb(u_int);
|
|
|
|
void armv5_ec_icache_sync_all(void);
|
|
void armv5_ec_icache_sync_range(vm_offset_t, vm_size_t);
|
|
|
|
void armv5_ec_dcache_wbinv_all(void);
|
|
void armv5_ec_dcache_wbinv_range(vm_offset_t, vm_size_t);
|
|
void armv5_ec_dcache_inv_range(vm_offset_t, vm_size_t);
|
|
void armv5_ec_dcache_wb_range(vm_offset_t, vm_size_t);
|
|
|
|
void armv5_ec_idcache_wbinv_all(void);
|
|
void armv5_ec_idcache_wbinv_range(vm_offset_t, vm_size_t);
|
|
#endif
|
|
|
|
#if defined (CPU_ARM10)
|
|
void armv5_setttb(u_int);
|
|
|
|
void armv5_icache_sync_all(void);
|
|
void armv5_icache_sync_range(vm_offset_t, vm_size_t);
|
|
|
|
void armv5_dcache_wbinv_all(void);
|
|
void armv5_dcache_wbinv_range(vm_offset_t, vm_size_t);
|
|
void armv5_dcache_inv_range(vm_offset_t, vm_size_t);
|
|
void armv5_dcache_wb_range(vm_offset_t, vm_size_t);
|
|
|
|
void armv5_idcache_wbinv_all(void);
|
|
void armv5_idcache_wbinv_range(vm_offset_t, vm_size_t);
|
|
|
|
extern unsigned armv5_dcache_sets_max;
|
|
extern unsigned armv5_dcache_sets_inc;
|
|
extern unsigned armv5_dcache_index_max;
|
|
extern unsigned armv5_dcache_index_inc;
|
|
#endif
|
|
|
|
#if defined(CPU_ARM9) || defined(CPU_ARM9E) || defined(CPU_ARM10) || \
|
|
defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
|
|
defined(CPU_FA526) || defined(CPU_FA626TE) || \
|
|
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
|
|
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
|
|
|
|
void armv4_tlb_flushID (void);
|
|
void armv4_tlb_flushI (void);
|
|
void armv4_tlb_flushD (void);
|
|
void armv4_tlb_flushD_SE (u_int va);
|
|
|
|
void armv4_drain_writebuf (void);
|
|
void armv4_idcache_inv_all (void);
|
|
#endif
|
|
|
|
#if defined(CPU_XSCALE_80200) || defined(CPU_XSCALE_80321) || \
|
|
defined(CPU_XSCALE_PXA2X0) || defined(CPU_XSCALE_IXP425) || \
|
|
defined(CPU_XSCALE_80219) || defined(CPU_XSCALE_81342)
|
|
void xscale_cpwait (void);
|
|
|
|
void xscale_cpu_sleep (int mode);
|
|
|
|
u_int xscale_control (u_int clear, u_int bic);
|
|
|
|
void xscale_setttb (u_int ttb);
|
|
|
|
void xscale_tlb_flushID_SE (u_int va);
|
|
|
|
void xscale_cache_flushID (void);
|
|
void xscale_cache_flushI (void);
|
|
void xscale_cache_flushD (void);
|
|
void xscale_cache_flushD_SE (u_int entry);
|
|
|
|
void xscale_cache_cleanID (void);
|
|
void xscale_cache_cleanD (void);
|
|
void xscale_cache_cleanD_E (u_int entry);
|
|
|
|
void xscale_cache_clean_minidata (void);
|
|
|
|
void xscale_cache_purgeID (void);
|
|
void xscale_cache_purgeID_E (u_int entry);
|
|
void xscale_cache_purgeD (void);
|
|
void xscale_cache_purgeD_E (u_int entry);
|
|
|
|
void xscale_cache_syncI (void);
|
|
void xscale_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
|
|
void xscale_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
|
|
void xscale_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
|
|
void xscale_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
|
|
void xscale_cache_syncI_rng (vm_offset_t start, vm_size_t end);
|
|
void xscale_cache_flushD_rng (vm_offset_t start, vm_size_t end);
|
|
|
|
void xscale_context_switch (void);
|
|
|
|
void xscale_setup (char *string);
|
|
#endif /* CPU_XSCALE_80200 || CPU_XSCALE_80321 || CPU_XSCALE_PXA2X0 || CPU_XSCALE_IXP425
|
|
CPU_XSCALE_80219 */
|
|
|
|
#ifdef CPU_XSCALE_81342
|
|
|
|
void xscalec3_l2cache_purge (void);
|
|
void xscalec3_cache_purgeID (void);
|
|
void xscalec3_cache_purgeD (void);
|
|
void xscalec3_cache_cleanID (void);
|
|
void xscalec3_cache_cleanD (void);
|
|
void xscalec3_cache_syncI (void);
|
|
|
|
void xscalec3_cache_purgeID_rng (vm_offset_t start, vm_size_t end);
|
|
void xscalec3_cache_purgeD_rng (vm_offset_t start, vm_size_t end);
|
|
void xscalec3_cache_cleanID_rng (vm_offset_t start, vm_size_t end);
|
|
void xscalec3_cache_cleanD_rng (vm_offset_t start, vm_size_t end);
|
|
void xscalec3_cache_syncI_rng (vm_offset_t start, vm_size_t end);
|
|
|
|
void xscalec3_l2cache_flush_rng (vm_offset_t, vm_size_t);
|
|
void xscalec3_l2cache_clean_rng (vm_offset_t start, vm_size_t end);
|
|
void xscalec3_l2cache_purge_rng (vm_offset_t start, vm_size_t end);
|
|
|
|
|
|
void xscalec3_setttb (u_int ttb);
|
|
void xscalec3_context_switch (void);
|
|
|
|
#endif /* CPU_XSCALE_81342 */
|
|
|
|
#define tlb_flush cpu_tlb_flushID
|
|
#define setttb cpu_setttb
|
|
#define drain_writebuf cpu_drain_writebuf
|
|
|
|
/*
|
|
* Macros for manipulating CPU interrupts
|
|
*/
|
|
static __inline u_int32_t __set_cpsr_c(u_int bic, u_int eor) __attribute__((__unused__));
|
|
|
|
static __inline u_int32_t
|
|
__set_cpsr_c(u_int bic, u_int eor)
|
|
{
|
|
u_int32_t tmp, ret;
|
|
|
|
__asm __volatile(
|
|
"mrs %0, cpsr\n" /* Get the CPSR */
|
|
"bic %1, %0, %2\n" /* Clear bits */
|
|
"eor %1, %1, %3\n" /* XOR bits */
|
|
"msr cpsr_c, %1\n" /* Set the control field of CPSR */
|
|
: "=&r" (ret), "=&r" (tmp)
|
|
: "r" (bic), "r" (eor) : "memory");
|
|
|
|
return ret;
|
|
}
|
|
|
|
#define ARM_CPSR_F32 (1 << 6) /* FIQ disable */
|
|
#define ARM_CPSR_I32 (1 << 7) /* IRQ disable */
|
|
|
|
#define disable_interrupts(mask) \
|
|
(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), \
|
|
(mask) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
|
|
|
|
#define enable_interrupts(mask) \
|
|
(__set_cpsr_c((mask) & (ARM_CPSR_I32 | ARM_CPSR_F32), 0))
|
|
|
|
#define restore_interrupts(old_cpsr) \
|
|
(__set_cpsr_c((ARM_CPSR_I32 | ARM_CPSR_F32), \
|
|
(old_cpsr) & (ARM_CPSR_I32 | ARM_CPSR_F32)))
|
|
|
|
static __inline register_t
|
|
intr_disable(void)
|
|
{
|
|
register_t s;
|
|
|
|
s = disable_interrupts(ARM_CPSR_I32 | ARM_CPSR_F32);
|
|
return (s);
|
|
}
|
|
|
|
static __inline void
|
|
intr_restore(register_t s)
|
|
{
|
|
|
|
restore_interrupts(s);
|
|
}
|
|
|
|
/* Functions to manipulate the CPSR. */
|
|
u_int SetCPSR(u_int bic, u_int eor);
|
|
u_int GetCPSR(void);
|
|
|
|
/*
|
|
* Functions to manipulate cpu r13
|
|
* (in arm/arm32/setstack.S)
|
|
*/
|
|
|
|
void set_stackptr (u_int mode, u_int address);
|
|
u_int get_stackptr (u_int mode);
|
|
|
|
/*
|
|
* Miscellany
|
|
*/
|
|
|
|
int get_pc_str_offset (void);
|
|
|
|
/*
|
|
* CPU functions from locore.S
|
|
*/
|
|
|
|
void cpu_reset (void) __attribute__((__noreturn__));
|
|
|
|
/*
|
|
* Cache info variables.
|
|
*/
|
|
|
|
/* PRIMARY CACHE VARIABLES */
|
|
extern int arm_picache_size;
|
|
extern int arm_picache_line_size;
|
|
extern int arm_picache_ways;
|
|
|
|
extern int arm_pdcache_size; /* and unified */
|
|
extern int arm_pdcache_line_size;
|
|
extern int arm_pdcache_ways;
|
|
|
|
extern int arm_pcache_type;
|
|
extern int arm_pcache_unified;
|
|
|
|
extern int arm_dcache_align;
|
|
extern int arm_dcache_align_mask;
|
|
|
|
extern u_int arm_cache_level;
|
|
extern u_int arm_cache_loc;
|
|
extern u_int arm_cache_type[14];
|
|
|
|
#endif /* _KERNEL */
|
|
#endif /* _MACHINE_CPUFUNC_H_ */
|
|
|
|
/* End of cpufunc.h */
|