e4fc3b653a
We also update the kernel view early in the boot. This will allow the use of the common kernel view in ifunc resolvers. Sponsored by: Innovate UK
214 lines
6.8 KiB
C
214 lines
6.8 KiB
C
/*-
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* Copyright (c) 1990 The Regents of the University of California.
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* Copyright (c) 2014-2016 The FreeBSD Foundation
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Portions of this software were developed by Andrew Turner
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* under sponsorship from the FreeBSD Foundation
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: @(#)cpu.h 5.4 (Berkeley) 5/9/91
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* from: FreeBSD: src/sys/i386/include/cpu.h,v 1.62 2001/06/29
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* $FreeBSD$
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*/
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#ifndef _MACHINE_CPU_H_
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#define _MACHINE_CPU_H_
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#include <machine/atomic.h>
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#include <machine/frame.h>
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#include <machine/armreg.h>
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#define TRAPF_PC(tfp) ((tfp)->tf_lr)
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#define TRAPF_USERMODE(tfp) (((tfp)->tf_spsr & PSR_M_MASK) == PSR_M_EL0t)
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#define cpu_getstack(td) ((td)->td_frame->tf_sp)
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#define cpu_setstack(td, sp) ((td)->td_frame->tf_sp = (sp))
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#define cpu_spinwait() __asm __volatile("yield" ::: "memory")
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#define cpu_lock_delay() DELAY(1)
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/* Extract CPU affinity levels 0-3 */
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#define CPU_AFF0(mpidr) (u_int)(((mpidr) >> 0) & 0xff)
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#define CPU_AFF1(mpidr) (u_int)(((mpidr) >> 8) & 0xff)
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#define CPU_AFF2(mpidr) (u_int)(((mpidr) >> 16) & 0xff)
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#define CPU_AFF3(mpidr) (u_int)(((mpidr) >> 32) & 0xff)
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#define CPU_AFF0_MASK 0xffUL
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#define CPU_AFF1_MASK 0xff00UL
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#define CPU_AFF2_MASK 0xff0000UL
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#define CPU_AFF3_MASK 0xff00000000UL
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#define CPU_AFF_MASK (CPU_AFF0_MASK | CPU_AFF1_MASK | \
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CPU_AFF2_MASK| CPU_AFF3_MASK) /* Mask affinity fields in MPIDR_EL1 */
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#ifdef _KERNEL
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#define CPU_IMPL_ARM 0x41
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#define CPU_IMPL_BROADCOM 0x42
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#define CPU_IMPL_CAVIUM 0x43
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#define CPU_IMPL_DEC 0x44
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#define CPU_IMPL_INFINEON 0x49
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#define CPU_IMPL_FREESCALE 0x4D
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#define CPU_IMPL_NVIDIA 0x4E
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#define CPU_IMPL_APM 0x50
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#define CPU_IMPL_QUALCOMM 0x51
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#define CPU_IMPL_MARVELL 0x56
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#define CPU_IMPL_INTEL 0x69
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/* ARM Part numbers */
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#define CPU_PART_FOUNDATION 0xD00
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#define CPU_PART_CORTEX_A53 0xD03
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#define CPU_PART_CORTEX_A35 0xD04
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#define CPU_PART_CORTEX_A55 0xD05
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#define CPU_PART_CORTEX_A65 0xD06
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#define CPU_PART_CORTEX_A57 0xD07
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#define CPU_PART_CORTEX_A72 0xD08
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#define CPU_PART_CORTEX_A73 0xD09
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#define CPU_PART_CORTEX_A75 0xD0A
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#define CPU_PART_CORTEX_A76 0xD0B
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#define CPU_PART_NEOVERSE_N1 0xD0C
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#define CPU_PART_CORTEX_A77 0xD0D
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#define CPU_PART_CORTEX_A76AE 0xD0E
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/* Cavium Part numbers */
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#define CPU_PART_THUNDERX 0x0A1
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#define CPU_PART_THUNDERX_81XX 0x0A2
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#define CPU_PART_THUNDERX_83XX 0x0A3
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#define CPU_PART_THUNDERX2 0x0AF
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#define CPU_REV_THUNDERX_1_0 0x00
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#define CPU_REV_THUNDERX_1_1 0x01
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#define CPU_REV_THUNDERX2_0 0x00
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/* APM / Ampere Part Number */
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#define CPU_PART_EMAG8180 0x000
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#define CPU_IMPL(midr) (((midr) >> 24) & 0xff)
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#define CPU_PART(midr) (((midr) >> 4) & 0xfff)
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#define CPU_VAR(midr) (((midr) >> 20) & 0xf)
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#define CPU_REV(midr) (((midr) >> 0) & 0xf)
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#define CPU_IMPL_TO_MIDR(val) (((val) & 0xff) << 24)
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#define CPU_PART_TO_MIDR(val) (((val) & 0xfff) << 4)
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#define CPU_VAR_TO_MIDR(val) (((val) & 0xf) << 20)
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#define CPU_REV_TO_MIDR(val) (((val) & 0xf) << 0)
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#define CPU_IMPL_MASK (0xff << 24)
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#define CPU_PART_MASK (0xfff << 4)
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#define CPU_VAR_MASK (0xf << 20)
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#define CPU_REV_MASK (0xf << 0)
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#define CPU_ID_RAW(impl, part, var, rev) \
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(CPU_IMPL_TO_MIDR((impl)) | \
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CPU_PART_TO_MIDR((part)) | CPU_VAR_TO_MIDR((var)) | \
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CPU_REV_TO_MIDR((rev)))
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#define CPU_MATCH(mask, impl, part, var, rev) \
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(((mask) & PCPU_GET(midr)) == \
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((mask) & CPU_ID_RAW((impl), (part), (var), (rev))))
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#define CPU_MATCH_RAW(mask, devid) \
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(((mask) & PCPU_GET(midr)) == ((mask) & (devid)))
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/*
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* Chip-specific errata. This defines are intended to be
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* booleans used within if statements. When an appropriate
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* kernel option is disabled, these defines must be defined
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* as 0 to allow the compiler to remove a dead code thus
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* produce better optimized kernel image.
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*/
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/*
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* Vendor: Cavium
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* Chip: ThunderX
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* Revision(s): Pass 1.0, Pass 1.1
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*/
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#ifdef THUNDERX_PASS_1_1_ERRATA
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#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 \
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(CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
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CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_0) || \
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CPU_MATCH(CPU_IMPL_MASK | CPU_PART_MASK | CPU_REV_MASK, \
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CPU_IMPL_CAVIUM, CPU_PART_THUNDERX, 0, CPU_REV_THUNDERX_1_1))
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#else
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#define CPU_MATCH_ERRATA_CAVIUM_THUNDERX_1_1 0
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#endif
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extern char btext[];
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extern char etext[];
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extern uint64_t __cpu_affinity[];
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void cpu_halt(void) __dead2;
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void cpu_reset(void) __dead2;
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void fork_trampoline(void);
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void identify_cache(uint64_t);
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void identify_cpu(u_int);
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void install_cpu_errata(void);
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void swi_vm(void *v);
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/* Functions to read the sanitised view of the special registers */
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void update_special_regs(u_int);
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bool extract_user_id_field(u_int, u_int, uint8_t *);
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bool get_kernel_reg(u_int, uint64_t *);
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#define CPU_AFFINITY(cpu) __cpu_affinity[(cpu)]
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#define CPU_CURRENT_SOCKET \
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(CPU_AFF2(CPU_AFFINITY(PCPU_GET(cpuid))))
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static __inline uint64_t
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get_cyclecount(void)
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{
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uint64_t ret;
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ret = READ_SPECIALREG(cntvct_el0);
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return (ret);
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}
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#define ADDRESS_TRANSLATE_FUNC(stage) \
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static inline uint64_t \
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arm64_address_translate_ ##stage (uint64_t addr) \
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{ \
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uint64_t ret; \
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\
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__asm __volatile( \
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"at " __STRING(stage) ", %1 \n" \
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"mrs %0, par_el1" : "=r"(ret) : "r"(addr)); \
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\
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return (ret); \
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}
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ADDRESS_TRANSLATE_FUNC(s1e0r)
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ADDRESS_TRANSLATE_FUNC(s1e0w)
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ADDRESS_TRANSLATE_FUNC(s1e1r)
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ADDRESS_TRANSLATE_FUNC(s1e1w)
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#endif
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#endif /* !_MACHINE_CPU_H_ */
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